1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass VEMCRegisterClasses[];
17
18namespace VE {
19enum : unsigned {
20 NoRegister,
21 IC = 1,
22 PMMR = 2,
23 PSW = 3,
24 SAR = 4,
25 USRCC = 5,
26 VIX = 6,
27 VL = 7,
28 PMC0 = 8,
29 PMC1 = 9,
30 PMC2 = 10,
31 PMC3 = 11,
32 PMC4 = 12,
33 PMC5 = 13,
34 PMC6 = 14,
35 PMC7 = 15,
36 PMC8 = 16,
37 PMC9 = 17,
38 PMC10 = 18,
39 PMC11 = 19,
40 PMC12 = 20,
41 PMC13 = 21,
42 PMC14 = 22,
43 PMCR0 = 23,
44 PMCR1 = 24,
45 PMCR2 = 25,
46 PMCR3 = 26,
47 Q0 = 27,
48 Q1 = 28,
49 Q2 = 29,
50 Q3 = 30,
51 Q4 = 31,
52 Q5 = 32,
53 Q6 = 33,
54 Q7 = 34,
55 Q8 = 35,
56 Q9 = 36,
57 Q10 = 37,
58 Q11 = 38,
59 Q12 = 39,
60 Q13 = 40,
61 Q14 = 41,
62 Q15 = 42,
63 Q16 = 43,
64 Q17 = 44,
65 Q18 = 45,
66 Q19 = 46,
67 Q20 = 47,
68 Q21 = 48,
69 Q22 = 49,
70 Q23 = 50,
71 Q24 = 51,
72 Q25 = 52,
73 Q26 = 53,
74 Q27 = 54,
75 Q28 = 55,
76 Q29 = 56,
77 Q30 = 57,
78 Q31 = 58,
79 SF0 = 59,
80 SF1 = 60,
81 SF2 = 61,
82 SF3 = 62,
83 SF4 = 63,
84 SF5 = 64,
85 SF6 = 65,
86 SF7 = 66,
87 SF8 = 67,
88 SF9 = 68,
89 SF10 = 69,
90 SF11 = 70,
91 SF12 = 71,
92 SF13 = 72,
93 SF14 = 73,
94 SF15 = 74,
95 SF16 = 75,
96 SF17 = 76,
97 SF18 = 77,
98 SF19 = 78,
99 SF20 = 79,
100 SF21 = 80,
101 SF22 = 81,
102 SF23 = 82,
103 SF24 = 83,
104 SF25 = 84,
105 SF26 = 85,
106 SF27 = 86,
107 SF28 = 87,
108 SF29 = 88,
109 SF30 = 89,
110 SF31 = 90,
111 SF32 = 91,
112 SF33 = 92,
113 SF34 = 93,
114 SF35 = 94,
115 SF36 = 95,
116 SF37 = 96,
117 SF38 = 97,
118 SF39 = 98,
119 SF40 = 99,
120 SF41 = 100,
121 SF42 = 101,
122 SF43 = 102,
123 SF44 = 103,
124 SF45 = 104,
125 SF46 = 105,
126 SF47 = 106,
127 SF48 = 107,
128 SF49 = 108,
129 SF50 = 109,
130 SF51 = 110,
131 SF52 = 111,
132 SF53 = 112,
133 SF54 = 113,
134 SF55 = 114,
135 SF56 = 115,
136 SF57 = 116,
137 SF58 = 117,
138 SF59 = 118,
139 SF60 = 119,
140 SF61 = 120,
141 SF62 = 121,
142 SF63 = 122,
143 SW0 = 123,
144 SW1 = 124,
145 SW2 = 125,
146 SW3 = 126,
147 SW4 = 127,
148 SW5 = 128,
149 SW6 = 129,
150 SW7 = 130,
151 SW8 = 131,
152 SW9 = 132,
153 SW10 = 133,
154 SW11 = 134,
155 SW12 = 135,
156 SW13 = 136,
157 SW14 = 137,
158 SW15 = 138,
159 SW16 = 139,
160 SW17 = 140,
161 SW18 = 141,
162 SW19 = 142,
163 SW20 = 143,
164 SW21 = 144,
165 SW22 = 145,
166 SW23 = 146,
167 SW24 = 147,
168 SW25 = 148,
169 SW26 = 149,
170 SW27 = 150,
171 SW28 = 151,
172 SW29 = 152,
173 SW30 = 153,
174 SW31 = 154,
175 SW32 = 155,
176 SW33 = 156,
177 SW34 = 157,
178 SW35 = 158,
179 SW36 = 159,
180 SW37 = 160,
181 SW38 = 161,
182 SW39 = 162,
183 SW40 = 163,
184 SW41 = 164,
185 SW42 = 165,
186 SW43 = 166,
187 SW44 = 167,
188 SW45 = 168,
189 SW46 = 169,
190 SW47 = 170,
191 SW48 = 171,
192 SW49 = 172,
193 SW50 = 173,
194 SW51 = 174,
195 SW52 = 175,
196 SW53 = 176,
197 SW54 = 177,
198 SW55 = 178,
199 SW56 = 179,
200 SW57 = 180,
201 SW58 = 181,
202 SW59 = 182,
203 SW60 = 183,
204 SW61 = 184,
205 SW62 = 185,
206 SW63 = 186,
207 SX0 = 187,
208 SX1 = 188,
209 SX2 = 189,
210 SX3 = 190,
211 SX4 = 191,
212 SX5 = 192,
213 SX6 = 193,
214 SX7 = 194,
215 SX8 = 195,
216 SX9 = 196,
217 SX10 = 197,
218 SX11 = 198,
219 SX12 = 199,
220 SX13 = 200,
221 SX14 = 201,
222 SX15 = 202,
223 SX16 = 203,
224 SX17 = 204,
225 SX18 = 205,
226 SX19 = 206,
227 SX20 = 207,
228 SX21 = 208,
229 SX22 = 209,
230 SX23 = 210,
231 SX24 = 211,
232 SX25 = 212,
233 SX26 = 213,
234 SX27 = 214,
235 SX28 = 215,
236 SX29 = 216,
237 SX30 = 217,
238 SX31 = 218,
239 SX32 = 219,
240 SX33 = 220,
241 SX34 = 221,
242 SX35 = 222,
243 SX36 = 223,
244 SX37 = 224,
245 SX38 = 225,
246 SX39 = 226,
247 SX40 = 227,
248 SX41 = 228,
249 SX42 = 229,
250 SX43 = 230,
251 SX44 = 231,
252 SX45 = 232,
253 SX46 = 233,
254 SX47 = 234,
255 SX48 = 235,
256 SX49 = 236,
257 SX50 = 237,
258 SX51 = 238,
259 SX52 = 239,
260 SX53 = 240,
261 SX54 = 241,
262 SX55 = 242,
263 SX56 = 243,
264 SX57 = 244,
265 SX58 = 245,
266 SX59 = 246,
267 SX60 = 247,
268 SX61 = 248,
269 SX62 = 249,
270 SX63 = 250,
271 V0 = 251,
272 V1 = 252,
273 V2 = 253,
274 V3 = 254,
275 V4 = 255,
276 V5 = 256,
277 V6 = 257,
278 V7 = 258,
279 V8 = 259,
280 V9 = 260,
281 V10 = 261,
282 V11 = 262,
283 V12 = 263,
284 V13 = 264,
285 V14 = 265,
286 V15 = 266,
287 V16 = 267,
288 V17 = 268,
289 V18 = 269,
290 V19 = 270,
291 V20 = 271,
292 V21 = 272,
293 V22 = 273,
294 V23 = 274,
295 V24 = 275,
296 V25 = 276,
297 V26 = 277,
298 V27 = 278,
299 V28 = 279,
300 V29 = 280,
301 V30 = 281,
302 V31 = 282,
303 V32 = 283,
304 V33 = 284,
305 V34 = 285,
306 V35 = 286,
307 V36 = 287,
308 V37 = 288,
309 V38 = 289,
310 V39 = 290,
311 V40 = 291,
312 V41 = 292,
313 V42 = 293,
314 V43 = 294,
315 V44 = 295,
316 V45 = 296,
317 V46 = 297,
318 V47 = 298,
319 V48 = 299,
320 V49 = 300,
321 V50 = 301,
322 V51 = 302,
323 V52 = 303,
324 V53 = 304,
325 V54 = 305,
326 V55 = 306,
327 V56 = 307,
328 V57 = 308,
329 V58 = 309,
330 V59 = 310,
331 V60 = 311,
332 V61 = 312,
333 V62 = 313,
334 V63 = 314,
335 VM0 = 315,
336 VM1 = 316,
337 VM2 = 317,
338 VM3 = 318,
339 VM4 = 319,
340 VM5 = 320,
341 VM6 = 321,
342 VM7 = 322,
343 VM8 = 323,
344 VM9 = 324,
345 VM10 = 325,
346 VM11 = 326,
347 VM12 = 327,
348 VM13 = 328,
349 VM14 = 329,
350 VM15 = 330,
351 VMP0 = 331,
352 VMP1 = 332,
353 VMP2 = 333,
354 VMP3 = 334,
355 VMP4 = 335,
356 VMP5 = 336,
357 VMP6 = 337,
358 VMP7 = 338,
359 NUM_TARGET_REGS // 339
360};
361} // end namespace VE
362
363// Register classes
364
365namespace VE {
366enum {
367 F32RegClassID = 0,
368 I32RegClassID = 1,
369 VLSRegClassID = 2,
370 I64RegClassID = 3,
371 MISCRegClassID = 4,
372 F128RegClassID = 5,
373 VMRegClassID = 6,
374 VM512RegClassID = 7,
375 VM512_with_sub_vm_evenRegClassID = 8,
376 V64RegClassID = 9,
377
378};
379} // end namespace VE
380
381
382// Register alternate name indices
383
384namespace VE {
385enum {
386 AsmName, // 0
387 NoRegAltName, // 1
388 NUM_TARGET_REG_ALT_NAMES = 2
389};
390} // end namespace VE
391
392
393// Subregister indices
394
395namespace VE {
396enum : uint16_t {
397 NoSubRegister,
398 sub_even, // 1
399 sub_f32, // 2
400 sub_i32, // 3
401 sub_odd, // 4
402 sub_vm_even, // 5
403 sub_vm_odd, // 6
404 sub_odd_then_sub_f32, // 7
405 sub_odd_then_sub_i32, // 8
406 NUM_TARGET_SUBREGS
407};
408} // end namespace VE
409
410// Register pressure sets enum.
411namespace VE {
412enum RegisterPressureSets {
413 VLS = 0,
414 VM512 = 1,
415 VM = 2,
416 VM_with_VM512 = 3,
417 MISC = 4,
418 V64 = 5,
419 F32 = 6,
420 I32 = 7,
421 I64 = 8,
422};
423} // end namespace VE
424
425} // end namespace llvm
426
427#endif // GET_REGINFO_ENUM
428
429/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
430|* *|
431|* MC Register Information *|
432|* *|
433|* Automatically generated file, do not edit! *|
434|* *|
435\*===----------------------------------------------------------------------===*/
436
437
438#ifdef GET_REGINFO_MC_DESC
439#undef GET_REGINFO_MC_DESC
440
441namespace llvm {
442
443extern const int16_t VERegDiffLists[] = {
444 /* 0 */ 64, -192, 0,
445 /* 3 */ 128, -192, 0,
446 /* 6 */ 64, -191, 0,
447 /* 9 */ 128, -191, 0,
448 /* 12 */ 64, -190, 0,
449 /* 15 */ 128, -190, 0,
450 /* 18 */ 64, -189, 0,
451 /* 21 */ 128, -189, 0,
452 /* 24 */ 64, -188, 0,
453 /* 27 */ 128, -188, 0,
454 /* 30 */ 64, -187, 0,
455 /* 33 */ 128, -187, 0,
456 /* 36 */ 64, -186, 0,
457 /* 39 */ 128, -186, 0,
458 /* 42 */ 64, -185, 0,
459 /* 45 */ 128, -185, 0,
460 /* 48 */ 64, -184, 0,
461 /* 51 */ 128, -184, 0,
462 /* 54 */ 64, -183, 0,
463 /* 57 */ 128, -183, 0,
464 /* 60 */ 64, -182, 0,
465 /* 63 */ 128, -182, 0,
466 /* 66 */ 64, -181, 0,
467 /* 69 */ 128, -181, 0,
468 /* 72 */ 64, -180, 0,
469 /* 75 */ 128, -180, 0,
470 /* 78 */ 64, -179, 0,
471 /* 81 */ 128, -179, 0,
472 /* 84 */ 64, -178, 0,
473 /* 87 */ 128, -178, 0,
474 /* 90 */ 64, -177, 0,
475 /* 93 */ 128, -177, 0,
476 /* 96 */ 64, -176, 0,
477 /* 99 */ 128, -176, 0,
478 /* 102 */ 64, -175, 0,
479 /* 105 */ 128, -175, 0,
480 /* 108 */ 64, -174, 0,
481 /* 111 */ 128, -174, 0,
482 /* 114 */ 64, -173, 0,
483 /* 117 */ 128, -173, 0,
484 /* 120 */ 64, -172, 0,
485 /* 123 */ 128, -172, 0,
486 /* 126 */ 64, -171, 0,
487 /* 129 */ 128, -171, 0,
488 /* 132 */ 64, -170, 0,
489 /* 135 */ 128, -170, 0,
490 /* 138 */ 64, -169, 0,
491 /* 141 */ 128, -169, 0,
492 /* 144 */ 64, -168, 0,
493 /* 147 */ 128, -168, 0,
494 /* 150 */ 64, -167, 0,
495 /* 153 */ 128, -167, 0,
496 /* 156 */ 64, -166, 0,
497 /* 159 */ 128, -166, 0,
498 /* 162 */ 64, -165, 0,
499 /* 165 */ 128, -165, 0,
500 /* 168 */ 64, -164, 0,
501 /* 171 */ 128, -164, 0,
502 /* 174 */ 64, -163, 0,
503 /* 177 */ 128, -163, 0,
504 /* 180 */ 64, -162, 0,
505 /* 183 */ 128, -162, 0,
506 /* 186 */ 64, -161, 0,
507 /* 189 */ 128, -161, 0,
508 /* 192 */ 64, -160, 0,
509 /* 195 */ 128, -160, 0,
510 /* 198 */ 160, -64, -64, 129, -64, -64, 0,
511 /* 205 */ 161, -64, -64, 129, -64, -64, 0,
512 /* 212 */ 162, -64, -64, 129, -64, -64, 0,
513 /* 219 */ 163, -64, -64, 129, -64, -64, 0,
514 /* 226 */ 164, -64, -64, 129, -64, -64, 0,
515 /* 233 */ 165, -64, -64, 129, -64, -64, 0,
516 /* 240 */ 166, -64, -64, 129, -64, -64, 0,
517 /* 247 */ 167, -64, -64, 129, -64, -64, 0,
518 /* 254 */ 168, -64, -64, 129, -64, -64, 0,
519 /* 261 */ 169, -64, -64, 129, -64, -64, 0,
520 /* 268 */ 170, -64, -64, 129, -64, -64, 0,
521 /* 275 */ 171, -64, -64, 129, -64, -64, 0,
522 /* 282 */ 172, -64, -64, 129, -64, -64, 0,
523 /* 289 */ 173, -64, -64, 129, -64, -64, 0,
524 /* 296 */ 174, -64, -64, 129, -64, -64, 0,
525 /* 303 */ 175, -64, -64, 129, -64, -64, 0,
526 /* 310 */ 176, -64, -64, 129, -64, -64, 0,
527 /* 317 */ 177, -64, -64, 129, -64, -64, 0,
528 /* 324 */ 178, -64, -64, 129, -64, -64, 0,
529 /* 331 */ 179, -64, -64, 129, -64, -64, 0,
530 /* 338 */ 180, -64, -64, 129, -64, -64, 0,
531 /* 345 */ 181, -64, -64, 129, -64, -64, 0,
532 /* 352 */ 182, -64, -64, 129, -64, -64, 0,
533 /* 359 */ 183, -64, -64, 129, -64, -64, 0,
534 /* 366 */ 184, -64, -64, 129, -64, -64, 0,
535 /* 373 */ 185, -64, -64, 129, -64, -64, 0,
536 /* 380 */ 186, -64, -64, 129, -64, -64, 0,
537 /* 387 */ 187, -64, -64, 129, -64, -64, 0,
538 /* 394 */ 188, -64, -64, 129, -64, -64, 0,
539 /* 401 */ 189, -64, -64, 129, -64, -64, 0,
540 /* 408 */ 190, -64, -64, 129, -64, -64, 0,
541 /* 415 */ 191, -64, -64, 129, -64, -64, 0,
542 /* 422 */ -15, 1, 0,
543 /* 425 */ -14, 1, 0,
544 /* 428 */ -13, 1, 0,
545 /* 431 */ -12, 1, 0,
546 /* 434 */ -11, 1, 0,
547 /* 437 */ -10, 1, 0,
548 /* 440 */ -9, 1, 0,
549 /* 443 */ 1, 1, 1, 1, 1, 0,
550 /* 449 */ 8, 0,
551 /* 451 */ 9, 0,
552 /* 453 */ 10, 0,
553 /* 455 */ 11, 0,
554 /* 457 */ 12, 0,
555 /* 459 */ 13, 0,
556 /* 461 */ 14, 0,
557 /* 463 */ 15, 0,
558};
559
560extern const LaneBitmask VELaneMaskLists[] = {
561 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000000), LaneBitmask(0x0000000000000001),
562 /* 3 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
563 /* 5 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000000), LaneBitmask(0x0000000000000010),
564 /* 11 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF),
565};
566
567extern const uint16_t VESubRegIdxLists[] = {
568 /* 0 */ 3, 2,
569 /* 2 */ 5, 6,
570 /* 4 */ 1, 3, 2, 4, 8, 7,
571};
572
573
574#ifdef __GNUC__
575#pragma GCC diagnostic push
576#pragma GCC diagnostic ignored "-Woverlength-strings"
577#endif
578extern const char VERegStrings[] = {
579 /* 0 */ "PMC10\000"
580 /* 6 */ "SF10\000"
581 /* 11 */ "VM10\000"
582 /* 16 */ "Q10\000"
583 /* 20 */ "V10\000"
584 /* 24 */ "SW10\000"
585 /* 29 */ "SX10\000"
586 /* 34 */ "SF20\000"
587 /* 39 */ "Q20\000"
588 /* 43 */ "V20\000"
589 /* 47 */ "SW20\000"
590 /* 52 */ "SX20\000"
591 /* 57 */ "SF30\000"
592 /* 62 */ "Q30\000"
593 /* 66 */ "V30\000"
594 /* 70 */ "SW30\000"
595 /* 75 */ "SX30\000"
596 /* 80 */ "SF40\000"
597 /* 85 */ "V40\000"
598 /* 89 */ "SW40\000"
599 /* 94 */ "SX40\000"
600 /* 99 */ "SF50\000"
601 /* 104 */ "V50\000"
602 /* 108 */ "SW50\000"
603 /* 113 */ "SX50\000"
604 /* 118 */ "SF60\000"
605 /* 123 */ "V60\000"
606 /* 127 */ "SW60\000"
607 /* 132 */ "SX60\000"
608 /* 137 */ "PMC0\000"
609 /* 142 */ "SF0\000"
610 /* 146 */ "VM0\000"
611 /* 150 */ "VMP0\000"
612 /* 155 */ "Q0\000"
613 /* 158 */ "PMCR0\000"
614 /* 164 */ "V0\000"
615 /* 167 */ "SW0\000"
616 /* 171 */ "SX0\000"
617 /* 175 */ "PMC11\000"
618 /* 181 */ "SF11\000"
619 /* 186 */ "VM11\000"
620 /* 191 */ "Q11\000"
621 /* 195 */ "V11\000"
622 /* 199 */ "SW11\000"
623 /* 204 */ "SX11\000"
624 /* 209 */ "SF21\000"
625 /* 214 */ "Q21\000"
626 /* 218 */ "V21\000"
627 /* 222 */ "SW21\000"
628 /* 227 */ "SX21\000"
629 /* 232 */ "SF31\000"
630 /* 237 */ "Q31\000"
631 /* 241 */ "V31\000"
632 /* 245 */ "SW31\000"
633 /* 250 */ "SX31\000"
634 /* 255 */ "SF41\000"
635 /* 260 */ "V41\000"
636 /* 264 */ "SW41\000"
637 /* 269 */ "SX41\000"
638 /* 274 */ "SF51\000"
639 /* 279 */ "V51\000"
640 /* 283 */ "SW51\000"
641 /* 288 */ "SX51\000"
642 /* 293 */ "SF61\000"
643 /* 298 */ "V61\000"
644 /* 302 */ "SW61\000"
645 /* 307 */ "SX61\000"
646 /* 312 */ "PMC1\000"
647 /* 317 */ "SF1\000"
648 /* 321 */ "VM1\000"
649 /* 325 */ "VMP1\000"
650 /* 330 */ "Q1\000"
651 /* 333 */ "PMCR1\000"
652 /* 339 */ "V1\000"
653 /* 342 */ "SW1\000"
654 /* 346 */ "SX1\000"
655 /* 350 */ "PMC12\000"
656 /* 356 */ "SF12\000"
657 /* 361 */ "VM12\000"
658 /* 366 */ "Q12\000"
659 /* 370 */ "V12\000"
660 /* 374 */ "SW12\000"
661 /* 379 */ "SX12\000"
662 /* 384 */ "SF22\000"
663 /* 389 */ "Q22\000"
664 /* 393 */ "V22\000"
665 /* 397 */ "SW22\000"
666 /* 402 */ "SX22\000"
667 /* 407 */ "SF32\000"
668 /* 412 */ "V32\000"
669 /* 416 */ "SW32\000"
670 /* 421 */ "SX32\000"
671 /* 426 */ "SF42\000"
672 /* 431 */ "V42\000"
673 /* 435 */ "SW42\000"
674 /* 440 */ "SX42\000"
675 /* 445 */ "SF52\000"
676 /* 450 */ "V52\000"
677 /* 454 */ "SW52\000"
678 /* 459 */ "SX52\000"
679 /* 464 */ "SF62\000"
680 /* 469 */ "V62\000"
681 /* 473 */ "SW62\000"
682 /* 478 */ "SX62\000"
683 /* 483 */ "PMC2\000"
684 /* 488 */ "SF2\000"
685 /* 492 */ "VM2\000"
686 /* 496 */ "VMP2\000"
687 /* 501 */ "Q2\000"
688 /* 504 */ "PMCR2\000"
689 /* 510 */ "V2\000"
690 /* 513 */ "SW2\000"
691 /* 517 */ "SX2\000"
692 /* 521 */ "PMC13\000"
693 /* 527 */ "SF13\000"
694 /* 532 */ "VM13\000"
695 /* 537 */ "Q13\000"
696 /* 541 */ "V13\000"
697 /* 545 */ "SW13\000"
698 /* 550 */ "SX13\000"
699 /* 555 */ "SF23\000"
700 /* 560 */ "Q23\000"
701 /* 564 */ "V23\000"
702 /* 568 */ "SW23\000"
703 /* 573 */ "SX23\000"
704 /* 578 */ "SF33\000"
705 /* 583 */ "V33\000"
706 /* 587 */ "SW33\000"
707 /* 592 */ "SX33\000"
708 /* 597 */ "SF43\000"
709 /* 602 */ "V43\000"
710 /* 606 */ "SW43\000"
711 /* 611 */ "SX43\000"
712 /* 616 */ "SF53\000"
713 /* 621 */ "V53\000"
714 /* 625 */ "SW53\000"
715 /* 630 */ "SX53\000"
716 /* 635 */ "SF63\000"
717 /* 640 */ "V63\000"
718 /* 644 */ "SW63\000"
719 /* 649 */ "SX63\000"
720 /* 654 */ "PMC3\000"
721 /* 659 */ "SF3\000"
722 /* 663 */ "VM3\000"
723 /* 667 */ "VMP3\000"
724 /* 672 */ "Q3\000"
725 /* 675 */ "PMCR3\000"
726 /* 681 */ "V3\000"
727 /* 684 */ "SW3\000"
728 /* 688 */ "SX3\000"
729 /* 692 */ "PMC14\000"
730 /* 698 */ "SF14\000"
731 /* 703 */ "VM14\000"
732 /* 708 */ "Q14\000"
733 /* 712 */ "V14\000"
734 /* 716 */ "SW14\000"
735 /* 721 */ "SX14\000"
736 /* 726 */ "SF24\000"
737 /* 731 */ "Q24\000"
738 /* 735 */ "V24\000"
739 /* 739 */ "SW24\000"
740 /* 744 */ "SX24\000"
741 /* 749 */ "SF34\000"
742 /* 754 */ "V34\000"
743 /* 758 */ "SW34\000"
744 /* 763 */ "SX34\000"
745 /* 768 */ "SF44\000"
746 /* 773 */ "V44\000"
747 /* 777 */ "SW44\000"
748 /* 782 */ "SX44\000"
749 /* 787 */ "SF54\000"
750 /* 792 */ "V54\000"
751 /* 796 */ "SW54\000"
752 /* 801 */ "SX54\000"
753 /* 806 */ "PMC4\000"
754 /* 811 */ "SF4\000"
755 /* 815 */ "VM4\000"
756 /* 819 */ "VMP4\000"
757 /* 824 */ "Q4\000"
758 /* 827 */ "V4\000"
759 /* 830 */ "SW4\000"
760 /* 834 */ "SX4\000"
761 /* 838 */ "SF15\000"
762 /* 843 */ "VM15\000"
763 /* 848 */ "Q15\000"
764 /* 852 */ "V15\000"
765 /* 856 */ "SW15\000"
766 /* 861 */ "SX15\000"
767 /* 866 */ "SF25\000"
768 /* 871 */ "Q25\000"
769 /* 875 */ "V25\000"
770 /* 879 */ "SW25\000"
771 /* 884 */ "SX25\000"
772 /* 889 */ "SF35\000"
773 /* 894 */ "V35\000"
774 /* 898 */ "SW35\000"
775 /* 903 */ "SX35\000"
776 /* 908 */ "SF45\000"
777 /* 913 */ "V45\000"
778 /* 917 */ "SW45\000"
779 /* 922 */ "SX45\000"
780 /* 927 */ "SF55\000"
781 /* 932 */ "V55\000"
782 /* 936 */ "SW55\000"
783 /* 941 */ "SX55\000"
784 /* 946 */ "PMC5\000"
785 /* 951 */ "SF5\000"
786 /* 955 */ "VM5\000"
787 /* 959 */ "VMP5\000"
788 /* 964 */ "Q5\000"
789 /* 967 */ "V5\000"
790 /* 970 */ "SW5\000"
791 /* 974 */ "SX5\000"
792 /* 978 */ "SF16\000"
793 /* 983 */ "Q16\000"
794 /* 987 */ "V16\000"
795 /* 991 */ "SW16\000"
796 /* 996 */ "SX16\000"
797 /* 1001 */ "SF26\000"
798 /* 1006 */ "Q26\000"
799 /* 1010 */ "V26\000"
800 /* 1014 */ "SW26\000"
801 /* 1019 */ "SX26\000"
802 /* 1024 */ "SF36\000"
803 /* 1029 */ "V36\000"
804 /* 1033 */ "SW36\000"
805 /* 1038 */ "SX36\000"
806 /* 1043 */ "SF46\000"
807 /* 1048 */ "V46\000"
808 /* 1052 */ "SW46\000"
809 /* 1057 */ "SX46\000"
810 /* 1062 */ "SF56\000"
811 /* 1067 */ "V56\000"
812 /* 1071 */ "SW56\000"
813 /* 1076 */ "SX56\000"
814 /* 1081 */ "PMC6\000"
815 /* 1086 */ "SF6\000"
816 /* 1090 */ "VM6\000"
817 /* 1094 */ "VMP6\000"
818 /* 1099 */ "Q6\000"
819 /* 1102 */ "V6\000"
820 /* 1105 */ "SW6\000"
821 /* 1109 */ "SX6\000"
822 /* 1113 */ "SF17\000"
823 /* 1118 */ "Q17\000"
824 /* 1122 */ "V17\000"
825 /* 1126 */ "SW17\000"
826 /* 1131 */ "SX17\000"
827 /* 1136 */ "SF27\000"
828 /* 1141 */ "Q27\000"
829 /* 1145 */ "V27\000"
830 /* 1149 */ "SW27\000"
831 /* 1154 */ "SX27\000"
832 /* 1159 */ "SF37\000"
833 /* 1164 */ "V37\000"
834 /* 1168 */ "SW37\000"
835 /* 1173 */ "SX37\000"
836 /* 1178 */ "SF47\000"
837 /* 1183 */ "V47\000"
838 /* 1187 */ "SW47\000"
839 /* 1192 */ "SX47\000"
840 /* 1197 */ "SF57\000"
841 /* 1202 */ "V57\000"
842 /* 1206 */ "SW57\000"
843 /* 1211 */ "SX57\000"
844 /* 1216 */ "PMC7\000"
845 /* 1221 */ "SF7\000"
846 /* 1225 */ "VM7\000"
847 /* 1229 */ "VMP7\000"
848 /* 1234 */ "Q7\000"
849 /* 1237 */ "V7\000"
850 /* 1240 */ "SW7\000"
851 /* 1244 */ "SX7\000"
852 /* 1248 */ "SF18\000"
853 /* 1253 */ "Q18\000"
854 /* 1257 */ "V18\000"
855 /* 1261 */ "SW18\000"
856 /* 1266 */ "SX18\000"
857 /* 1271 */ "SF28\000"
858 /* 1276 */ "Q28\000"
859 /* 1280 */ "V28\000"
860 /* 1284 */ "SW28\000"
861 /* 1289 */ "SX28\000"
862 /* 1294 */ "SF38\000"
863 /* 1299 */ "V38\000"
864 /* 1303 */ "SW38\000"
865 /* 1308 */ "SX38\000"
866 /* 1313 */ "SF48\000"
867 /* 1318 */ "V48\000"
868 /* 1322 */ "SW48\000"
869 /* 1327 */ "SX48\000"
870 /* 1332 */ "SF58\000"
871 /* 1337 */ "V58\000"
872 /* 1341 */ "SW58\000"
873 /* 1346 */ "SX58\000"
874 /* 1351 */ "PMC8\000"
875 /* 1356 */ "SF8\000"
876 /* 1360 */ "VM8\000"
877 /* 1364 */ "Q8\000"
878 /* 1367 */ "V8\000"
879 /* 1370 */ "SW8\000"
880 /* 1374 */ "SX8\000"
881 /* 1378 */ "SF19\000"
882 /* 1383 */ "Q19\000"
883 /* 1387 */ "V19\000"
884 /* 1391 */ "SW19\000"
885 /* 1396 */ "SX19\000"
886 /* 1401 */ "SF29\000"
887 /* 1406 */ "Q29\000"
888 /* 1410 */ "V29\000"
889 /* 1414 */ "SW29\000"
890 /* 1419 */ "SX29\000"
891 /* 1424 */ "SF39\000"
892 /* 1429 */ "V39\000"
893 /* 1433 */ "SW39\000"
894 /* 1438 */ "SX39\000"
895 /* 1443 */ "SF49\000"
896 /* 1448 */ "V49\000"
897 /* 1452 */ "SW49\000"
898 /* 1457 */ "SX49\000"
899 /* 1462 */ "SF59\000"
900 /* 1467 */ "V59\000"
901 /* 1471 */ "SW59\000"
902 /* 1476 */ "SX59\000"
903 /* 1481 */ "PMC9\000"
904 /* 1486 */ "SF9\000"
905 /* 1490 */ "VM9\000"
906 /* 1494 */ "Q9\000"
907 /* 1497 */ "V9\000"
908 /* 1500 */ "SW9\000"
909 /* 1504 */ "SX9\000"
910 /* 1508 */ "USRCC\000"
911 /* 1514 */ "IC\000"
912 /* 1517 */ "VL\000"
913 /* 1520 */ "SAR\000"
914 /* 1524 */ "PMMR\000"
915 /* 1529 */ "PSW\000"
916 /* 1533 */ "VIX\000"
917};
918#ifdef __GNUC__
919#pragma GCC diagnostic pop
920#endif
921
922extern const MCRegisterDesc VERegDesc[] = { // Descriptors
923 { 5, 0, 0, 0, 0, 0, 0, 0 },
924 { 1514, 2, 2, 2, 8192, 12, 0, 0 },
925 { 1524, 2, 2, 2, 8193, 12, 0, 0 },
926 { 1529, 2, 2, 2, 8194, 12, 0, 0 },
927 { 1520, 2, 2, 2, 8195, 12, 0, 0 },
928 { 1508, 2, 2, 2, 8196, 12, 0, 0 },
929 { 1533, 2, 2, 2, 8197, 12, 0, 0 },
930 { 1517, 2, 2, 2, 8198, 12, 0, 0 },
931 { 137, 2, 2, 2, 8199, 12, 0, 0 },
932 { 312, 2, 2, 2, 8200, 12, 0, 0 },
933 { 483, 2, 2, 2, 8201, 12, 0, 0 },
934 { 654, 2, 2, 2, 8202, 12, 0, 0 },
935 { 806, 2, 2, 2, 8203, 12, 0, 0 },
936 { 946, 2, 2, 2, 8204, 12, 0, 0 },
937 { 1081, 2, 2, 2, 8205, 12, 0, 0 },
938 { 1216, 2, 2, 2, 8206, 12, 0, 0 },
939 { 1351, 2, 2, 2, 8207, 12, 0, 0 },
940 { 1481, 2, 2, 2, 8208, 12, 0, 0 },
941 { 0, 2, 2, 2, 8209, 12, 0, 0 },
942 { 175, 2, 2, 2, 8210, 12, 0, 0 },
943 { 350, 2, 2, 2, 8211, 12, 0, 0 },
944 { 521, 2, 2, 2, 8212, 12, 0, 0 },
945 { 692, 2, 2, 2, 8213, 12, 0, 0 },
946 { 158, 2, 2, 2, 8214, 12, 0, 0 },
947 { 333, 2, 2, 2, 8215, 12, 0, 0 },
948 { 504, 2, 2, 2, 8216, 12, 0, 0 },
949 { 675, 2, 2, 2, 8217, 12, 0, 0 },
950 { 155, 198, 2, 4, 1814554, 5, 0, 0 },
951 { 330, 205, 2, 4, 1814560, 5, 0, 0 },
952 { 501, 212, 2, 4, 1814566, 5, 0, 0 },
953 { 672, 219, 2, 4, 1814572, 5, 0, 0 },
954 { 824, 226, 2, 4, 1814578, 5, 0, 0 },
955 { 964, 233, 2, 4, 1814584, 5, 0, 0 },
956 { 1099, 240, 2, 4, 1814590, 5, 0, 0 },
957 { 1234, 247, 2, 4, 1814596, 5, 0, 0 },
958 { 1364, 254, 2, 4, 1814602, 5, 0, 0 },
959 { 1494, 261, 2, 4, 1814608, 5, 0, 0 },
960 { 16, 268, 2, 4, 1814614, 5, 0, 0 },
961 { 191, 275, 2, 4, 1814620, 5, 0, 0 },
962 { 366, 282, 2, 4, 1814626, 5, 0, 0 },
963 { 537, 289, 2, 4, 1814632, 5, 0, 0 },
964 { 708, 296, 2, 4, 1814638, 5, 0, 0 },
965 { 848, 303, 2, 4, 1814644, 5, 0, 0 },
966 { 983, 310, 2, 4, 1814650, 5, 0, 0 },
967 { 1118, 317, 2, 4, 1814656, 5, 0, 0 },
968 { 1253, 324, 2, 4, 1814662, 5, 0, 0 },
969 { 1383, 331, 2, 4, 1814668, 5, 0, 0 },
970 { 39, 338, 2, 4, 1814674, 5, 0, 0 },
971 { 214, 345, 2, 4, 1814680, 5, 0, 0 },
972 { 389, 352, 2, 4, 1814686, 5, 0, 0 },
973 { 560, 359, 2, 4, 1814692, 5, 0, 0 },
974 { 731, 366, 2, 4, 1814698, 5, 0, 0 },
975 { 871, 373, 2, 4, 1814704, 5, 0, 0 },
976 { 1006, 380, 2, 4, 1814710, 5, 0, 0 },
977 { 1141, 387, 2, 4, 1814716, 5, 0, 0 },
978 { 1276, 394, 2, 4, 1814722, 5, 0, 0 },
979 { 1406, 401, 2, 4, 1814728, 5, 0, 0 },
980 { 62, 408, 2, 4, 1814734, 5, 0, 0 },
981 { 237, 415, 2, 4, 1814740, 5, 0, 0 },
982 { 142, 2, 195, 2, 1732635, 11, 0, 0 },
983 { 317, 2, 189, 2, 1732638, 11, 0, 0 },
984 { 488, 2, 189, 2, 1732641, 11, 0, 0 },
985 { 659, 2, 183, 2, 1732644, 11, 0, 0 },
986 { 811, 2, 183, 2, 1732647, 11, 0, 0 },
987 { 951, 2, 177, 2, 1732650, 11, 0, 0 },
988 { 1086, 2, 177, 2, 1732653, 11, 0, 0 },
989 { 1221, 2, 171, 2, 1732656, 11, 0, 0 },
990 { 1356, 2, 171, 2, 1732659, 11, 0, 0 },
991 { 1486, 2, 165, 2, 1732662, 11, 0, 0 },
992 { 6, 2, 165, 2, 1732665, 11, 0, 0 },
993 { 181, 2, 159, 2, 1732668, 11, 0, 0 },
994 { 356, 2, 159, 2, 1732671, 11, 0, 0 },
995 { 527, 2, 153, 2, 1732674, 11, 0, 0 },
996 { 698, 2, 153, 2, 1732677, 11, 0, 0 },
997 { 838, 2, 147, 2, 1732680, 11, 0, 0 },
998 { 978, 2, 147, 2, 1732683, 11, 0, 0 },
999 { 1113, 2, 141, 2, 1732686, 11, 0, 0 },
1000 { 1248, 2, 141, 2, 1732689, 11, 0, 0 },
1001 { 1378, 2, 135, 2, 1732692, 11, 0, 0 },
1002 { 34, 2, 135, 2, 1732695, 11, 0, 0 },
1003 { 209, 2, 129, 2, 1732698, 11, 0, 0 },
1004 { 384, 2, 129, 2, 1732701, 11, 0, 0 },
1005 { 555, 2, 123, 2, 1732704, 11, 0, 0 },
1006 { 726, 2, 123, 2, 1732707, 11, 0, 0 },
1007 { 866, 2, 117, 2, 1732710, 11, 0, 0 },
1008 { 1001, 2, 117, 2, 1732713, 11, 0, 0 },
1009 { 1136, 2, 111, 2, 1732716, 11, 0, 0 },
1010 { 1271, 2, 111, 2, 1732719, 11, 0, 0 },
1011 { 1401, 2, 105, 2, 1732722, 11, 0, 0 },
1012 { 57, 2, 105, 2, 1732725, 11, 0, 0 },
1013 { 232, 2, 99, 2, 1732728, 11, 0, 0 },
1014 { 407, 2, 99, 2, 1732731, 11, 0, 0 },
1015 { 578, 2, 93, 2, 1732734, 11, 0, 0 },
1016 { 749, 2, 93, 2, 1732737, 11, 0, 0 },
1017 { 889, 2, 87, 2, 1732740, 11, 0, 0 },
1018 { 1024, 2, 87, 2, 1732743, 11, 0, 0 },
1019 { 1159, 2, 81, 2, 1732746, 11, 0, 0 },
1020 { 1294, 2, 81, 2, 1732749, 11, 0, 0 },
1021 { 1424, 2, 75, 2, 1732752, 11, 0, 0 },
1022 { 80, 2, 75, 2, 1732755, 11, 0, 0 },
1023 { 255, 2, 69, 2, 1732758, 11, 0, 0 },
1024 { 426, 2, 69, 2, 1732761, 11, 0, 0 },
1025 { 597, 2, 63, 2, 1732764, 11, 0, 0 },
1026 { 768, 2, 63, 2, 1732767, 11, 0, 0 },
1027 { 908, 2, 57, 2, 1732770, 11, 0, 0 },
1028 { 1043, 2, 57, 2, 1732773, 11, 0, 0 },
1029 { 1178, 2, 51, 2, 1732776, 11, 0, 0 },
1030 { 1313, 2, 51, 2, 1732779, 11, 0, 0 },
1031 { 1443, 2, 45, 2, 1732782, 11, 0, 0 },
1032 { 99, 2, 45, 2, 1732785, 11, 0, 0 },
1033 { 274, 2, 39, 2, 1732788, 11, 0, 0 },
1034 { 445, 2, 39, 2, 1732791, 11, 0, 0 },
1035 { 616, 2, 33, 2, 1732794, 11, 0, 0 },
1036 { 787, 2, 33, 2, 1732797, 11, 0, 0 },
1037 { 927, 2, 27, 2, 1732800, 11, 0, 0 },
1038 { 1062, 2, 27, 2, 1732803, 11, 0, 0 },
1039 { 1197, 2, 21, 2, 1732806, 11, 0, 0 },
1040 { 1332, 2, 21, 2, 1732809, 11, 0, 0 },
1041 { 1462, 2, 15, 2, 1732812, 11, 0, 0 },
1042 { 118, 2, 15, 2, 1732815, 11, 0, 0 },
1043 { 293, 2, 9, 2, 1732818, 11, 0, 0 },
1044 { 464, 2, 9, 2, 1732821, 11, 0, 0 },
1045 { 635, 2, 3, 2, 1732824, 11, 0, 0 },
1046 { 167, 2, 192, 2, 1732634, 11, 0, 0 },
1047 { 342, 2, 186, 2, 1732637, 11, 0, 0 },
1048 { 513, 2, 186, 2, 1732640, 11, 0, 0 },
1049 { 684, 2, 180, 2, 1732643, 11, 0, 0 },
1050 { 830, 2, 180, 2, 1732646, 11, 0, 0 },
1051 { 970, 2, 174, 2, 1732649, 11, 0, 0 },
1052 { 1105, 2, 174, 2, 1732652, 11, 0, 0 },
1053 { 1240, 2, 168, 2, 1732655, 11, 0, 0 },
1054 { 1370, 2, 168, 2, 1732658, 11, 0, 0 },
1055 { 1500, 2, 162, 2, 1732661, 11, 0, 0 },
1056 { 24, 2, 162, 2, 1732664, 11, 0, 0 },
1057 { 199, 2, 156, 2, 1732667, 11, 0, 0 },
1058 { 374, 2, 156, 2, 1732670, 11, 0, 0 },
1059 { 545, 2, 150, 2, 1732673, 11, 0, 0 },
1060 { 716, 2, 150, 2, 1732676, 11, 0, 0 },
1061 { 856, 2, 144, 2, 1732679, 11, 0, 0 },
1062 { 991, 2, 144, 2, 1732682, 11, 0, 0 },
1063 { 1126, 2, 138, 2, 1732685, 11, 0, 0 },
1064 { 1261, 2, 138, 2, 1732688, 11, 0, 0 },
1065 { 1391, 2, 132, 2, 1732691, 11, 0, 0 },
1066 { 47, 2, 132, 2, 1732694, 11, 0, 0 },
1067 { 222, 2, 126, 2, 1732697, 11, 0, 0 },
1068 { 397, 2, 126, 2, 1732700, 11, 0, 0 },
1069 { 568, 2, 120, 2, 1732703, 11, 0, 0 },
1070 { 739, 2, 120, 2, 1732706, 11, 0, 0 },
1071 { 879, 2, 114, 2, 1732709, 11, 0, 0 },
1072 { 1014, 2, 114, 2, 1732712, 11, 0, 0 },
1073 { 1149, 2, 108, 2, 1732715, 11, 0, 0 },
1074 { 1284, 2, 108, 2, 1732718, 11, 0, 0 },
1075 { 1414, 2, 102, 2, 1732721, 11, 0, 0 },
1076 { 70, 2, 102, 2, 1732724, 11, 0, 0 },
1077 { 245, 2, 96, 2, 1732727, 11, 0, 0 },
1078 { 416, 2, 96, 2, 1732730, 11, 0, 0 },
1079 { 587, 2, 90, 2, 1732733, 11, 0, 0 },
1080 { 758, 2, 90, 2, 1732736, 11, 0, 0 },
1081 { 898, 2, 84, 2, 1732739, 11, 0, 0 },
1082 { 1033, 2, 84, 2, 1732742, 11, 0, 0 },
1083 { 1168, 2, 78, 2, 1732745, 11, 0, 0 },
1084 { 1303, 2, 78, 2, 1732748, 11, 0, 0 },
1085 { 1433, 2, 72, 2, 1732751, 11, 0, 0 },
1086 { 89, 2, 72, 2, 1732754, 11, 0, 0 },
1087 { 264, 2, 66, 2, 1732757, 11, 0, 0 },
1088 { 435, 2, 66, 2, 1732760, 11, 0, 0 },
1089 { 606, 2, 60, 2, 1732763, 11, 0, 0 },
1090 { 777, 2, 60, 2, 1732766, 11, 0, 0 },
1091 { 917, 2, 54, 2, 1732769, 11, 0, 0 },
1092 { 1052, 2, 54, 2, 1732772, 11, 0, 0 },
1093 { 1187, 2, 48, 2, 1732775, 11, 0, 0 },
1094 { 1322, 2, 48, 2, 1732778, 11, 0, 0 },
1095 { 1452, 2, 42, 2, 1732781, 11, 0, 0 },
1096 { 108, 2, 42, 2, 1732784, 11, 0, 0 },
1097 { 283, 2, 36, 2, 1732787, 11, 0, 0 },
1098 { 454, 2, 36, 2, 1732790, 11, 0, 0 },
1099 { 625, 2, 30, 2, 1732793, 11, 0, 0 },
1100 { 796, 2, 30, 2, 1732796, 11, 0, 0 },
1101 { 936, 2, 24, 2, 1732799, 11, 0, 0 },
1102 { 1071, 2, 24, 2, 1732802, 11, 0, 0 },
1103 { 1206, 2, 18, 2, 1732805, 11, 0, 0 },
1104 { 1341, 2, 18, 2, 1732808, 11, 0, 0 },
1105 { 1471, 2, 12, 2, 1732811, 11, 0, 0 },
1106 { 127, 2, 12, 2, 1732814, 11, 0, 0 },
1107 { 302, 2, 6, 2, 1732817, 11, 0, 0 },
1108 { 473, 2, 6, 2, 1732820, 11, 0, 0 },
1109 { 644, 2, 0, 2, 1732823, 11, 0, 0 },
1110 { 171, 202, 193, 0, 1826842, 0, 0, 0 },
1111 { 346, 202, 187, 0, 1826845, 0, 0, 0 },
1112 { 517, 202, 187, 0, 1826848, 0, 0, 0 },
1113 { 688, 202, 181, 0, 1826851, 0, 0, 0 },
1114 { 834, 202, 181, 0, 1826854, 0, 0, 0 },
1115 { 974, 202, 175, 0, 1826857, 0, 0, 0 },
1116 { 1109, 202, 175, 0, 1826860, 0, 0, 0 },
1117 { 1244, 202, 169, 0, 1826863, 0, 0, 0 },
1118 { 1374, 202, 169, 0, 1826866, 0, 0, 0 },
1119 { 1504, 202, 163, 0, 1826869, 0, 0, 0 },
1120 { 29, 202, 163, 0, 1826872, 0, 0, 0 },
1121 { 204, 202, 157, 0, 1826875, 0, 0, 0 },
1122 { 379, 202, 157, 0, 1826878, 0, 0, 0 },
1123 { 550, 202, 151, 0, 1826881, 0, 0, 0 },
1124 { 721, 202, 151, 0, 1826884, 0, 0, 0 },
1125 { 861, 202, 145, 0, 1826887, 0, 0, 0 },
1126 { 996, 202, 145, 0, 1826890, 0, 0, 0 },
1127 { 1131, 202, 139, 0, 1826893, 0, 0, 0 },
1128 { 1266, 202, 139, 0, 1826896, 0, 0, 0 },
1129 { 1396, 202, 133, 0, 1826899, 0, 0, 0 },
1130 { 52, 202, 133, 0, 1826902, 0, 0, 0 },
1131 { 227, 202, 127, 0, 1826905, 0, 0, 0 },
1132 { 402, 202, 127, 0, 1826908, 0, 0, 0 },
1133 { 573, 202, 121, 0, 1826911, 0, 0, 0 },
1134 { 744, 202, 121, 0, 1826914, 0, 0, 0 },
1135 { 884, 202, 115, 0, 1826917, 0, 0, 0 },
1136 { 1019, 202, 115, 0, 1826920, 0, 0, 0 },
1137 { 1154, 202, 109, 0, 1826923, 0, 0, 0 },
1138 { 1289, 202, 109, 0, 1826926, 0, 0, 0 },
1139 { 1419, 202, 103, 0, 1826929, 0, 0, 0 },
1140 { 75, 202, 103, 0, 1826932, 0, 0, 0 },
1141 { 250, 202, 97, 0, 1826935, 0, 0, 0 },
1142 { 421, 202, 97, 0, 1826938, 0, 0, 0 },
1143 { 592, 202, 91, 0, 1826941, 0, 0, 0 },
1144 { 763, 202, 91, 0, 1826944, 0, 0, 0 },
1145 { 903, 202, 85, 0, 1826947, 0, 0, 0 },
1146 { 1038, 202, 85, 0, 1826950, 0, 0, 0 },
1147 { 1173, 202, 79, 0, 1826953, 0, 0, 0 },
1148 { 1308, 202, 79, 0, 1826956, 0, 0, 0 },
1149 { 1438, 202, 73, 0, 1826959, 0, 0, 0 },
1150 { 94, 202, 73, 0, 1826962, 0, 0, 0 },
1151 { 269, 202, 67, 0, 1826965, 0, 0, 0 },
1152 { 440, 202, 67, 0, 1826968, 0, 0, 0 },
1153 { 611, 202, 61, 0, 1826971, 0, 0, 0 },
1154 { 782, 202, 61, 0, 1826974, 0, 0, 0 },
1155 { 922, 202, 55, 0, 1826977, 0, 0, 0 },
1156 { 1057, 202, 55, 0, 1826980, 0, 0, 0 },
1157 { 1192, 202, 49, 0, 1826983, 0, 0, 0 },
1158 { 1327, 202, 49, 0, 1826986, 0, 0, 0 },
1159 { 1457, 202, 43, 0, 1826989, 0, 0, 0 },
1160 { 113, 202, 43, 0, 1826992, 0, 0, 0 },
1161 { 288, 202, 37, 0, 1826995, 0, 0, 0 },
1162 { 459, 202, 37, 0, 1826998, 0, 0, 0 },
1163 { 630, 202, 31, 0, 1827001, 0, 0, 0 },
1164 { 801, 202, 31, 0, 1827004, 0, 0, 0 },
1165 { 941, 202, 25, 0, 1827007, 0, 0, 0 },
1166 { 1076, 202, 25, 0, 1827010, 0, 0, 0 },
1167 { 1211, 202, 19, 0, 1827013, 0, 0, 0 },
1168 { 1346, 202, 19, 0, 1827016, 0, 0, 0 },
1169 { 1476, 202, 13, 0, 1827019, 0, 0, 0 },
1170 { 132, 202, 13, 0, 1827022, 0, 0, 0 },
1171 { 307, 202, 7, 0, 1827025, 0, 0, 0 },
1172 { 478, 202, 7, 0, 1827028, 0, 0, 0 },
1173 { 649, 202, 1, 0, 1827031, 0, 0, 0 },
1174 { 164, 2, 2, 2, 8410, 12, 0, 0 },
1175 { 339, 2, 2, 2, 8411, 12, 0, 0 },
1176 { 510, 2, 2, 2, 8412, 12, 0, 0 },
1177 { 681, 2, 2, 2, 8413, 12, 0, 0 },
1178 { 827, 2, 2, 2, 8414, 12, 0, 0 },
1179 { 967, 2, 2, 2, 8415, 12, 0, 0 },
1180 { 1102, 2, 2, 2, 8416, 12, 0, 0 },
1181 { 1237, 2, 2, 2, 8417, 12, 0, 0 },
1182 { 1367, 2, 2, 2, 8418, 12, 0, 0 },
1183 { 1497, 2, 2, 2, 8419, 12, 0, 0 },
1184 { 20, 2, 2, 2, 8420, 12, 0, 0 },
1185 { 195, 2, 2, 2, 8421, 12, 0, 0 },
1186 { 370, 2, 2, 2, 8422, 12, 0, 0 },
1187 { 541, 2, 2, 2, 8423, 12, 0, 0 },
1188 { 712, 2, 2, 2, 8424, 12, 0, 0 },
1189 { 852, 2, 2, 2, 8425, 12, 0, 0 },
1190 { 987, 2, 2, 2, 8426, 12, 0, 0 },
1191 { 1122, 2, 2, 2, 8427, 12, 0, 0 },
1192 { 1257, 2, 2, 2, 8428, 12, 0, 0 },
1193 { 1387, 2, 2, 2, 8429, 12, 0, 0 },
1194 { 43, 2, 2, 2, 8430, 12, 0, 0 },
1195 { 218, 2, 2, 2, 8431, 12, 0, 0 },
1196 { 393, 2, 2, 2, 8432, 12, 0, 0 },
1197 { 564, 2, 2, 2, 8433, 12, 0, 0 },
1198 { 735, 2, 2, 2, 8434, 12, 0, 0 },
1199 { 875, 2, 2, 2, 8435, 12, 0, 0 },
1200 { 1010, 2, 2, 2, 8436, 12, 0, 0 },
1201 { 1145, 2, 2, 2, 8437, 12, 0, 0 },
1202 { 1280, 2, 2, 2, 8438, 12, 0, 0 },
1203 { 1410, 2, 2, 2, 8439, 12, 0, 0 },
1204 { 66, 2, 2, 2, 8440, 12, 0, 0 },
1205 { 241, 2, 2, 2, 8441, 12, 0, 0 },
1206 { 412, 2, 2, 2, 8442, 12, 0, 0 },
1207 { 583, 2, 2, 2, 8443, 12, 0, 0 },
1208 { 754, 2, 2, 2, 8444, 12, 0, 0 },
1209 { 894, 2, 2, 2, 8445, 12, 0, 0 },
1210 { 1029, 2, 2, 2, 8446, 12, 0, 0 },
1211 { 1164, 2, 2, 2, 8447, 12, 0, 0 },
1212 { 1299, 2, 2, 2, 8448, 12, 0, 0 },
1213 { 1429, 2, 2, 2, 8449, 12, 0, 0 },
1214 { 85, 2, 2, 2, 8450, 12, 0, 0 },
1215 { 260, 2, 2, 2, 8451, 12, 0, 0 },
1216 { 431, 2, 2, 2, 8452, 12, 0, 0 },
1217 { 602, 2, 2, 2, 8453, 12, 0, 0 },
1218 { 773, 2, 2, 2, 8454, 12, 0, 0 },
1219 { 913, 2, 2, 2, 8455, 12, 0, 0 },
1220 { 1048, 2, 2, 2, 8456, 12, 0, 0 },
1221 { 1183, 2, 2, 2, 8457, 12, 0, 0 },
1222 { 1318, 2, 2, 2, 8458, 12, 0, 0 },
1223 { 1448, 2, 2, 2, 8459, 12, 0, 0 },
1224 { 104, 2, 2, 2, 8460, 12, 0, 0 },
1225 { 279, 2, 2, 2, 8461, 12, 0, 0 },
1226 { 450, 2, 2, 2, 8462, 12, 0, 0 },
1227 { 621, 2, 2, 2, 8463, 12, 0, 0 },
1228 { 792, 2, 2, 2, 8464, 12, 0, 0 },
1229 { 932, 2, 2, 2, 8465, 12, 0, 0 },
1230 { 1067, 2, 2, 2, 8466, 12, 0, 0 },
1231 { 1202, 2, 2, 2, 8467, 12, 0, 0 },
1232 { 1337, 2, 2, 2, 8468, 12, 0, 0 },
1233 { 1467, 2, 2, 2, 8469, 12, 0, 0 },
1234 { 123, 2, 2, 2, 8470, 12, 0, 0 },
1235 { 298, 2, 2, 2, 8471, 12, 0, 0 },
1236 { 469, 2, 2, 2, 8472, 12, 0, 0 },
1237 { 640, 2, 2, 2, 8473, 12, 0, 0 },
1238 { 146, 2, 2, 2, 8474, 12, 1, 0 },
1239 { 321, 2, 2, 2, 8475, 12, 0, 0 },
1240 { 492, 2, 463, 2, 8476, 12, 0, 0 },
1241 { 663, 2, 461, 2, 8477, 12, 0, 0 },
1242 { 815, 2, 461, 2, 8478, 12, 0, 0 },
1243 { 955, 2, 459, 2, 8479, 12, 0, 0 },
1244 { 1090, 2, 459, 2, 8480, 12, 0, 0 },
1245 { 1225, 2, 457, 2, 8481, 12, 0, 0 },
1246 { 1360, 2, 457, 2, 8482, 12, 0, 0 },
1247 { 1490, 2, 455, 2, 8483, 12, 0, 0 },
1248 { 11, 2, 455, 2, 8484, 12, 0, 0 },
1249 { 186, 2, 453, 2, 8485, 12, 0, 0 },
1250 { 361, 2, 453, 2, 8486, 12, 0, 0 },
1251 { 532, 2, 451, 2, 8487, 12, 0, 0 },
1252 { 703, 2, 451, 2, 8488, 12, 0, 0 },
1253 { 843, 2, 449, 2, 8489, 12, 0, 0 },
1254 { 150, 2, 2, 2, 8490, 12, 1, 0 },
1255 { 325, 422, 2, 2, 1732892, 3, 0, 0 },
1256 { 496, 425, 2, 2, 1732894, 3, 0, 0 },
1257 { 667, 428, 2, 2, 1732896, 3, 0, 0 },
1258 { 819, 431, 2, 2, 1732898, 3, 0, 0 },
1259 { 959, 434, 2, 2, 1732900, 3, 0, 0 },
1260 { 1094, 437, 2, 2, 1732902, 3, 0, 0 },
1261 { 1229, 440, 2, 2, 1732904, 3, 0, 0 },
1262};
1263
1264extern const MCPhysReg VERegUnitRoots[][2] = {
1265 { VE::IC },
1266 { VE::PMMR },
1267 { VE::PSW },
1268 { VE::SAR },
1269 { VE::USRCC },
1270 { VE::VIX },
1271 { VE::VL },
1272 { VE::PMC0 },
1273 { VE::PMC1 },
1274 { VE::PMC2 },
1275 { VE::PMC3 },
1276 { VE::PMC4 },
1277 { VE::PMC5 },
1278 { VE::PMC6 },
1279 { VE::PMC7 },
1280 { VE::PMC8 },
1281 { VE::PMC9 },
1282 { VE::PMC10 },
1283 { VE::PMC11 },
1284 { VE::PMC12 },
1285 { VE::PMC13 },
1286 { VE::PMC14 },
1287 { VE::PMCR0 },
1288 { VE::PMCR1 },
1289 { VE::PMCR2 },
1290 { VE::PMCR3 },
1291 { VE::SW0 },
1292 { VE::SW0, VE::SF0 },
1293 { VE::SF0 },
1294 { VE::SW1 },
1295 { VE::SW1, VE::SF1 },
1296 { VE::SF1 },
1297 { VE::SW2 },
1298 { VE::SW2, VE::SF2 },
1299 { VE::SF2 },
1300 { VE::SW3 },
1301 { VE::SW3, VE::SF3 },
1302 { VE::SF3 },
1303 { VE::SW4 },
1304 { VE::SW4, VE::SF4 },
1305 { VE::SF4 },
1306 { VE::SW5 },
1307 { VE::SW5, VE::SF5 },
1308 { VE::SF5 },
1309 { VE::SW6 },
1310 { VE::SW6, VE::SF6 },
1311 { VE::SF6 },
1312 { VE::SW7 },
1313 { VE::SW7, VE::SF7 },
1314 { VE::SF7 },
1315 { VE::SW8 },
1316 { VE::SW8, VE::SF8 },
1317 { VE::SF8 },
1318 { VE::SW9 },
1319 { VE::SW9, VE::SF9 },
1320 { VE::SF9 },
1321 { VE::SW10 },
1322 { VE::SW10, VE::SF10 },
1323 { VE::SF10 },
1324 { VE::SW11 },
1325 { VE::SW11, VE::SF11 },
1326 { VE::SF11 },
1327 { VE::SW12 },
1328 { VE::SW12, VE::SF12 },
1329 { VE::SF12 },
1330 { VE::SW13 },
1331 { VE::SW13, VE::SF13 },
1332 { VE::SF13 },
1333 { VE::SW14 },
1334 { VE::SW14, VE::SF14 },
1335 { VE::SF14 },
1336 { VE::SW15 },
1337 { VE::SW15, VE::SF15 },
1338 { VE::SF15 },
1339 { VE::SW16 },
1340 { VE::SW16, VE::SF16 },
1341 { VE::SF16 },
1342 { VE::SW17 },
1343 { VE::SW17, VE::SF17 },
1344 { VE::SF17 },
1345 { VE::SW18 },
1346 { VE::SW18, VE::SF18 },
1347 { VE::SF18 },
1348 { VE::SW19 },
1349 { VE::SW19, VE::SF19 },
1350 { VE::SF19 },
1351 { VE::SW20 },
1352 { VE::SW20, VE::SF20 },
1353 { VE::SF20 },
1354 { VE::SW21 },
1355 { VE::SW21, VE::SF21 },
1356 { VE::SF21 },
1357 { VE::SW22 },
1358 { VE::SW22, VE::SF22 },
1359 { VE::SF22 },
1360 { VE::SW23 },
1361 { VE::SW23, VE::SF23 },
1362 { VE::SF23 },
1363 { VE::SW24 },
1364 { VE::SW24, VE::SF24 },
1365 { VE::SF24 },
1366 { VE::SW25 },
1367 { VE::SW25, VE::SF25 },
1368 { VE::SF25 },
1369 { VE::SW26 },
1370 { VE::SW26, VE::SF26 },
1371 { VE::SF26 },
1372 { VE::SW27 },
1373 { VE::SW27, VE::SF27 },
1374 { VE::SF27 },
1375 { VE::SW28 },
1376 { VE::SW28, VE::SF28 },
1377 { VE::SF28 },
1378 { VE::SW29 },
1379 { VE::SW29, VE::SF29 },
1380 { VE::SF29 },
1381 { VE::SW30 },
1382 { VE::SW30, VE::SF30 },
1383 { VE::SF30 },
1384 { VE::SW31 },
1385 { VE::SW31, VE::SF31 },
1386 { VE::SF31 },
1387 { VE::SW32 },
1388 { VE::SW32, VE::SF32 },
1389 { VE::SF32 },
1390 { VE::SW33 },
1391 { VE::SW33, VE::SF33 },
1392 { VE::SF33 },
1393 { VE::SW34 },
1394 { VE::SW34, VE::SF34 },
1395 { VE::SF34 },
1396 { VE::SW35 },
1397 { VE::SW35, VE::SF35 },
1398 { VE::SF35 },
1399 { VE::SW36 },
1400 { VE::SW36, VE::SF36 },
1401 { VE::SF36 },
1402 { VE::SW37 },
1403 { VE::SW37, VE::SF37 },
1404 { VE::SF37 },
1405 { VE::SW38 },
1406 { VE::SW38, VE::SF38 },
1407 { VE::SF38 },
1408 { VE::SW39 },
1409 { VE::SW39, VE::SF39 },
1410 { VE::SF39 },
1411 { VE::SW40 },
1412 { VE::SW40, VE::SF40 },
1413 { VE::SF40 },
1414 { VE::SW41 },
1415 { VE::SW41, VE::SF41 },
1416 { VE::SF41 },
1417 { VE::SW42 },
1418 { VE::SW42, VE::SF42 },
1419 { VE::SF42 },
1420 { VE::SW43 },
1421 { VE::SW43, VE::SF43 },
1422 { VE::SF43 },
1423 { VE::SW44 },
1424 { VE::SW44, VE::SF44 },
1425 { VE::SF44 },
1426 { VE::SW45 },
1427 { VE::SW45, VE::SF45 },
1428 { VE::SF45 },
1429 { VE::SW46 },
1430 { VE::SW46, VE::SF46 },
1431 { VE::SF46 },
1432 { VE::SW47 },
1433 { VE::SW47, VE::SF47 },
1434 { VE::SF47 },
1435 { VE::SW48 },
1436 { VE::SW48, VE::SF48 },
1437 { VE::SF48 },
1438 { VE::SW49 },
1439 { VE::SW49, VE::SF49 },
1440 { VE::SF49 },
1441 { VE::SW50 },
1442 { VE::SW50, VE::SF50 },
1443 { VE::SF50 },
1444 { VE::SW51 },
1445 { VE::SW51, VE::SF51 },
1446 { VE::SF51 },
1447 { VE::SW52 },
1448 { VE::SW52, VE::SF52 },
1449 { VE::SF52 },
1450 { VE::SW53 },
1451 { VE::SW53, VE::SF53 },
1452 { VE::SF53 },
1453 { VE::SW54 },
1454 { VE::SW54, VE::SF54 },
1455 { VE::SF54 },
1456 { VE::SW55 },
1457 { VE::SW55, VE::SF55 },
1458 { VE::SF55 },
1459 { VE::SW56 },
1460 { VE::SW56, VE::SF56 },
1461 { VE::SF56 },
1462 { VE::SW57 },
1463 { VE::SW57, VE::SF57 },
1464 { VE::SF57 },
1465 { VE::SW58 },
1466 { VE::SW58, VE::SF58 },
1467 { VE::SF58 },
1468 { VE::SW59 },
1469 { VE::SW59, VE::SF59 },
1470 { VE::SF59 },
1471 { VE::SW60 },
1472 { VE::SW60, VE::SF60 },
1473 { VE::SF60 },
1474 { VE::SW61 },
1475 { VE::SW61, VE::SF61 },
1476 { VE::SF61 },
1477 { VE::SW62 },
1478 { VE::SW62, VE::SF62 },
1479 { VE::SF62 },
1480 { VE::SW63 },
1481 { VE::SW63, VE::SF63 },
1482 { VE::SF63 },
1483 { VE::V0 },
1484 { VE::V1 },
1485 { VE::V2 },
1486 { VE::V3 },
1487 { VE::V4 },
1488 { VE::V5 },
1489 { VE::V6 },
1490 { VE::V7 },
1491 { VE::V8 },
1492 { VE::V9 },
1493 { VE::V10 },
1494 { VE::V11 },
1495 { VE::V12 },
1496 { VE::V13 },
1497 { VE::V14 },
1498 { VE::V15 },
1499 { VE::V16 },
1500 { VE::V17 },
1501 { VE::V18 },
1502 { VE::V19 },
1503 { VE::V20 },
1504 { VE::V21 },
1505 { VE::V22 },
1506 { VE::V23 },
1507 { VE::V24 },
1508 { VE::V25 },
1509 { VE::V26 },
1510 { VE::V27 },
1511 { VE::V28 },
1512 { VE::V29 },
1513 { VE::V30 },
1514 { VE::V31 },
1515 { VE::V32 },
1516 { VE::V33 },
1517 { VE::V34 },
1518 { VE::V35 },
1519 { VE::V36 },
1520 { VE::V37 },
1521 { VE::V38 },
1522 { VE::V39 },
1523 { VE::V40 },
1524 { VE::V41 },
1525 { VE::V42 },
1526 { VE::V43 },
1527 { VE::V44 },
1528 { VE::V45 },
1529 { VE::V46 },
1530 { VE::V47 },
1531 { VE::V48 },
1532 { VE::V49 },
1533 { VE::V50 },
1534 { VE::V51 },
1535 { VE::V52 },
1536 { VE::V53 },
1537 { VE::V54 },
1538 { VE::V55 },
1539 { VE::V56 },
1540 { VE::V57 },
1541 { VE::V58 },
1542 { VE::V59 },
1543 { VE::V60 },
1544 { VE::V61 },
1545 { VE::V62 },
1546 { VE::V63 },
1547 { VE::VM0 },
1548 { VE::VM1 },
1549 { VE::VM2 },
1550 { VE::VM3 },
1551 { VE::VM4 },
1552 { VE::VM5 },
1553 { VE::VM6 },
1554 { VE::VM7 },
1555 { VE::VM8 },
1556 { VE::VM9 },
1557 { VE::VM10 },
1558 { VE::VM11 },
1559 { VE::VM12 },
1560 { VE::VM13 },
1561 { VE::VM14 },
1562 { VE::VM15 },
1563 { VE::VMP0 },
1564};
1565
1566namespace { // Register classes...
1567 // F32 Register Class...
1568 const MCPhysReg F32[] = {
1569 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6, VE::SF7, VE::SF34, VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41, VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48, VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55, VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62, VE::SF63, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13, VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20, VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27, VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33,
1570 };
1571
1572 // F32 Bit set.
1573 const uint8_t F32Bits[] = {
1574 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07,
1575 };
1576
1577 // I32 Register Class...
1578 const MCPhysReg I32[] = {
1579 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6, VE::SW7, VE::SW34, VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41, VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48, VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55, VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62, VE::SW63, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13, VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20, VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27, VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33,
1580 };
1581
1582 // I32 Bit set.
1583 const uint8_t I32Bits[] = {
1584 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07,
1585 };
1586
1587 // VLS Register Class...
1588 const MCPhysReg VLS[] = {
1589 VE::VL,
1590 };
1591
1592 // VLS Bit set.
1593 const uint8_t VLSBits[] = {
1594 0x80,
1595 };
1596
1597 // I64 Register Class...
1598 const MCPhysReg I64[] = {
1599 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7, VE::SX34, VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62, VE::SX63, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33,
1600 };
1601
1602 // I64 Bit set.
1603 const uint8_t I64Bits[] = {
1604 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07,
1605 };
1606
1607 // MISC Register Class...
1608 const MCPhysReg MISC[] = {
1609 VE::USRCC, VE::PSW, VE::SAR, VE::PMMR, VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3, VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3, VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7, VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11, VE::PMC12, VE::PMC13, VE::PMC14,
1610 };
1611
1612 // MISC Bit set.
1613 const uint8_t MISCBits[] = {
1614 0x3c, 0xff, 0xff, 0x07,
1615 };
1616
1617 // F128 Register Class...
1618 const MCPhysReg F128[] = {
1619 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23, VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31, VE::Q4, VE::Q5, VE::Q6, VE::Q7, VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15, VE::Q16,
1620 };
1621
1622 // F128 Bit set.
1623 const uint8_t F128Bits[] = {
1624 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1625 };
1626
1627 // VM Register Class...
1628 const MCPhysReg VM[] = {
1629 VE::VM0, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, VE::VM12, VE::VM13, VE::VM14, VE::VM15,
1630 };
1631
1632 // VM Bit set.
1633 const uint8_t VMBits[] = {
1634 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1635 };
1636
1637 // VM512 Register Class...
1638 const MCPhysReg VM512[] = {
1639 VE::VMP0, VE::VMP1, VE::VMP2, VE::VMP3, VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7,
1640 };
1641
1642 // VM512 Bit set.
1643 const uint8_t VM512Bits[] = {
1644 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
1645 };
1646
1647 // VM512_with_sub_vm_even Register Class...
1648 const MCPhysReg VM512_with_sub_vm_even[] = {
1649 VE::VMP1, VE::VMP2, VE::VMP3, VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7,
1650 };
1651
1652 // VM512_with_sub_vm_even Bit set.
1653 const uint8_t VM512_with_sub_vm_evenBits[] = {
1654 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
1655 };
1656
1657 // V64 Register Class...
1658 const MCPhysReg V64[] = {
1659 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63, VE::VIX,
1660 };
1661
1662 // V64 Bit set.
1663 const uint8_t V64Bits[] = {
1664 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07,
1665 };
1666
1667} // end anonymous namespace
1668
1669
1670#ifdef __GNUC__
1671#pragma GCC diagnostic push
1672#pragma GCC diagnostic ignored "-Woverlength-strings"
1673#endif
1674extern const char VERegClassStrings[] = {
1675 /* 0 */ "VM512\000"
1676 /* 6 */ "F32\000"
1677 /* 10 */ "I32\000"
1678 /* 14 */ "I64\000"
1679 /* 18 */ "V64\000"
1680 /* 22 */ "F128\000"
1681 /* 27 */ "MISC\000"
1682 /* 32 */ "VM\000"
1683 /* 35 */ "VLS\000"
1684 /* 39 */ "VM512_with_sub_vm_even\000"
1685};
1686#ifdef __GNUC__
1687#pragma GCC diagnostic pop
1688#endif
1689
1690extern const MCRegisterClass VEMCRegisterClasses[] = {
1691 { F32, F32Bits, 6, 64, sizeof(F32Bits), VE::F32RegClassID, 32, 1, true, false },
1692 { I32, I32Bits, 10, 64, sizeof(I32Bits), VE::I32RegClassID, 32, 1, true, false },
1693 { VLS, VLSBits, 35, 1, sizeof(VLSBits), VE::VLSRegClassID, 32, 1, true, false },
1694 { I64, I64Bits, 14, 64, sizeof(I64Bits), VE::I64RegClassID, 64, 1, true, false },
1695 { MISC, MISCBits, 27, 23, sizeof(MISCBits), VE::MISCRegClassID, 64, 1, true, false },
1696 { F128, F128Bits, 22, 32, sizeof(F128Bits), VE::F128RegClassID, 128, 1, true, false },
1697 { VM, VMBits, 32, 16, sizeof(VMBits), VE::VMRegClassID, 256, 1, true, false },
1698 { VM512, VM512Bits, 0, 8, sizeof(VM512Bits), VE::VM512RegClassID, 512, 1, true, false },
1699 { VM512_with_sub_vm_even, VM512_with_sub_vm_evenBits, 39, 7, sizeof(VM512_with_sub_vm_evenBits), VE::VM512_with_sub_vm_evenRegClassID, 512, 1, true, false },
1700 { V64, V64Bits, 18, 65, sizeof(V64Bits), VE::V64RegClassID, 16384, 1, true, false },
1701};
1702
1703// VE Dwarf<->LLVM register mappings.
1704extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0Dwarf2L[] = {
1705 { 0U, VE::SX0 },
1706 { 1U, VE::SX1 },
1707 { 2U, VE::SX2 },
1708 { 3U, VE::SX3 },
1709 { 4U, VE::SX4 },
1710 { 5U, VE::SX5 },
1711 { 6U, VE::SX6 },
1712 { 7U, VE::SX7 },
1713 { 8U, VE::SX8 },
1714 { 9U, VE::SX9 },
1715 { 10U, VE::SX10 },
1716 { 11U, VE::SX11 },
1717 { 12U, VE::SX12 },
1718 { 13U, VE::SX13 },
1719 { 14U, VE::SX14 },
1720 { 15U, VE::SX15 },
1721 { 16U, VE::SX16 },
1722 { 17U, VE::SX17 },
1723 { 18U, VE::SX18 },
1724 { 19U, VE::SX19 },
1725 { 20U, VE::SX20 },
1726 { 21U, VE::SX21 },
1727 { 22U, VE::SX22 },
1728 { 23U, VE::SX23 },
1729 { 24U, VE::SX24 },
1730 { 25U, VE::SX25 },
1731 { 26U, VE::SX26 },
1732 { 27U, VE::SX27 },
1733 { 28U, VE::SX28 },
1734 { 29U, VE::SX29 },
1735 { 30U, VE::SX30 },
1736 { 31U, VE::SX31 },
1737 { 32U, VE::SX32 },
1738 { 33U, VE::SX33 },
1739 { 34U, VE::SX34 },
1740 { 35U, VE::SX35 },
1741 { 36U, VE::SX36 },
1742 { 37U, VE::SX37 },
1743 { 38U, VE::SX38 },
1744 { 39U, VE::SX39 },
1745 { 40U, VE::SX40 },
1746 { 41U, VE::SX41 },
1747 { 42U, VE::SX42 },
1748 { 43U, VE::SX43 },
1749 { 44U, VE::SX44 },
1750 { 45U, VE::SX45 },
1751 { 46U, VE::SX46 },
1752 { 47U, VE::SX47 },
1753 { 48U, VE::SX48 },
1754 { 49U, VE::SX49 },
1755 { 50U, VE::SX50 },
1756 { 51U, VE::SX51 },
1757 { 52U, VE::SX52 },
1758 { 53U, VE::SX53 },
1759 { 54U, VE::SX54 },
1760 { 55U, VE::SX55 },
1761 { 56U, VE::SX56 },
1762 { 57U, VE::SX57 },
1763 { 58U, VE::SX58 },
1764 { 59U, VE::SX59 },
1765 { 60U, VE::SX60 },
1766 { 61U, VE::SX61 },
1767 { 62U, VE::SX62 },
1768 { 63U, VE::SX63 },
1769 { 64U, VE::V0 },
1770 { 65U, VE::V1 },
1771 { 66U, VE::V2 },
1772 { 67U, VE::V3 },
1773 { 68U, VE::V4 },
1774 { 69U, VE::V5 },
1775 { 70U, VE::V6 },
1776 { 71U, VE::V7 },
1777 { 72U, VE::V8 },
1778 { 73U, VE::V9 },
1779 { 74U, VE::V10 },
1780 { 75U, VE::V11 },
1781 { 76U, VE::V12 },
1782 { 77U, VE::V13 },
1783 { 78U, VE::V14 },
1784 { 79U, VE::V15 },
1785 { 80U, VE::V16 },
1786 { 81U, VE::V17 },
1787 { 82U, VE::V18 },
1788 { 83U, VE::V19 },
1789 { 84U, VE::V20 },
1790 { 85U, VE::V21 },
1791 { 86U, VE::V22 },
1792 { 87U, VE::V23 },
1793 { 88U, VE::V24 },
1794 { 89U, VE::V25 },
1795 { 90U, VE::V26 },
1796 { 91U, VE::V27 },
1797 { 92U, VE::V28 },
1798 { 93U, VE::V29 },
1799 { 94U, VE::V30 },
1800 { 95U, VE::V31 },
1801 { 96U, VE::V32 },
1802 { 97U, VE::V33 },
1803 { 98U, VE::V34 },
1804 { 99U, VE::V35 },
1805 { 100U, VE::V36 },
1806 { 101U, VE::V37 },
1807 { 102U, VE::V38 },
1808 { 103U, VE::V39 },
1809 { 104U, VE::V40 },
1810 { 105U, VE::V41 },
1811 { 106U, VE::V42 },
1812 { 107U, VE::V43 },
1813 { 108U, VE::V44 },
1814 { 109U, VE::V45 },
1815 { 110U, VE::V46 },
1816 { 111U, VE::V47 },
1817 { 112U, VE::V48 },
1818 { 113U, VE::V49 },
1819 { 114U, VE::V50 },
1820 { 115U, VE::V51 },
1821 { 116U, VE::V52 },
1822 { 117U, VE::V53 },
1823 { 118U, VE::V54 },
1824 { 119U, VE::V55 },
1825 { 120U, VE::V56 },
1826 { 121U, VE::V57 },
1827 { 122U, VE::V58 },
1828 { 123U, VE::V59 },
1829 { 124U, VE::V60 },
1830 { 125U, VE::V61 },
1831 { 126U, VE::V62 },
1832 { 127U, VE::V63 },
1833 { 128U, VE::VM0 },
1834 { 129U, VE::VM1 },
1835 { 130U, VE::VM2 },
1836 { 131U, VE::VM3 },
1837 { 132U, VE::VM4 },
1838 { 133U, VE::VM5 },
1839 { 134U, VE::VM6 },
1840 { 135U, VE::VM7 },
1841 { 136U, VE::VM8 },
1842 { 137U, VE::VM9 },
1843 { 138U, VE::VM10 },
1844 { 139U, VE::VM11 },
1845 { 140U, VE::VM12 },
1846 { 141U, VE::VM13 },
1847 { 142U, VE::VM14 },
1848 { 143U, VE::VM15 },
1849};
1850extern const unsigned VEDwarfFlavour0Dwarf2LSize = std::size(VEDwarfFlavour0Dwarf2L);
1851
1852extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0Dwarf2L[] = {
1853 { 0U, VE::SX0 },
1854 { 1U, VE::SX1 },
1855 { 2U, VE::SX2 },
1856 { 3U, VE::SX3 },
1857 { 4U, VE::SX4 },
1858 { 5U, VE::SX5 },
1859 { 6U, VE::SX6 },
1860 { 7U, VE::SX7 },
1861 { 8U, VE::SX8 },
1862 { 9U, VE::SX9 },
1863 { 10U, VE::SX10 },
1864 { 11U, VE::SX11 },
1865 { 12U, VE::SX12 },
1866 { 13U, VE::SX13 },
1867 { 14U, VE::SX14 },
1868 { 15U, VE::SX15 },
1869 { 16U, VE::SX16 },
1870 { 17U, VE::SX17 },
1871 { 18U, VE::SX18 },
1872 { 19U, VE::SX19 },
1873 { 20U, VE::SX20 },
1874 { 21U, VE::SX21 },
1875 { 22U, VE::SX22 },
1876 { 23U, VE::SX23 },
1877 { 24U, VE::SX24 },
1878 { 25U, VE::SX25 },
1879 { 26U, VE::SX26 },
1880 { 27U, VE::SX27 },
1881 { 28U, VE::SX28 },
1882 { 29U, VE::SX29 },
1883 { 30U, VE::SX30 },
1884 { 31U, VE::SX31 },
1885 { 32U, VE::SX32 },
1886 { 33U, VE::SX33 },
1887 { 34U, VE::SX34 },
1888 { 35U, VE::SX35 },
1889 { 36U, VE::SX36 },
1890 { 37U, VE::SX37 },
1891 { 38U, VE::SX38 },
1892 { 39U, VE::SX39 },
1893 { 40U, VE::SX40 },
1894 { 41U, VE::SX41 },
1895 { 42U, VE::SX42 },
1896 { 43U, VE::SX43 },
1897 { 44U, VE::SX44 },
1898 { 45U, VE::SX45 },
1899 { 46U, VE::SX46 },
1900 { 47U, VE::SX47 },
1901 { 48U, VE::SX48 },
1902 { 49U, VE::SX49 },
1903 { 50U, VE::SX50 },
1904 { 51U, VE::SX51 },
1905 { 52U, VE::SX52 },
1906 { 53U, VE::SX53 },
1907 { 54U, VE::SX54 },
1908 { 55U, VE::SX55 },
1909 { 56U, VE::SX56 },
1910 { 57U, VE::SX57 },
1911 { 58U, VE::SX58 },
1912 { 59U, VE::SX59 },
1913 { 60U, VE::SX60 },
1914 { 61U, VE::SX61 },
1915 { 62U, VE::SX62 },
1916 { 63U, VE::SX63 },
1917 { 64U, VE::V0 },
1918 { 65U, VE::V1 },
1919 { 66U, VE::V2 },
1920 { 67U, VE::V3 },
1921 { 68U, VE::V4 },
1922 { 69U, VE::V5 },
1923 { 70U, VE::V6 },
1924 { 71U, VE::V7 },
1925 { 72U, VE::V8 },
1926 { 73U, VE::V9 },
1927 { 74U, VE::V10 },
1928 { 75U, VE::V11 },
1929 { 76U, VE::V12 },
1930 { 77U, VE::V13 },
1931 { 78U, VE::V14 },
1932 { 79U, VE::V15 },
1933 { 80U, VE::V16 },
1934 { 81U, VE::V17 },
1935 { 82U, VE::V18 },
1936 { 83U, VE::V19 },
1937 { 84U, VE::V20 },
1938 { 85U, VE::V21 },
1939 { 86U, VE::V22 },
1940 { 87U, VE::V23 },
1941 { 88U, VE::V24 },
1942 { 89U, VE::V25 },
1943 { 90U, VE::V26 },
1944 { 91U, VE::V27 },
1945 { 92U, VE::V28 },
1946 { 93U, VE::V29 },
1947 { 94U, VE::V30 },
1948 { 95U, VE::V31 },
1949 { 96U, VE::V32 },
1950 { 97U, VE::V33 },
1951 { 98U, VE::V34 },
1952 { 99U, VE::V35 },
1953 { 100U, VE::V36 },
1954 { 101U, VE::V37 },
1955 { 102U, VE::V38 },
1956 { 103U, VE::V39 },
1957 { 104U, VE::V40 },
1958 { 105U, VE::V41 },
1959 { 106U, VE::V42 },
1960 { 107U, VE::V43 },
1961 { 108U, VE::V44 },
1962 { 109U, VE::V45 },
1963 { 110U, VE::V46 },
1964 { 111U, VE::V47 },
1965 { 112U, VE::V48 },
1966 { 113U, VE::V49 },
1967 { 114U, VE::V50 },
1968 { 115U, VE::V51 },
1969 { 116U, VE::V52 },
1970 { 117U, VE::V53 },
1971 { 118U, VE::V54 },
1972 { 119U, VE::V55 },
1973 { 120U, VE::V56 },
1974 { 121U, VE::V57 },
1975 { 122U, VE::V58 },
1976 { 123U, VE::V59 },
1977 { 124U, VE::V60 },
1978 { 125U, VE::V61 },
1979 { 126U, VE::V62 },
1980 { 127U, VE::V63 },
1981 { 128U, VE::VM0 },
1982 { 129U, VE::VM1 },
1983 { 130U, VE::VM2 },
1984 { 131U, VE::VM3 },
1985 { 132U, VE::VM4 },
1986 { 133U, VE::VM5 },
1987 { 134U, VE::VM6 },
1988 { 135U, VE::VM7 },
1989 { 136U, VE::VM8 },
1990 { 137U, VE::VM9 },
1991 { 138U, VE::VM10 },
1992 { 139U, VE::VM11 },
1993 { 140U, VE::VM12 },
1994 { 141U, VE::VM13 },
1995 { 142U, VE::VM14 },
1996 { 143U, VE::VM15 },
1997};
1998extern const unsigned VEEHFlavour0Dwarf2LSize = std::size(VEEHFlavour0Dwarf2L);
1999
2000extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0L2Dwarf[] = {
2001 { VE::SF0, 0U },
2002 { VE::SF1, 1U },
2003 { VE::SF2, 2U },
2004 { VE::SF3, 3U },
2005 { VE::SF4, 4U },
2006 { VE::SF5, 5U },
2007 { VE::SF6, 6U },
2008 { VE::SF7, 7U },
2009 { VE::SF8, 8U },
2010 { VE::SF9, 9U },
2011 { VE::SF10, 10U },
2012 { VE::SF11, 11U },
2013 { VE::SF12, 12U },
2014 { VE::SF13, 13U },
2015 { VE::SF14, 14U },
2016 { VE::SF15, 15U },
2017 { VE::SF16, 16U },
2018 { VE::SF17, 17U },
2019 { VE::SF18, 18U },
2020 { VE::SF19, 19U },
2021 { VE::SF20, 20U },
2022 { VE::SF21, 21U },
2023 { VE::SF22, 22U },
2024 { VE::SF23, 23U },
2025 { VE::SF24, 24U },
2026 { VE::SF25, 25U },
2027 { VE::SF26, 26U },
2028 { VE::SF27, 27U },
2029 { VE::SF28, 28U },
2030 { VE::SF29, 29U },
2031 { VE::SF30, 30U },
2032 { VE::SF31, 31U },
2033 { VE::SF32, 32U },
2034 { VE::SF33, 33U },
2035 { VE::SF34, 34U },
2036 { VE::SF35, 35U },
2037 { VE::SF36, 36U },
2038 { VE::SF37, 37U },
2039 { VE::SF38, 38U },
2040 { VE::SF39, 39U },
2041 { VE::SF40, 40U },
2042 { VE::SF41, 41U },
2043 { VE::SF42, 42U },
2044 { VE::SF43, 43U },
2045 { VE::SF44, 44U },
2046 { VE::SF45, 45U },
2047 { VE::SF46, 46U },
2048 { VE::SF47, 47U },
2049 { VE::SF48, 48U },
2050 { VE::SF49, 49U },
2051 { VE::SF50, 50U },
2052 { VE::SF51, 51U },
2053 { VE::SF52, 52U },
2054 { VE::SF53, 53U },
2055 { VE::SF54, 54U },
2056 { VE::SF55, 55U },
2057 { VE::SF56, 56U },
2058 { VE::SF57, 57U },
2059 { VE::SF58, 58U },
2060 { VE::SF59, 59U },
2061 { VE::SF60, 60U },
2062 { VE::SF61, 61U },
2063 { VE::SF62, 62U },
2064 { VE::SF63, 63U },
2065 { VE::SW0, 0U },
2066 { VE::SW1, 1U },
2067 { VE::SW2, 2U },
2068 { VE::SW3, 3U },
2069 { VE::SW4, 4U },
2070 { VE::SW5, 5U },
2071 { VE::SW6, 6U },
2072 { VE::SW7, 7U },
2073 { VE::SW8, 8U },
2074 { VE::SW9, 9U },
2075 { VE::SW10, 10U },
2076 { VE::SW11, 11U },
2077 { VE::SW12, 12U },
2078 { VE::SW13, 13U },
2079 { VE::SW14, 14U },
2080 { VE::SW15, 15U },
2081 { VE::SW16, 16U },
2082 { VE::SW17, 17U },
2083 { VE::SW18, 18U },
2084 { VE::SW19, 19U },
2085 { VE::SW20, 20U },
2086 { VE::SW21, 21U },
2087 { VE::SW22, 22U },
2088 { VE::SW23, 23U },
2089 { VE::SW24, 24U },
2090 { VE::SW25, 25U },
2091 { VE::SW26, 26U },
2092 { VE::SW27, 27U },
2093 { VE::SW28, 28U },
2094 { VE::SW29, 29U },
2095 { VE::SW30, 30U },
2096 { VE::SW31, 31U },
2097 { VE::SW32, 32U },
2098 { VE::SW33, 33U },
2099 { VE::SW34, 34U },
2100 { VE::SW35, 35U },
2101 { VE::SW36, 36U },
2102 { VE::SW37, 37U },
2103 { VE::SW38, 38U },
2104 { VE::SW39, 39U },
2105 { VE::SW40, 40U },
2106 { VE::SW41, 41U },
2107 { VE::SW42, 42U },
2108 { VE::SW43, 43U },
2109 { VE::SW44, 44U },
2110 { VE::SW45, 45U },
2111 { VE::SW46, 46U },
2112 { VE::SW47, 47U },
2113 { VE::SW48, 48U },
2114 { VE::SW49, 49U },
2115 { VE::SW50, 50U },
2116 { VE::SW51, 51U },
2117 { VE::SW52, 52U },
2118 { VE::SW53, 53U },
2119 { VE::SW54, 54U },
2120 { VE::SW55, 55U },
2121 { VE::SW56, 56U },
2122 { VE::SW57, 57U },
2123 { VE::SW58, 58U },
2124 { VE::SW59, 59U },
2125 { VE::SW60, 60U },
2126 { VE::SW61, 61U },
2127 { VE::SW62, 62U },
2128 { VE::SW63, 63U },
2129 { VE::SX0, 0U },
2130 { VE::SX1, 1U },
2131 { VE::SX2, 2U },
2132 { VE::SX3, 3U },
2133 { VE::SX4, 4U },
2134 { VE::SX5, 5U },
2135 { VE::SX6, 6U },
2136 { VE::SX7, 7U },
2137 { VE::SX8, 8U },
2138 { VE::SX9, 9U },
2139 { VE::SX10, 10U },
2140 { VE::SX11, 11U },
2141 { VE::SX12, 12U },
2142 { VE::SX13, 13U },
2143 { VE::SX14, 14U },
2144 { VE::SX15, 15U },
2145 { VE::SX16, 16U },
2146 { VE::SX17, 17U },
2147 { VE::SX18, 18U },
2148 { VE::SX19, 19U },
2149 { VE::SX20, 20U },
2150 { VE::SX21, 21U },
2151 { VE::SX22, 22U },
2152 { VE::SX23, 23U },
2153 { VE::SX24, 24U },
2154 { VE::SX25, 25U },
2155 { VE::SX26, 26U },
2156 { VE::SX27, 27U },
2157 { VE::SX28, 28U },
2158 { VE::SX29, 29U },
2159 { VE::SX30, 30U },
2160 { VE::SX31, 31U },
2161 { VE::SX32, 32U },
2162 { VE::SX33, 33U },
2163 { VE::SX34, 34U },
2164 { VE::SX35, 35U },
2165 { VE::SX36, 36U },
2166 { VE::SX37, 37U },
2167 { VE::SX38, 38U },
2168 { VE::SX39, 39U },
2169 { VE::SX40, 40U },
2170 { VE::SX41, 41U },
2171 { VE::SX42, 42U },
2172 { VE::SX43, 43U },
2173 { VE::SX44, 44U },
2174 { VE::SX45, 45U },
2175 { VE::SX46, 46U },
2176 { VE::SX47, 47U },
2177 { VE::SX48, 48U },
2178 { VE::SX49, 49U },
2179 { VE::SX50, 50U },
2180 { VE::SX51, 51U },
2181 { VE::SX52, 52U },
2182 { VE::SX53, 53U },
2183 { VE::SX54, 54U },
2184 { VE::SX55, 55U },
2185 { VE::SX56, 56U },
2186 { VE::SX57, 57U },
2187 { VE::SX58, 58U },
2188 { VE::SX59, 59U },
2189 { VE::SX60, 60U },
2190 { VE::SX61, 61U },
2191 { VE::SX62, 62U },
2192 { VE::SX63, 63U },
2193 { VE::V0, 64U },
2194 { VE::V1, 65U },
2195 { VE::V2, 66U },
2196 { VE::V3, 67U },
2197 { VE::V4, 68U },
2198 { VE::V5, 69U },
2199 { VE::V6, 70U },
2200 { VE::V7, 71U },
2201 { VE::V8, 72U },
2202 { VE::V9, 73U },
2203 { VE::V10, 74U },
2204 { VE::V11, 75U },
2205 { VE::V12, 76U },
2206 { VE::V13, 77U },
2207 { VE::V14, 78U },
2208 { VE::V15, 79U },
2209 { VE::V16, 80U },
2210 { VE::V17, 81U },
2211 { VE::V18, 82U },
2212 { VE::V19, 83U },
2213 { VE::V20, 84U },
2214 { VE::V21, 85U },
2215 { VE::V22, 86U },
2216 { VE::V23, 87U },
2217 { VE::V24, 88U },
2218 { VE::V25, 89U },
2219 { VE::V26, 90U },
2220 { VE::V27, 91U },
2221 { VE::V28, 92U },
2222 { VE::V29, 93U },
2223 { VE::V30, 94U },
2224 { VE::V31, 95U },
2225 { VE::V32, 96U },
2226 { VE::V33, 97U },
2227 { VE::V34, 98U },
2228 { VE::V35, 99U },
2229 { VE::V36, 100U },
2230 { VE::V37, 101U },
2231 { VE::V38, 102U },
2232 { VE::V39, 103U },
2233 { VE::V40, 104U },
2234 { VE::V41, 105U },
2235 { VE::V42, 106U },
2236 { VE::V43, 107U },
2237 { VE::V44, 108U },
2238 { VE::V45, 109U },
2239 { VE::V46, 110U },
2240 { VE::V47, 111U },
2241 { VE::V48, 112U },
2242 { VE::V49, 113U },
2243 { VE::V50, 114U },
2244 { VE::V51, 115U },
2245 { VE::V52, 116U },
2246 { VE::V53, 117U },
2247 { VE::V54, 118U },
2248 { VE::V55, 119U },
2249 { VE::V56, 120U },
2250 { VE::V57, 121U },
2251 { VE::V58, 122U },
2252 { VE::V59, 123U },
2253 { VE::V60, 124U },
2254 { VE::V61, 125U },
2255 { VE::V62, 126U },
2256 { VE::V63, 127U },
2257 { VE::VM0, 128U },
2258 { VE::VM1, 129U },
2259 { VE::VM2, 130U },
2260 { VE::VM3, 131U },
2261 { VE::VM4, 132U },
2262 { VE::VM5, 133U },
2263 { VE::VM6, 134U },
2264 { VE::VM7, 135U },
2265 { VE::VM8, 136U },
2266 { VE::VM9, 137U },
2267 { VE::VM10, 138U },
2268 { VE::VM11, 139U },
2269 { VE::VM12, 140U },
2270 { VE::VM13, 141U },
2271 { VE::VM14, 142U },
2272 { VE::VM15, 143U },
2273};
2274extern const unsigned VEDwarfFlavour0L2DwarfSize = std::size(VEDwarfFlavour0L2Dwarf);
2275
2276extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0L2Dwarf[] = {
2277 { VE::SF0, 0U },
2278 { VE::SF1, 1U },
2279 { VE::SF2, 2U },
2280 { VE::SF3, 3U },
2281 { VE::SF4, 4U },
2282 { VE::SF5, 5U },
2283 { VE::SF6, 6U },
2284 { VE::SF7, 7U },
2285 { VE::SF8, 8U },
2286 { VE::SF9, 9U },
2287 { VE::SF10, 10U },
2288 { VE::SF11, 11U },
2289 { VE::SF12, 12U },
2290 { VE::SF13, 13U },
2291 { VE::SF14, 14U },
2292 { VE::SF15, 15U },
2293 { VE::SF16, 16U },
2294 { VE::SF17, 17U },
2295 { VE::SF18, 18U },
2296 { VE::SF19, 19U },
2297 { VE::SF20, 20U },
2298 { VE::SF21, 21U },
2299 { VE::SF22, 22U },
2300 { VE::SF23, 23U },
2301 { VE::SF24, 24U },
2302 { VE::SF25, 25U },
2303 { VE::SF26, 26U },
2304 { VE::SF27, 27U },
2305 { VE::SF28, 28U },
2306 { VE::SF29, 29U },
2307 { VE::SF30, 30U },
2308 { VE::SF31, 31U },
2309 { VE::SF32, 32U },
2310 { VE::SF33, 33U },
2311 { VE::SF34, 34U },
2312 { VE::SF35, 35U },
2313 { VE::SF36, 36U },
2314 { VE::SF37, 37U },
2315 { VE::SF38, 38U },
2316 { VE::SF39, 39U },
2317 { VE::SF40, 40U },
2318 { VE::SF41, 41U },
2319 { VE::SF42, 42U },
2320 { VE::SF43, 43U },
2321 { VE::SF44, 44U },
2322 { VE::SF45, 45U },
2323 { VE::SF46, 46U },
2324 { VE::SF47, 47U },
2325 { VE::SF48, 48U },
2326 { VE::SF49, 49U },
2327 { VE::SF50, 50U },
2328 { VE::SF51, 51U },
2329 { VE::SF52, 52U },
2330 { VE::SF53, 53U },
2331 { VE::SF54, 54U },
2332 { VE::SF55, 55U },
2333 { VE::SF56, 56U },
2334 { VE::SF57, 57U },
2335 { VE::SF58, 58U },
2336 { VE::SF59, 59U },
2337 { VE::SF60, 60U },
2338 { VE::SF61, 61U },
2339 { VE::SF62, 62U },
2340 { VE::SF63, 63U },
2341 { VE::SW0, 0U },
2342 { VE::SW1, 1U },
2343 { VE::SW2, 2U },
2344 { VE::SW3, 3U },
2345 { VE::SW4, 4U },
2346 { VE::SW5, 5U },
2347 { VE::SW6, 6U },
2348 { VE::SW7, 7U },
2349 { VE::SW8, 8U },
2350 { VE::SW9, 9U },
2351 { VE::SW10, 10U },
2352 { VE::SW11, 11U },
2353 { VE::SW12, 12U },
2354 { VE::SW13, 13U },
2355 { VE::SW14, 14U },
2356 { VE::SW15, 15U },
2357 { VE::SW16, 16U },
2358 { VE::SW17, 17U },
2359 { VE::SW18, 18U },
2360 { VE::SW19, 19U },
2361 { VE::SW20, 20U },
2362 { VE::SW21, 21U },
2363 { VE::SW22, 22U },
2364 { VE::SW23, 23U },
2365 { VE::SW24, 24U },
2366 { VE::SW25, 25U },
2367 { VE::SW26, 26U },
2368 { VE::SW27, 27U },
2369 { VE::SW28, 28U },
2370 { VE::SW29, 29U },
2371 { VE::SW30, 30U },
2372 { VE::SW31, 31U },
2373 { VE::SW32, 32U },
2374 { VE::SW33, 33U },
2375 { VE::SW34, 34U },
2376 { VE::SW35, 35U },
2377 { VE::SW36, 36U },
2378 { VE::SW37, 37U },
2379 { VE::SW38, 38U },
2380 { VE::SW39, 39U },
2381 { VE::SW40, 40U },
2382 { VE::SW41, 41U },
2383 { VE::SW42, 42U },
2384 { VE::SW43, 43U },
2385 { VE::SW44, 44U },
2386 { VE::SW45, 45U },
2387 { VE::SW46, 46U },
2388 { VE::SW47, 47U },
2389 { VE::SW48, 48U },
2390 { VE::SW49, 49U },
2391 { VE::SW50, 50U },
2392 { VE::SW51, 51U },
2393 { VE::SW52, 52U },
2394 { VE::SW53, 53U },
2395 { VE::SW54, 54U },
2396 { VE::SW55, 55U },
2397 { VE::SW56, 56U },
2398 { VE::SW57, 57U },
2399 { VE::SW58, 58U },
2400 { VE::SW59, 59U },
2401 { VE::SW60, 60U },
2402 { VE::SW61, 61U },
2403 { VE::SW62, 62U },
2404 { VE::SW63, 63U },
2405 { VE::SX0, 0U },
2406 { VE::SX1, 1U },
2407 { VE::SX2, 2U },
2408 { VE::SX3, 3U },
2409 { VE::SX4, 4U },
2410 { VE::SX5, 5U },
2411 { VE::SX6, 6U },
2412 { VE::SX7, 7U },
2413 { VE::SX8, 8U },
2414 { VE::SX9, 9U },
2415 { VE::SX10, 10U },
2416 { VE::SX11, 11U },
2417 { VE::SX12, 12U },
2418 { VE::SX13, 13U },
2419 { VE::SX14, 14U },
2420 { VE::SX15, 15U },
2421 { VE::SX16, 16U },
2422 { VE::SX17, 17U },
2423 { VE::SX18, 18U },
2424 { VE::SX19, 19U },
2425 { VE::SX20, 20U },
2426 { VE::SX21, 21U },
2427 { VE::SX22, 22U },
2428 { VE::SX23, 23U },
2429 { VE::SX24, 24U },
2430 { VE::SX25, 25U },
2431 { VE::SX26, 26U },
2432 { VE::SX27, 27U },
2433 { VE::SX28, 28U },
2434 { VE::SX29, 29U },
2435 { VE::SX30, 30U },
2436 { VE::SX31, 31U },
2437 { VE::SX32, 32U },
2438 { VE::SX33, 33U },
2439 { VE::SX34, 34U },
2440 { VE::SX35, 35U },
2441 { VE::SX36, 36U },
2442 { VE::SX37, 37U },
2443 { VE::SX38, 38U },
2444 { VE::SX39, 39U },
2445 { VE::SX40, 40U },
2446 { VE::SX41, 41U },
2447 { VE::SX42, 42U },
2448 { VE::SX43, 43U },
2449 { VE::SX44, 44U },
2450 { VE::SX45, 45U },
2451 { VE::SX46, 46U },
2452 { VE::SX47, 47U },
2453 { VE::SX48, 48U },
2454 { VE::SX49, 49U },
2455 { VE::SX50, 50U },
2456 { VE::SX51, 51U },
2457 { VE::SX52, 52U },
2458 { VE::SX53, 53U },
2459 { VE::SX54, 54U },
2460 { VE::SX55, 55U },
2461 { VE::SX56, 56U },
2462 { VE::SX57, 57U },
2463 { VE::SX58, 58U },
2464 { VE::SX59, 59U },
2465 { VE::SX60, 60U },
2466 { VE::SX61, 61U },
2467 { VE::SX62, 62U },
2468 { VE::SX63, 63U },
2469 { VE::V0, 64U },
2470 { VE::V1, 65U },
2471 { VE::V2, 66U },
2472 { VE::V3, 67U },
2473 { VE::V4, 68U },
2474 { VE::V5, 69U },
2475 { VE::V6, 70U },
2476 { VE::V7, 71U },
2477 { VE::V8, 72U },
2478 { VE::V9, 73U },
2479 { VE::V10, 74U },
2480 { VE::V11, 75U },
2481 { VE::V12, 76U },
2482 { VE::V13, 77U },
2483 { VE::V14, 78U },
2484 { VE::V15, 79U },
2485 { VE::V16, 80U },
2486 { VE::V17, 81U },
2487 { VE::V18, 82U },
2488 { VE::V19, 83U },
2489 { VE::V20, 84U },
2490 { VE::V21, 85U },
2491 { VE::V22, 86U },
2492 { VE::V23, 87U },
2493 { VE::V24, 88U },
2494 { VE::V25, 89U },
2495 { VE::V26, 90U },
2496 { VE::V27, 91U },
2497 { VE::V28, 92U },
2498 { VE::V29, 93U },
2499 { VE::V30, 94U },
2500 { VE::V31, 95U },
2501 { VE::V32, 96U },
2502 { VE::V33, 97U },
2503 { VE::V34, 98U },
2504 { VE::V35, 99U },
2505 { VE::V36, 100U },
2506 { VE::V37, 101U },
2507 { VE::V38, 102U },
2508 { VE::V39, 103U },
2509 { VE::V40, 104U },
2510 { VE::V41, 105U },
2511 { VE::V42, 106U },
2512 { VE::V43, 107U },
2513 { VE::V44, 108U },
2514 { VE::V45, 109U },
2515 { VE::V46, 110U },
2516 { VE::V47, 111U },
2517 { VE::V48, 112U },
2518 { VE::V49, 113U },
2519 { VE::V50, 114U },
2520 { VE::V51, 115U },
2521 { VE::V52, 116U },
2522 { VE::V53, 117U },
2523 { VE::V54, 118U },
2524 { VE::V55, 119U },
2525 { VE::V56, 120U },
2526 { VE::V57, 121U },
2527 { VE::V58, 122U },
2528 { VE::V59, 123U },
2529 { VE::V60, 124U },
2530 { VE::V61, 125U },
2531 { VE::V62, 126U },
2532 { VE::V63, 127U },
2533 { VE::VM0, 128U },
2534 { VE::VM1, 129U },
2535 { VE::VM2, 130U },
2536 { VE::VM3, 131U },
2537 { VE::VM4, 132U },
2538 { VE::VM5, 133U },
2539 { VE::VM6, 134U },
2540 { VE::VM7, 135U },
2541 { VE::VM8, 136U },
2542 { VE::VM9, 137U },
2543 { VE::VM10, 138U },
2544 { VE::VM11, 139U },
2545 { VE::VM12, 140U },
2546 { VE::VM13, 141U },
2547 { VE::VM14, 142U },
2548 { VE::VM15, 143U },
2549};
2550extern const unsigned VEEHFlavour0L2DwarfSize = std::size(VEEHFlavour0L2Dwarf);
2551
2552extern const uint16_t VERegEncodingTable[] = {
2553 0,
2554 62,
2555 7,
2556 1,
2557 2,
2558 0,
2559 255,
2560 63,
2561 16,
2562 17,
2563 18,
2564 19,
2565 20,
2566 21,
2567 22,
2568 23,
2569 24,
2570 25,
2571 26,
2572 27,
2573 28,
2574 29,
2575 30,
2576 8,
2577 9,
2578 10,
2579 11,
2580 0,
2581 2,
2582 4,
2583 6,
2584 8,
2585 10,
2586 12,
2587 14,
2588 16,
2589 18,
2590 20,
2591 22,
2592 24,
2593 26,
2594 28,
2595 30,
2596 32,
2597 34,
2598 36,
2599 38,
2600 40,
2601 42,
2602 44,
2603 46,
2604 48,
2605 50,
2606 52,
2607 54,
2608 56,
2609 58,
2610 60,
2611 62,
2612 0,
2613 1,
2614 2,
2615 3,
2616 4,
2617 5,
2618 6,
2619 7,
2620 8,
2621 9,
2622 10,
2623 11,
2624 12,
2625 13,
2626 14,
2627 15,
2628 16,
2629 17,
2630 18,
2631 19,
2632 20,
2633 21,
2634 22,
2635 23,
2636 24,
2637 25,
2638 26,
2639 27,
2640 28,
2641 29,
2642 30,
2643 31,
2644 32,
2645 33,
2646 34,
2647 35,
2648 36,
2649 37,
2650 38,
2651 39,
2652 40,
2653 41,
2654 42,
2655 43,
2656 44,
2657 45,
2658 46,
2659 47,
2660 48,
2661 49,
2662 50,
2663 51,
2664 52,
2665 53,
2666 54,
2667 55,
2668 56,
2669 57,
2670 58,
2671 59,
2672 60,
2673 61,
2674 62,
2675 63,
2676 0,
2677 1,
2678 2,
2679 3,
2680 4,
2681 5,
2682 6,
2683 7,
2684 8,
2685 9,
2686 10,
2687 11,
2688 12,
2689 13,
2690 14,
2691 15,
2692 16,
2693 17,
2694 18,
2695 19,
2696 20,
2697 21,
2698 22,
2699 23,
2700 24,
2701 25,
2702 26,
2703 27,
2704 28,
2705 29,
2706 30,
2707 31,
2708 32,
2709 33,
2710 34,
2711 35,
2712 36,
2713 37,
2714 38,
2715 39,
2716 40,
2717 41,
2718 42,
2719 43,
2720 44,
2721 45,
2722 46,
2723 47,
2724 48,
2725 49,
2726 50,
2727 51,
2728 52,
2729 53,
2730 54,
2731 55,
2732 56,
2733 57,
2734 58,
2735 59,
2736 60,
2737 61,
2738 62,
2739 63,
2740 0,
2741 1,
2742 2,
2743 3,
2744 4,
2745 5,
2746 6,
2747 7,
2748 8,
2749 9,
2750 10,
2751 11,
2752 12,
2753 13,
2754 14,
2755 15,
2756 16,
2757 17,
2758 18,
2759 19,
2760 20,
2761 21,
2762 22,
2763 23,
2764 24,
2765 25,
2766 26,
2767 27,
2768 28,
2769 29,
2770 30,
2771 31,
2772 32,
2773 33,
2774 34,
2775 35,
2776 36,
2777 37,
2778 38,
2779 39,
2780 40,
2781 41,
2782 42,
2783 43,
2784 44,
2785 45,
2786 46,
2787 47,
2788 48,
2789 49,
2790 50,
2791 51,
2792 52,
2793 53,
2794 54,
2795 55,
2796 56,
2797 57,
2798 58,
2799 59,
2800 60,
2801 61,
2802 62,
2803 63,
2804 0,
2805 1,
2806 2,
2807 3,
2808 4,
2809 5,
2810 6,
2811 7,
2812 8,
2813 9,
2814 10,
2815 11,
2816 12,
2817 13,
2818 14,
2819 15,
2820 16,
2821 17,
2822 18,
2823 19,
2824 20,
2825 21,
2826 22,
2827 23,
2828 24,
2829 25,
2830 26,
2831 27,
2832 28,
2833 29,
2834 30,
2835 31,
2836 32,
2837 33,
2838 34,
2839 35,
2840 36,
2841 37,
2842 38,
2843 39,
2844 40,
2845 41,
2846 42,
2847 43,
2848 44,
2849 45,
2850 46,
2851 47,
2852 48,
2853 49,
2854 50,
2855 51,
2856 52,
2857 53,
2858 54,
2859 55,
2860 56,
2861 57,
2862 58,
2863 59,
2864 60,
2865 61,
2866 62,
2867 63,
2868 0,
2869 1,
2870 2,
2871 3,
2872 4,
2873 5,
2874 6,
2875 7,
2876 8,
2877 9,
2878 10,
2879 11,
2880 12,
2881 13,
2882 14,
2883 15,
2884 0,
2885 2,
2886 4,
2887 6,
2888 8,
2889 10,
2890 12,
2891 14,
2892};
2893static inline void InitVEMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
2894 RI->InitMCRegisterInfo(VERegDesc, 339, RA, PC, VEMCRegisterClasses, 10, VERegUnitRoots, 299, VERegDiffLists, VELaneMaskLists, VERegStrings, VERegClassStrings, VESubRegIdxLists, 9,
2895VERegEncodingTable);
2896
2897 switch (DwarfFlavour) {
2898 default:
2899 llvm_unreachable("Unknown DWARF flavour");
2900 case 0:
2901 RI->mapDwarfRegsToLLVMRegs(VEDwarfFlavour0Dwarf2L, VEDwarfFlavour0Dwarf2LSize, false);
2902 break;
2903 }
2904 switch (EHFlavour) {
2905 default:
2906 llvm_unreachable("Unknown DWARF flavour");
2907 case 0:
2908 RI->mapDwarfRegsToLLVMRegs(VEEHFlavour0Dwarf2L, VEEHFlavour0Dwarf2LSize, true);
2909 break;
2910 }
2911 switch (DwarfFlavour) {
2912 default:
2913 llvm_unreachable("Unknown DWARF flavour");
2914 case 0:
2915 RI->mapLLVMRegsToDwarfRegs(VEDwarfFlavour0L2Dwarf, VEDwarfFlavour0L2DwarfSize, false);
2916 break;
2917 }
2918 switch (EHFlavour) {
2919 default:
2920 llvm_unreachable("Unknown DWARF flavour");
2921 case 0:
2922 RI->mapLLVMRegsToDwarfRegs(VEEHFlavour0L2Dwarf, VEEHFlavour0L2DwarfSize, true);
2923 break;
2924 }
2925}
2926
2927} // end namespace llvm
2928
2929#endif // GET_REGINFO_MC_DESC
2930
2931/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2932|* *|
2933|* Register Information Header Fragment *|
2934|* *|
2935|* Automatically generated file, do not edit! *|
2936|* *|
2937\*===----------------------------------------------------------------------===*/
2938
2939
2940#ifdef GET_REGINFO_HEADER
2941#undef GET_REGINFO_HEADER
2942
2943#include "llvm/CodeGen/TargetRegisterInfo.h"
2944
2945namespace llvm {
2946
2947class VEFrameLowering;
2948
2949struct VEGenRegisterInfo : public TargetRegisterInfo {
2950 explicit VEGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
2951 unsigned PC = 0, unsigned HwMode = 0);
2952 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
2953 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
2954 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2955 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2956 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
2957 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
2958 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
2959 unsigned getRegUnitWeight(unsigned RegUnit) const override;
2960 unsigned getNumRegPressureSets() const override;
2961 const char *getRegPressureSetName(unsigned Idx) const override;
2962 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
2963 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
2964 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
2965 ArrayRef<const char *> getRegMaskNames() const override;
2966 ArrayRef<const uint32_t *> getRegMasks() const override;
2967 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
2968 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
2969 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
2970 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
2971 bool isConstantPhysReg(MCRegister PhysReg) const override final;
2972 /// Devirtualized TargetFrameLowering.
2973 static const VEFrameLowering *getFrameLowering(
2974 const MachineFunction &MF);
2975};
2976
2977namespace VE { // Register classes
2978 extern const TargetRegisterClass F32RegClass;
2979 extern const TargetRegisterClass I32RegClass;
2980 extern const TargetRegisterClass VLSRegClass;
2981 extern const TargetRegisterClass I64RegClass;
2982 extern const TargetRegisterClass MISCRegClass;
2983 extern const TargetRegisterClass F128RegClass;
2984 extern const TargetRegisterClass VMRegClass;
2985 extern const TargetRegisterClass VM512RegClass;
2986 extern const TargetRegisterClass VM512_with_sub_vm_evenRegClass;
2987 extern const TargetRegisterClass V64RegClass;
2988} // end namespace VE
2989
2990} // end namespace llvm
2991
2992#endif // GET_REGINFO_HEADER
2993
2994/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2995|* *|
2996|* Target Register and Register Classes Information *|
2997|* *|
2998|* Automatically generated file, do not edit! *|
2999|* *|
3000\*===----------------------------------------------------------------------===*/
3001
3002
3003#ifdef GET_REGINFO_TARGET_DESC
3004#undef GET_REGINFO_TARGET_DESC
3005
3006namespace llvm {
3007
3008extern const MCRegisterClass VEMCRegisterClasses[];
3009
3010static const MVT::SimpleValueType VTLists[] = {
3011 /* 0 */ MVT::i32, MVT::Other,
3012 /* 2 */ MVT::i64, MVT::Other,
3013 /* 4 */ MVT::f32, MVT::Other,
3014 /* 6 */ MVT::i64, MVT::f64, MVT::Other,
3015 /* 9 */ MVT::f128, MVT::Other,
3016 /* 11 */ MVT::v256i1, MVT::Other,
3017 /* 13 */ MVT::v512i1, MVT::Other,
3018 /* 15 */ MVT::v256f64, MVT::v512i32, MVT::v512f32, MVT::v256i64, MVT::v256i32, MVT::v256f32, MVT::Other,
3019};
3020
3021static const char *SubRegIndexNameTable[] = { "sub_even", "sub_f32", "sub_i32", "sub_odd", "sub_vm_even", "sub_vm_odd", "sub_odd_then_sub_f32", "sub_odd_then_sub_i32", "" };
3022
3023static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
3024 { 65535, 65535 },
3025 { 0, 64 }, // sub_even
3026 { 0, 32 }, // sub_f32
3027 { 32, 32 }, // sub_i32
3028 { 64, 64 }, // sub_odd
3029 { 0, 256 }, // sub_vm_even
3030 { 256, 256 }, // sub_vm_odd
3031 { 64, 32 }, // sub_odd_then_sub_f32
3032 { 96, 32 }, // sub_odd_then_sub_i32
3033};
3034
3035
3036static const LaneBitmask SubRegIndexLaneMaskTable[] = {
3037 LaneBitmask::getAll(),
3038 LaneBitmask(0x0000000000000003), // sub_even
3039 LaneBitmask(0x0000000000000001), // sub_f32
3040 LaneBitmask(0x0000000000000002), // sub_i32
3041 LaneBitmask(0x0000000000000030), // sub_odd
3042 LaneBitmask(0x0000000000000004), // sub_vm_even
3043 LaneBitmask(0x0000000000000008), // sub_vm_odd
3044 LaneBitmask(0x0000000000000010), // sub_odd_then_sub_f32
3045 LaneBitmask(0x0000000000000020), // sub_odd_then_sub_i32
3046 };
3047
3048
3049
3050static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
3051 // Mode = 0 (Default)
3052 { 32, 32, 32, /*VTLists+*/4 }, // F32
3053 { 32, 32, 32, /*VTLists+*/0 }, // I32
3054 { 32, 32, 64, /*VTLists+*/0 }, // VLS
3055 { 64, 64, 64, /*VTLists+*/6 }, // I64
3056 { 64, 64, 64, /*VTLists+*/2 }, // MISC
3057 { 128, 128, 128, /*VTLists+*/9 }, // F128
3058 { 256, 256, 64, /*VTLists+*/11 }, // VM
3059 { 512, 512, 64, /*VTLists+*/13 }, // VM512
3060 { 512, 512, 64, /*VTLists+*/13 }, // VM512_with_sub_vm_even
3061 { 16384, 16384, 64, /*VTLists+*/15 }, // V64
3062};
3063static const uint32_t F32SubClassMask[] = {
3064 0x00000001,
3065 0x00000028, // sub_f32
3066 0x00000020, // sub_odd_then_sub_f32
3067};
3068
3069static const uint32_t I32SubClassMask[] = {
3070 0x00000002,
3071 0x00000028, // sub_i32
3072 0x00000020, // sub_odd_then_sub_i32
3073};
3074
3075static const uint32_t VLSSubClassMask[] = {
3076 0x00000004,
3077};
3078
3079static const uint32_t I64SubClassMask[] = {
3080 0x00000008,
3081 0x00000020, // sub_even
3082 0x00000020, // sub_odd
3083};
3084
3085static const uint32_t MISCSubClassMask[] = {
3086 0x00000010,
3087};
3088
3089static const uint32_t F128SubClassMask[] = {
3090 0x00000020,
3091};
3092
3093static const uint32_t VMSubClassMask[] = {
3094 0x00000040,
3095 0x00000100, // sub_vm_even
3096 0x00000100, // sub_vm_odd
3097};
3098
3099static const uint32_t VM512SubClassMask[] = {
3100 0x00000180,
3101};
3102
3103static const uint32_t VM512_with_sub_vm_evenSubClassMask[] = {
3104 0x00000100,
3105};
3106
3107static const uint32_t V64SubClassMask[] = {
3108 0x00000200,
3109};
3110
3111static const uint16_t SuperRegIdxSeqs[] = {
3112 /* 0 */ 1, 4, 0,
3113 /* 3 */ 5, 6, 0,
3114 /* 6 */ 2, 7, 0,
3115 /* 9 */ 3, 8, 0,
3116};
3117
3118static unsigned const VM512_with_sub_vm_evenSuperclasses[] = {
3119 VE::VM512RegClassID,
3120};
3121
3122
3123namespace VE { // Register class instances
3124 extern const TargetRegisterClass F32RegClass = {
3125 &VEMCRegisterClasses[F32RegClassID],
3126 F32SubClassMask,
3127 SuperRegIdxSeqs + 6,
3128 LaneBitmask(0x0000000000000001),
3129 0,
3130 false,
3131 0x00, /* TSFlags */
3132 false, /* HasDisjunctSubRegs */
3133 false, /* CoveredBySubRegs */
3134 nullptr, 0,
3135 nullptr
3136 };
3137
3138 extern const TargetRegisterClass I32RegClass = {
3139 &VEMCRegisterClasses[I32RegClassID],
3140 I32SubClassMask,
3141 SuperRegIdxSeqs + 9,
3142 LaneBitmask(0x0000000000000001),
3143 0,
3144 false,
3145 0x00, /* TSFlags */
3146 false, /* HasDisjunctSubRegs */
3147 false, /* CoveredBySubRegs */
3148 nullptr, 0,
3149 nullptr
3150 };
3151
3152 extern const TargetRegisterClass VLSRegClass = {
3153 &VEMCRegisterClasses[VLSRegClassID],
3154 VLSSubClassMask,
3155 SuperRegIdxSeqs + 2,
3156 LaneBitmask(0x0000000000000001),
3157 0,
3158 false,
3159 0x00, /* TSFlags */
3160 false, /* HasDisjunctSubRegs */
3161 false, /* CoveredBySubRegs */
3162 nullptr, 0,
3163 nullptr
3164 };
3165
3166 extern const TargetRegisterClass I64RegClass = {
3167 &VEMCRegisterClasses[I64RegClassID],
3168 I64SubClassMask,
3169 SuperRegIdxSeqs + 0,
3170 LaneBitmask(0x0000000000000003),
3171 0,
3172 false,
3173 0x00, /* TSFlags */
3174 true, /* HasDisjunctSubRegs */
3175 true, /* CoveredBySubRegs */
3176 nullptr, 0,
3177 nullptr
3178 };
3179
3180 extern const TargetRegisterClass MISCRegClass = {
3181 &VEMCRegisterClasses[MISCRegClassID],
3182 MISCSubClassMask,
3183 SuperRegIdxSeqs + 2,
3184 LaneBitmask(0x0000000000000001),
3185 0,
3186 false,
3187 0x00, /* TSFlags */
3188 false, /* HasDisjunctSubRegs */
3189 false, /* CoveredBySubRegs */
3190 nullptr, 0,
3191 nullptr
3192 };
3193
3194 extern const TargetRegisterClass F128RegClass = {
3195 &VEMCRegisterClasses[F128RegClassID],
3196 F128SubClassMask,
3197 SuperRegIdxSeqs + 2,
3198 LaneBitmask(0x0000000000000033),
3199 0,
3200 false,
3201 0x00, /* TSFlags */
3202 true, /* HasDisjunctSubRegs */
3203 true, /* CoveredBySubRegs */
3204 nullptr, 0,
3205 nullptr
3206 };
3207
3208 extern const TargetRegisterClass VMRegClass = {
3209 &VEMCRegisterClasses[VMRegClassID],
3210 VMSubClassMask,
3211 SuperRegIdxSeqs + 3,
3212 LaneBitmask(0x0000000000000001),
3213 0,
3214 false,
3215 0x00, /* TSFlags */
3216 false, /* HasDisjunctSubRegs */
3217 false, /* CoveredBySubRegs */
3218 nullptr, 0,
3219 nullptr
3220 };
3221
3222 extern const TargetRegisterClass VM512RegClass = {
3223 &VEMCRegisterClasses[VM512RegClassID],
3224 VM512SubClassMask,
3225 SuperRegIdxSeqs + 2,
3226 LaneBitmask(0x000000000000000C),
3227 0,
3228 false,
3229 0x00, /* TSFlags */
3230 true, /* HasDisjunctSubRegs */
3231 false, /* CoveredBySubRegs */
3232 nullptr, 0,
3233 nullptr
3234 };
3235
3236 extern const TargetRegisterClass VM512_with_sub_vm_evenRegClass = {
3237 &VEMCRegisterClasses[VM512_with_sub_vm_evenRegClassID],
3238 VM512_with_sub_vm_evenSubClassMask,
3239 SuperRegIdxSeqs + 2,
3240 LaneBitmask(0x000000000000000C),
3241 0,
3242 false,
3243 0x00, /* TSFlags */
3244 true, /* HasDisjunctSubRegs */
3245 true, /* CoveredBySubRegs */
3246 VM512_with_sub_vm_evenSuperclasses, 1,
3247 nullptr
3248 };
3249
3250 extern const TargetRegisterClass V64RegClass = {
3251 &VEMCRegisterClasses[V64RegClassID],
3252 V64SubClassMask,
3253 SuperRegIdxSeqs + 2,
3254 LaneBitmask(0x0000000000000001),
3255 0,
3256 false,
3257 0x00, /* TSFlags */
3258 false, /* HasDisjunctSubRegs */
3259 false, /* CoveredBySubRegs */
3260 nullptr, 0,
3261 nullptr
3262 };
3263
3264} // end namespace VE
3265
3266namespace {
3267 const TargetRegisterClass *const RegisterClasses[] = {
3268 &VE::F32RegClass,
3269 &VE::I32RegClass,
3270 &VE::VLSRegClass,
3271 &VE::I64RegClass,
3272 &VE::MISCRegClass,
3273 &VE::F128RegClass,
3274 &VE::VMRegClass,
3275 &VE::VM512RegClass,
3276 &VE::VM512_with_sub_vm_evenRegClass,
3277 &VE::V64RegClass,
3278 };
3279} // end anonymous namespace
3280
3281static const uint8_t CostPerUseTable[] = {
32820, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
3283
3284
3285static const bool InAllocatableClassTable[] = {
3286false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
3287
3288
3289static const TargetRegisterInfoDesc VERegInfoDesc = { // Extra Descriptors
3290CostPerUseTable, 1, InAllocatableClassTable};
3291
3292unsigned VEGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
3293 static const uint8_t RowMap[8] = {
3294 0, 0, 0, 1, 0, 0, 0, 0,
3295 };
3296 static const uint8_t Rows[2][8] = {
3297 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
3298 { 0, VE::sub_odd_then_sub_f32, VE::sub_odd_then_sub_i32, 0, 0, 0, 0, 0, },
3299 };
3300
3301 --IdxA; assert(IdxA < 8); (void) IdxA;
3302 --IdxB; assert(IdxB < 8);
3303 return Rows[RowMap[IdxA]][IdxB];
3304}
3305
3306unsigned VEGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
3307 static const uint8_t Table[8][8] = {
3308 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
3309 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
3310 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
3311 { 0, 0, 0, 0, 0, 0, VE::sub_f32, VE::sub_i32, },
3312 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
3313 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
3314 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
3315 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
3316 };
3317
3318 --IdxA; assert(IdxA < 8);
3319 --IdxB; assert(IdxB < 8);
3320 return Table[IdxA][IdxB];
3321 }
3322
3323 struct MaskRolOp {
3324 LaneBitmask Mask;
3325 uint8_t RotateLeft;
3326 };
3327 static const MaskRolOp LaneMaskComposeSequences[] = {
3328 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
3329 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
3330 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
3331 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
3332 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
3333 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 } // Sequence 10
3334 };
3335 static const uint8_t CompositeSequences[] = {
3336 0, // to sub_even
3337 0, // to sub_f32
3338 2, // to sub_i32
3339 4, // to sub_odd
3340 6, // to sub_vm_even
3341 8, // to sub_vm_odd
3342 4, // to sub_odd_then_sub_f32
3343 10 // to sub_odd_then_sub_i32
3344 };
3345
3346LaneBitmask VEGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
3347 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
3348 LaneBitmask Result;
3349 for (const MaskRolOp *Ops =
3350 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
3351 Ops->Mask.any(); ++Ops) {
3352 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
3353 if (unsigned S = Ops->RotateLeft)
3354 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
3355 else
3356 Result |= LaneBitmask(M);
3357 }
3358 return Result;
3359}
3360
3361LaneBitmask VEGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
3362 LaneMask &= getSubRegIndexLaneMask(IdxA);
3363 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
3364 LaneBitmask Result;
3365 for (const MaskRolOp *Ops =
3366 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
3367 Ops->Mask.any(); ++Ops) {
3368 LaneBitmask::Type M = LaneMask.getAsInteger();
3369 if (unsigned S = Ops->RotateLeft)
3370 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
3371 else
3372 Result |= LaneBitmask(M);
3373 }
3374 return Result;
3375}
3376
3377const TargetRegisterClass *VEGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
3378 static const uint8_t Table[10][8] = {
3379 { // F32
3380 0, // sub_even
3381 0, // sub_f32
3382 0, // sub_i32
3383 0, // sub_odd
3384 0, // sub_vm_even
3385 0, // sub_vm_odd
3386 0, // sub_odd_then_sub_f32
3387 0, // sub_odd_then_sub_i32
3388 },
3389 { // I32
3390 0, // sub_even
3391 0, // sub_f32
3392 0, // sub_i32
3393 0, // sub_odd
3394 0, // sub_vm_even
3395 0, // sub_vm_odd
3396 0, // sub_odd_then_sub_f32
3397 0, // sub_odd_then_sub_i32
3398 },
3399 { // VLS
3400 0, // sub_even
3401 0, // sub_f32
3402 0, // sub_i32
3403 0, // sub_odd
3404 0, // sub_vm_even
3405 0, // sub_vm_odd
3406 0, // sub_odd_then_sub_f32
3407 0, // sub_odd_then_sub_i32
3408 },
3409 { // I64
3410 0, // sub_even
3411 4, // sub_f32 -> I64
3412 4, // sub_i32 -> I64
3413 0, // sub_odd
3414 0, // sub_vm_even
3415 0, // sub_vm_odd
3416 0, // sub_odd_then_sub_f32
3417 0, // sub_odd_then_sub_i32
3418 },
3419 { // MISC
3420 0, // sub_even
3421 0, // sub_f32
3422 0, // sub_i32
3423 0, // sub_odd
3424 0, // sub_vm_even
3425 0, // sub_vm_odd
3426 0, // sub_odd_then_sub_f32
3427 0, // sub_odd_then_sub_i32
3428 },
3429 { // F128
3430 6, // sub_even -> F128
3431 6, // sub_f32 -> F128
3432 6, // sub_i32 -> F128
3433 6, // sub_odd -> F128
3434 0, // sub_vm_even
3435 0, // sub_vm_odd
3436 6, // sub_odd_then_sub_f32 -> F128
3437 6, // sub_odd_then_sub_i32 -> F128
3438 },
3439 { // VM
3440 0, // sub_even
3441 0, // sub_f32
3442 0, // sub_i32
3443 0, // sub_odd
3444 0, // sub_vm_even
3445 0, // sub_vm_odd
3446 0, // sub_odd_then_sub_f32
3447 0, // sub_odd_then_sub_i32
3448 },
3449 { // VM512
3450 0, // sub_even
3451 0, // sub_f32
3452 0, // sub_i32
3453 0, // sub_odd
3454 9, // sub_vm_even -> VM512_with_sub_vm_even
3455 9, // sub_vm_odd -> VM512_with_sub_vm_even
3456 0, // sub_odd_then_sub_f32
3457 0, // sub_odd_then_sub_i32
3458 },
3459 { // VM512_with_sub_vm_even
3460 0, // sub_even
3461 0, // sub_f32
3462 0, // sub_i32
3463 0, // sub_odd
3464 9, // sub_vm_even -> VM512_with_sub_vm_even
3465 9, // sub_vm_odd -> VM512_with_sub_vm_even
3466 0, // sub_odd_then_sub_f32
3467 0, // sub_odd_then_sub_i32
3468 },
3469 { // V64
3470 0, // sub_even
3471 0, // sub_f32
3472 0, // sub_i32
3473 0, // sub_odd
3474 0, // sub_vm_even
3475 0, // sub_vm_odd
3476 0, // sub_odd_then_sub_f32
3477 0, // sub_odd_then_sub_i32
3478 },
3479 };
3480 assert(RC && "Missing regclass");
3481 if (!Idx) return RC;
3482 --Idx;
3483 assert(Idx < 8 && "Bad subreg");
3484 unsigned TV = Table[RC->getID()][Idx];
3485 return TV ? getRegClass(TV - 1) : nullptr;
3486}
3487
3488const TargetRegisterClass *VEGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
3489 static const uint8_t Table[10][8] = {
3490 { // F32
3491 0, // F32:sub_even
3492 0, // F32:sub_f32
3493 0, // F32:sub_i32
3494 0, // F32:sub_odd
3495 0, // F32:sub_vm_even
3496 0, // F32:sub_vm_odd
3497 0, // F32:sub_odd_then_sub_f32
3498 0, // F32:sub_odd_then_sub_i32
3499 },
3500 { // I32
3501 0, // I32:sub_even
3502 0, // I32:sub_f32
3503 0, // I32:sub_i32
3504 0, // I32:sub_odd
3505 0, // I32:sub_vm_even
3506 0, // I32:sub_vm_odd
3507 0, // I32:sub_odd_then_sub_f32
3508 0, // I32:sub_odd_then_sub_i32
3509 },
3510 { // VLS
3511 0, // VLS:sub_even
3512 0, // VLS:sub_f32
3513 0, // VLS:sub_i32
3514 0, // VLS:sub_odd
3515 0, // VLS:sub_vm_even
3516 0, // VLS:sub_vm_odd
3517 0, // VLS:sub_odd_then_sub_f32
3518 0, // VLS:sub_odd_then_sub_i32
3519 },
3520 { // I64
3521 0, // I64:sub_even
3522 1, // I64:sub_f32 -> F32
3523 2, // I64:sub_i32 -> I32
3524 0, // I64:sub_odd
3525 0, // I64:sub_vm_even
3526 0, // I64:sub_vm_odd
3527 0, // I64:sub_odd_then_sub_f32
3528 0, // I64:sub_odd_then_sub_i32
3529 },
3530 { // MISC
3531 0, // MISC:sub_even
3532 0, // MISC:sub_f32
3533 0, // MISC:sub_i32
3534 0, // MISC:sub_odd
3535 0, // MISC:sub_vm_even
3536 0, // MISC:sub_vm_odd
3537 0, // MISC:sub_odd_then_sub_f32
3538 0, // MISC:sub_odd_then_sub_i32
3539 },
3540 { // F128
3541 4, // F128:sub_even -> I64
3542 1, // F128:sub_f32 -> F32
3543 2, // F128:sub_i32 -> I32
3544 4, // F128:sub_odd -> I64
3545 0, // F128:sub_vm_even
3546 0, // F128:sub_vm_odd
3547 1, // F128:sub_odd_then_sub_f32 -> F32
3548 2, // F128:sub_odd_then_sub_i32 -> I32
3549 },
3550 { // VM
3551 0, // VM:sub_even
3552 0, // VM:sub_f32
3553 0, // VM:sub_i32
3554 0, // VM:sub_odd
3555 0, // VM:sub_vm_even
3556 0, // VM:sub_vm_odd
3557 0, // VM:sub_odd_then_sub_f32
3558 0, // VM:sub_odd_then_sub_i32
3559 },
3560 { // VM512
3561 0, // VM512:sub_even
3562 0, // VM512:sub_f32
3563 0, // VM512:sub_i32
3564 0, // VM512:sub_odd
3565 7, // VM512:sub_vm_even -> VM
3566 7, // VM512:sub_vm_odd -> VM
3567 0, // VM512:sub_odd_then_sub_f32
3568 0, // VM512:sub_odd_then_sub_i32
3569 },
3570 { // VM512_with_sub_vm_even
3571 0, // VM512_with_sub_vm_even:sub_even
3572 0, // VM512_with_sub_vm_even:sub_f32
3573 0, // VM512_with_sub_vm_even:sub_i32
3574 0, // VM512_with_sub_vm_even:sub_odd
3575 7, // VM512_with_sub_vm_even:sub_vm_even -> VM
3576 7, // VM512_with_sub_vm_even:sub_vm_odd -> VM
3577 0, // VM512_with_sub_vm_even:sub_odd_then_sub_f32
3578 0, // VM512_with_sub_vm_even:sub_odd_then_sub_i32
3579 },
3580 { // V64
3581 0, // V64:sub_even
3582 0, // V64:sub_f32
3583 0, // V64:sub_i32
3584 0, // V64:sub_odd
3585 0, // V64:sub_vm_even
3586 0, // V64:sub_vm_odd
3587 0, // V64:sub_odd_then_sub_f32
3588 0, // V64:sub_odd_then_sub_i32
3589 },
3590 };
3591 assert(RC && "Missing regclass");
3592 if (!Idx) return RC;
3593 --Idx;
3594 assert(Idx < 8 && "Bad subreg");
3595 unsigned TV = Table[RC->getID()][Idx];
3596 return TV ? getRegClass(TV - 1) : nullptr;
3597}
3598
3599/// Get the weight in units of pressure for this register class.
3600const RegClassWeight &VEGenRegisterInfo::
3601getRegClassWeight(const TargetRegisterClass *RC) const {
3602 static const RegClassWeight RCWeightTable[] = {
3603 {2, 128}, // F32
3604 {2, 128}, // I32
3605 {1, 1}, // VLS
3606 {3, 192}, // I64
3607 {1, 23}, // MISC
3608 {6, 192}, // F128
3609 {1, 16}, // VM
3610 {2, 16}, // VM512
3611 {2, 14}, // VM512_with_sub_vm_even
3612 {1, 65}, // V64
3613 };
3614 return RCWeightTable[RC->getID()];
3615}
3616
3617/// Get the weight in units of pressure for this register unit.
3618unsigned VEGenRegisterInfo::
3619getRegUnitWeight(unsigned RegUnit) const {
3620 assert(RegUnit < 299 && "invalid register unit");
3621 static const uint8_t RUWeightTable[] = {
3622 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, };
3623 return RUWeightTable[RegUnit];
3624}
3625
3626
3627// Get the number of dimensions of register pressure.
3628unsigned VEGenRegisterInfo::getNumRegPressureSets() const {
3629 return 9;
3630}
3631
3632// Get the name of this register unit pressure set.
3633const char *VEGenRegisterInfo::
3634getRegPressureSetName(unsigned Idx) const {
3635 static const char *PressureNameTable[] = {
3636 "VLS",
3637 "VM512",
3638 "VM",
3639 "VM_with_VM512",
3640 "MISC",
3641 "V64",
3642 "F32",
3643 "I32",
3644 "I64",
3645 };
3646 return PressureNameTable[Idx];
3647}
3648
3649// Get the register unit pressure limit for this dimension.
3650// This limit must be adjusted dynamically for reserved registers.
3651unsigned VEGenRegisterInfo::
3652getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
3653 static const uint8_t PressureLimitTable[] = {
3654 1, // 0: VLS
3655 16, // 1: VM512
3656 16, // 2: VM
3657 18, // 3: VM_with_VM512
3658 23, // 4: MISC
3659 65, // 5: V64
3660 128, // 6: F32
3661 128, // 7: I32
3662 192, // 8: I64
3663 };
3664 return PressureLimitTable[Idx];
3665}
3666
3667/// Table of pressure sets per register class or unit.
3668static const int RCSetsTable[] = {
3669 /* 0 */ 0, -1,
3670 /* 2 */ 1, 3, -1,
3671 /* 5 */ 1, 2, 3, -1,
3672 /* 9 */ 4, -1,
3673 /* 11 */ 5, -1,
3674 /* 13 */ 6, 8, -1,
3675 /* 16 */ 6, 7, 8, -1,
3676};
3677
3678/// Get the dimensions of register pressure impacted by this register class.
3679/// Returns a -1 terminated array of pressure set IDs
3680const int *VEGenRegisterInfo::
3681getRegClassPressureSets(const TargetRegisterClass *RC) const {
3682 static const uint8_t RCSetStartTable[] = {
3683 13,17,0,14,9,14,6,2,5,11,};
3684 return &RCSetsTable[RCSetStartTable[RC->getID()]];
3685}
3686
3687/// Get the dimensions of register pressure impacted by this register unit.
3688/// Returns a -1 terminated array of pressure set IDs
3689const int *VEGenRegisterInfo::
3690getRegUnitPressureSets(unsigned RegUnit) const {
3691 assert(RegUnit < 299 && "invalid register unit");
3692 static const uint8_t RUSetStartTable[] = {
3693 1,9,9,9,9,11,0,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,17,16,13,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,6,6,5,5,5,5,5,5,5,5,5,5,5,5,5,5,2,};
3694 return &RCSetsTable[RUSetStartTable[RegUnit]];
3695}
3696
3697extern const MCRegisterDesc VERegDesc[];
3698extern const int16_t VERegDiffLists[];
3699extern const LaneBitmask VELaneMaskLists[];
3700extern const char VERegStrings[];
3701extern const char VERegClassStrings[];
3702extern const MCPhysReg VERegUnitRoots[][2];
3703extern const uint16_t VESubRegIdxLists[];
3704extern const uint16_t VERegEncodingTable[];
3705// VE Dwarf<->LLVM register mappings.
3706extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0Dwarf2L[];
3707extern const unsigned VEDwarfFlavour0Dwarf2LSize;
3708
3709extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0Dwarf2L[];
3710extern const unsigned VEEHFlavour0Dwarf2LSize;
3711
3712extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0L2Dwarf[];
3713extern const unsigned VEDwarfFlavour0L2DwarfSize;
3714
3715extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0L2Dwarf[];
3716extern const unsigned VEEHFlavour0L2DwarfSize;
3717
3718VEGenRegisterInfo::
3719VEGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
3720 unsigned PC, unsigned HwMode)
3721 : TargetRegisterInfo(&VERegInfoDesc, RegisterClasses, RegisterClasses+10,
3722 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
3723 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
3724 InitMCRegisterInfo(VERegDesc, 339, RA, PC,
3725 VEMCRegisterClasses, 10,
3726 VERegUnitRoots,
3727 299,
3728 VERegDiffLists,
3729 VELaneMaskLists,
3730 VERegStrings,
3731 VERegClassStrings,
3732 VESubRegIdxLists,
3733 9,
3734 VERegEncodingTable);
3735
3736 switch (DwarfFlavour) {
3737 default:
3738 llvm_unreachable("Unknown DWARF flavour");
3739 case 0:
3740 mapDwarfRegsToLLVMRegs(VEDwarfFlavour0Dwarf2L, VEDwarfFlavour0Dwarf2LSize, false);
3741 break;
3742 }
3743 switch (EHFlavour) {
3744 default:
3745 llvm_unreachable("Unknown DWARF flavour");
3746 case 0:
3747 mapDwarfRegsToLLVMRegs(VEEHFlavour0Dwarf2L, VEEHFlavour0Dwarf2LSize, true);
3748 break;
3749 }
3750 switch (DwarfFlavour) {
3751 default:
3752 llvm_unreachable("Unknown DWARF flavour");
3753 case 0:
3754 mapLLVMRegsToDwarfRegs(VEDwarfFlavour0L2Dwarf, VEDwarfFlavour0L2DwarfSize, false);
3755 break;
3756 }
3757 switch (EHFlavour) {
3758 default:
3759 llvm_unreachable("Unknown DWARF flavour");
3760 case 0:
3761 mapLLVMRegsToDwarfRegs(VEEHFlavour0L2Dwarf, VEEHFlavour0L2DwarfSize, true);
3762 break;
3763 }
3764}
3765
3766static const MCPhysReg CSR_SaveList[] = { VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, 0 };
3767static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000ff0, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
3768static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
3769static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
3770static const MCPhysReg CSR_preserve_all_SaveList[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, VE::VM12, VE::VM13, VE::VM14, VE::VM15, 0 };
3771static const uint32_t CSR_preserve_all_RegMask[] = { 0xf8000000, 0xfbffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xffffffff, 0x0007ffff, };
3772
3773
3774ArrayRef<const uint32_t *> VEGenRegisterInfo::getRegMasks() const {
3775 static const uint32_t *const Masks[] = {
3776 CSR_RegMask,
3777 CSR_NoRegs_RegMask,
3778 CSR_preserve_all_RegMask,
3779 };
3780 return ArrayRef(Masks);
3781}
3782
3783bool VEGenRegisterInfo::
3784isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3785 return
3786 false;
3787}
3788
3789bool VEGenRegisterInfo::
3790isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
3791 return
3792 false;
3793}
3794
3795bool VEGenRegisterInfo::
3796isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3797 return
3798 false;
3799}
3800
3801bool VEGenRegisterInfo::
3802isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3803 return
3804 false;
3805}
3806
3807bool VEGenRegisterInfo::
3808isConstantPhysReg(MCRegister PhysReg) const {
3809 return
3810 PhysReg == VE::VM0 ||
3811 PhysReg == VE::VMP0 ||
3812 false;
3813}
3814
3815ArrayRef<const char *> VEGenRegisterInfo::getRegMaskNames() const {
3816 static const char *Names[] = {
3817 "CSR",
3818 "CSR_NoRegs",
3819 "CSR_preserve_all",
3820 };
3821 return ArrayRef(Names);
3822}
3823
3824const VEFrameLowering *
3825VEGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
3826 return static_cast<const VEFrameLowering *>(
3827 MF.getSubtarget().getFrameLowering());
3828}
3829
3830} // end namespace llvm
3831
3832#endif // GET_REGINFO_TARGET_DESC
3833
3834