1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace VE {
15enum {
16 FeatureEnableVPU = 0,
17 NumSubtargetFeatures = 1
18};
19} // end namespace VE
20} // end namespace llvm
21
22#endif // GET_SUBTARGETINFO_ENUM
23
24
25#ifdef GET_SUBTARGETINFO_MACRO
26GET_SUBTARGETINFO_MACRO(EnableVPU, false, enableVPU)
27#undef GET_SUBTARGETINFO_MACRO
28#endif // GET_SUBTARGETINFO_MACRO
29
30
31#ifdef GET_SUBTARGETINFO_MC_DESC
32#undef GET_SUBTARGETINFO_MC_DESC
33
34namespace llvm {
35// Sorted (by key) array of values for CPU features.
36extern const llvm::SubtargetFeatureKV VEFeatureKV[] = {
37 { "vpu", "Enable the VPU", VE::FeatureEnableVPU, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
38};
39
40#ifdef DBGFIELD
41#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
42#endif
43#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
44#define DBGFIELD(x) x,
45#define DBGVAL_OR_NULLPTR(x) x
46#else
47#define DBGFIELD(x)
48#define DBGVAL_OR_NULLPTR(x) nullptr
49#endif
50
51// ===============================================================
52// Data tables for the new per-operand machine model.
53
54// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
55extern const llvm::MCWriteProcResEntry VEWriteProcResTable[] = {
56 { 0, 0, 0 }, // Invalid
57}; // VEWriteProcResTable
58
59// {Cycles, WriteResourceID}
60extern const llvm::MCWriteLatencyEntry VEWriteLatencyTable[] = {
61 { 0, 0}, // Invalid
62}; // VEWriteLatencyTable
63
64// {UseIdx, WriteResourceID, Cycles}
65extern const llvm::MCReadAdvanceEntry VEReadAdvanceTable[] = {
66 {0, 0, 0}, // Invalid
67}; // VEReadAdvanceTable
68
69#ifdef __GNUC__
70#pragma GCC diagnostic push
71#pragma GCC diagnostic ignored "-Woverlength-strings"
72#endif
73static constexpr char VESchedClassNamesStorage[] =
74 "\0"
75 "InvalidSchedClass\0"
76 ;
77#ifdef __GNUC__
78#pragma GCC diagnostic pop
79#endif
80
81static constexpr llvm::StringTable VESchedClassNames =
82 VESchedClassNamesStorage;
83
84static const llvm::MCSchedModel NoSchedModel = {
85 MCSchedModel::DefaultIssueWidth,
86 MCSchedModel::DefaultMicroOpBufferSize,
87 MCSchedModel::DefaultLoopMicroOpBufferSize,
88 MCSchedModel::DefaultLoadLatency,
89 MCSchedModel::DefaultHighLatency,
90 MCSchedModel::DefaultMispredictPenalty,
91 false, // PostRAScheduler
92 false, // CompleteModel
93 false, // EnableIntervals
94 0, // Processor ID
95 nullptr, nullptr, 0, 0, // No instruction-level machine model.
96 DBGVAL_OR_NULLPTR(&VESchedClassNames), // SchedClassNames
97 nullptr, // No Itinerary
98 nullptr // No extra processor descriptor
99};
100
101#undef DBGFIELD
102
103#undef DBGVAL_OR_NULLPTR
104
105// Sorted (by key) array of values for CPU subtype.
106extern const llvm::SubtargetSubTypeKV VESubTypeKV[] = {
107 { "generic", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
108};
109
110// Sorted array of names of CPU subtypes, including aliases.
111extern const llvm::StringRef VENames[] = {
112"generic"};
113
114namespace VE_MC {
115unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
116 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
117 // Don't know how to resolve this scheduling class.
118 return 0;
119}
120} // end namespace VE_MC
121
122struct VEGenMCSubtargetInfo : public MCSubtargetInfo {
123 VEGenMCSubtargetInfo(const Triple &TT,
124 StringRef CPU, StringRef TuneCPU, StringRef FS,
125 ArrayRef<StringRef> PN,
126 ArrayRef<SubtargetFeatureKV> PF,
127 ArrayRef<SubtargetSubTypeKV> PD,
128 const MCWriteProcResEntry *WPR,
129 const MCWriteLatencyEntry *WL,
130 const MCReadAdvanceEntry *RA, const InstrStage *IS,
131 const unsigned *OC, const unsigned *FP) :
132 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
133 WPR, WL, RA, IS, OC, FP) { }
134
135 unsigned resolveVariantSchedClass(unsigned SchedClass,
136 const MCInst *MI, const MCInstrInfo *MCII,
137 unsigned CPUID) const override {
138 return VE_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
139 }
140};
141
142static inline MCSubtargetInfo *createVEMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
143 return new VEGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, VENames, VEFeatureKV, VESubTypeKV,
144 VEWriteProcResTable, VEWriteLatencyTable, VEReadAdvanceTable,
145 nullptr, nullptr, nullptr);
146}
147
148} // end namespace llvm
149
150#endif // GET_SUBTARGETINFO_MC_DESC
151
152
153#ifdef GET_SUBTARGETINFO_TARGET_DESC
154#undef GET_SUBTARGETINFO_TARGET_DESC
155
156#include "llvm/ADT/BitmaskEnum.h"
157#include "llvm/Support/Debug.h"
158#include "llvm/Support/raw_ostream.h"
159
160// ParseSubtargetFeatures - Parses features string setting specified
161// subtarget options.
162void llvm::VESubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
163 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
164 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
165 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
166 InitMCProcessorInfo(CPU, TuneCPU, FS);
167 const FeatureBitset &Bits = getFeatureBits();
168 if (Bits[VE::FeatureEnableVPU]) EnableVPU = true;
169}
170#endif // GET_SUBTARGETINFO_TARGET_DESC
171
172
173#ifdef GET_SUBTARGETINFO_HEADER
174#undef GET_SUBTARGETINFO_HEADER
175
176namespace llvm {
177class DFAPacketizer;
178namespace VE_MC {
179unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
180} // end namespace VE_MC
181
182struct VEGenSubtargetInfo : public TargetSubtargetInfo {
183 explicit VEGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
184public:
185 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
186 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
187 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
188};
189} // end namespace llvm
190
191#endif // GET_SUBTARGETINFO_HEADER
192
193
194#ifdef GET_SUBTARGETINFO_CTOR
195#undef GET_SUBTARGETINFO_CTOR
196
197#include "llvm/CodeGen/TargetSchedule.h"
198
199namespace llvm {
200extern const llvm::StringRef VENames[];
201extern const llvm::SubtargetFeatureKV VEFeatureKV[];
202extern const llvm::SubtargetSubTypeKV VESubTypeKV[];
203extern const llvm::MCWriteProcResEntry VEWriteProcResTable[];
204extern const llvm::MCWriteLatencyEntry VEWriteLatencyTable[];
205extern const llvm::MCReadAdvanceEntry VEReadAdvanceTable[];
206VEGenSubtargetInfo::VEGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
207 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(VENames, 1), ArrayRef(VEFeatureKV, 1), ArrayRef(VESubTypeKV, 1),
208 VEWriteProcResTable, VEWriteLatencyTable, VEReadAdvanceTable,
209 nullptr, nullptr, nullptr) {}
210
211unsigned VEGenSubtargetInfo
212::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
213 report_fatal_error("Expected a variant SchedClass");
214} // VEGenSubtargetInfo::resolveSchedClass
215
216unsigned VEGenSubtargetInfo
217::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
218 return VE_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
219} // VEGenSubtargetInfo::resolveVariantSchedClass
220
221} // end namespace llvm
222
223#endif // GET_SUBTARGETINFO_CTOR
224
225
226#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
227#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
228
229#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
230
231
232#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
233#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
234
235#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
236
237