1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm::WebAssembly {
12 enum {
13 PHI = 0,
14 INLINEASM = 1,
15 INLINEASM_BR = 2,
16 CFI_INSTRUCTION = 3,
17 EH_LABEL = 4,
18 GC_LABEL = 5,
19 ANNOTATION_LABEL = 6,
20 KILL = 7,
21 EXTRACT_SUBREG = 8,
22 INSERT_SUBREG = 9,
23 IMPLICIT_DEF = 10,
24 INIT_UNDEF = 11,
25 SUBREG_TO_REG = 12,
26 COPY_TO_REGCLASS = 13,
27 DBG_VALUE = 14,
28 DBG_VALUE_LIST = 15,
29 DBG_INSTR_REF = 16,
30 DBG_PHI = 17,
31 DBG_LABEL = 18,
32 REG_SEQUENCE = 19,
33 COPY = 20,
34 BUNDLE = 21,
35 LIFETIME_START = 22,
36 LIFETIME_END = 23,
37 PSEUDO_PROBE = 24,
38 ARITH_FENCE = 25,
39 STACKMAP = 26,
40 FENTRY_CALL = 27,
41 PATCHPOINT = 28,
42 LOAD_STACK_GUARD = 29,
43 PREALLOCATED_SETUP = 30,
44 PREALLOCATED_ARG = 31,
45 STATEPOINT = 32,
46 LOCAL_ESCAPE = 33,
47 FAULTING_OP = 34,
48 PATCHABLE_OP = 35,
49 PATCHABLE_FUNCTION_ENTER = 36,
50 PATCHABLE_RET = 37,
51 PATCHABLE_FUNCTION_EXIT = 38,
52 PATCHABLE_TAIL_CALL = 39,
53 PATCHABLE_EVENT_CALL = 40,
54 PATCHABLE_TYPED_EVENT_CALL = 41,
55 ICALL_BRANCH_FUNNEL = 42,
56 FAKE_USE = 43,
57 MEMBARRIER = 44,
58 JUMP_TABLE_DEBUG_INFO = 45,
59 CONVERGENCECTRL_ENTRY = 46,
60 CONVERGENCECTRL_ANCHOR = 47,
61 CONVERGENCECTRL_LOOP = 48,
62 CONVERGENCECTRL_GLUE = 49,
63 G_ASSERT_SEXT = 50,
64 G_ASSERT_ZEXT = 51,
65 G_ASSERT_ALIGN = 52,
66 G_ADD = 53,
67 G_SUB = 54,
68 G_MUL = 55,
69 G_SDIV = 56,
70 G_UDIV = 57,
71 G_SREM = 58,
72 G_UREM = 59,
73 G_SDIVREM = 60,
74 G_UDIVREM = 61,
75 G_AND = 62,
76 G_OR = 63,
77 G_XOR = 64,
78 G_ABDS = 65,
79 G_ABDU = 66,
80 G_IMPLICIT_DEF = 67,
81 G_PHI = 68,
82 G_FRAME_INDEX = 69,
83 G_GLOBAL_VALUE = 70,
84 G_PTRAUTH_GLOBAL_VALUE = 71,
85 G_CONSTANT_POOL = 72,
86 G_EXTRACT = 73,
87 G_UNMERGE_VALUES = 74,
88 G_INSERT = 75,
89 G_MERGE_VALUES = 76,
90 G_BUILD_VECTOR = 77,
91 G_BUILD_VECTOR_TRUNC = 78,
92 G_CONCAT_VECTORS = 79,
93 G_PTRTOINT = 80,
94 G_INTTOPTR = 81,
95 G_BITCAST = 82,
96 G_FREEZE = 83,
97 G_CONSTANT_FOLD_BARRIER = 84,
98 G_INTRINSIC_FPTRUNC_ROUND = 85,
99 G_INTRINSIC_TRUNC = 86,
100 G_INTRINSIC_ROUND = 87,
101 G_INTRINSIC_LRINT = 88,
102 G_INTRINSIC_LLRINT = 89,
103 G_INTRINSIC_ROUNDEVEN = 90,
104 G_READCYCLECOUNTER = 91,
105 G_READSTEADYCOUNTER = 92,
106 G_LOAD = 93,
107 G_SEXTLOAD = 94,
108 G_ZEXTLOAD = 95,
109 G_INDEXED_LOAD = 96,
110 G_INDEXED_SEXTLOAD = 97,
111 G_INDEXED_ZEXTLOAD = 98,
112 G_STORE = 99,
113 G_INDEXED_STORE = 100,
114 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101,
115 G_ATOMIC_CMPXCHG = 102,
116 G_ATOMICRMW_XCHG = 103,
117 G_ATOMICRMW_ADD = 104,
118 G_ATOMICRMW_SUB = 105,
119 G_ATOMICRMW_AND = 106,
120 G_ATOMICRMW_NAND = 107,
121 G_ATOMICRMW_OR = 108,
122 G_ATOMICRMW_XOR = 109,
123 G_ATOMICRMW_MAX = 110,
124 G_ATOMICRMW_MIN = 111,
125 G_ATOMICRMW_UMAX = 112,
126 G_ATOMICRMW_UMIN = 113,
127 G_ATOMICRMW_FADD = 114,
128 G_ATOMICRMW_FSUB = 115,
129 G_ATOMICRMW_FMAX = 116,
130 G_ATOMICRMW_FMIN = 117,
131 G_ATOMICRMW_FMAXIMUM = 118,
132 G_ATOMICRMW_FMINIMUM = 119,
133 G_ATOMICRMW_UINC_WRAP = 120,
134 G_ATOMICRMW_UDEC_WRAP = 121,
135 G_ATOMICRMW_USUB_COND = 122,
136 G_ATOMICRMW_USUB_SAT = 123,
137 G_FENCE = 124,
138 G_PREFETCH = 125,
139 G_BRCOND = 126,
140 G_BRINDIRECT = 127,
141 G_INVOKE_REGION_START = 128,
142 G_INTRINSIC = 129,
143 G_INTRINSIC_W_SIDE_EFFECTS = 130,
144 G_INTRINSIC_CONVERGENT = 131,
145 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132,
146 G_ANYEXT = 133,
147 G_TRUNC = 134,
148 G_CONSTANT = 135,
149 G_FCONSTANT = 136,
150 G_VASTART = 137,
151 G_VAARG = 138,
152 G_SEXT = 139,
153 G_SEXT_INREG = 140,
154 G_ZEXT = 141,
155 G_SHL = 142,
156 G_LSHR = 143,
157 G_ASHR = 144,
158 G_FSHL = 145,
159 G_FSHR = 146,
160 G_ROTR = 147,
161 G_ROTL = 148,
162 G_ICMP = 149,
163 G_FCMP = 150,
164 G_SCMP = 151,
165 G_UCMP = 152,
166 G_SELECT = 153,
167 G_UADDO = 154,
168 G_UADDE = 155,
169 G_USUBO = 156,
170 G_USUBE = 157,
171 G_SADDO = 158,
172 G_SADDE = 159,
173 G_SSUBO = 160,
174 G_SSUBE = 161,
175 G_UMULO = 162,
176 G_SMULO = 163,
177 G_UMULH = 164,
178 G_SMULH = 165,
179 G_UADDSAT = 166,
180 G_SADDSAT = 167,
181 G_USUBSAT = 168,
182 G_SSUBSAT = 169,
183 G_USHLSAT = 170,
184 G_SSHLSAT = 171,
185 G_SMULFIX = 172,
186 G_UMULFIX = 173,
187 G_SMULFIXSAT = 174,
188 G_UMULFIXSAT = 175,
189 G_SDIVFIX = 176,
190 G_UDIVFIX = 177,
191 G_SDIVFIXSAT = 178,
192 G_UDIVFIXSAT = 179,
193 G_FADD = 180,
194 G_FSUB = 181,
195 G_FMUL = 182,
196 G_FMA = 183,
197 G_FMAD = 184,
198 G_FDIV = 185,
199 G_FREM = 186,
200 G_FPOW = 187,
201 G_FPOWI = 188,
202 G_FEXP = 189,
203 G_FEXP2 = 190,
204 G_FEXP10 = 191,
205 G_FLOG = 192,
206 G_FLOG2 = 193,
207 G_FLOG10 = 194,
208 G_FLDEXP = 195,
209 G_FFREXP = 196,
210 G_FNEG = 197,
211 G_FPEXT = 198,
212 G_FPTRUNC = 199,
213 G_FPTOSI = 200,
214 G_FPTOUI = 201,
215 G_SITOFP = 202,
216 G_UITOFP = 203,
217 G_FPTOSI_SAT = 204,
218 G_FPTOUI_SAT = 205,
219 G_FABS = 206,
220 G_FCOPYSIGN = 207,
221 G_IS_FPCLASS = 208,
222 G_FCANONICALIZE = 209,
223 G_FMINNUM = 210,
224 G_FMAXNUM = 211,
225 G_FMINNUM_IEEE = 212,
226 G_FMAXNUM_IEEE = 213,
227 G_FMINIMUM = 214,
228 G_FMAXIMUM = 215,
229 G_FMINIMUMNUM = 216,
230 G_FMAXIMUMNUM = 217,
231 G_GET_FPENV = 218,
232 G_SET_FPENV = 219,
233 G_RESET_FPENV = 220,
234 G_GET_FPMODE = 221,
235 G_SET_FPMODE = 222,
236 G_RESET_FPMODE = 223,
237 G_PTR_ADD = 224,
238 G_PTRMASK = 225,
239 G_SMIN = 226,
240 G_SMAX = 227,
241 G_UMIN = 228,
242 G_UMAX = 229,
243 G_ABS = 230,
244 G_LROUND = 231,
245 G_LLROUND = 232,
246 G_BR = 233,
247 G_BRJT = 234,
248 G_VSCALE = 235,
249 G_INSERT_SUBVECTOR = 236,
250 G_EXTRACT_SUBVECTOR = 237,
251 G_INSERT_VECTOR_ELT = 238,
252 G_EXTRACT_VECTOR_ELT = 239,
253 G_SHUFFLE_VECTOR = 240,
254 G_SPLAT_VECTOR = 241,
255 G_STEP_VECTOR = 242,
256 G_VECTOR_COMPRESS = 243,
257 G_CTTZ = 244,
258 G_CTTZ_ZERO_UNDEF = 245,
259 G_CTLZ = 246,
260 G_CTLZ_ZERO_UNDEF = 247,
261 G_CTPOP = 248,
262 G_BSWAP = 249,
263 G_BITREVERSE = 250,
264 G_FCEIL = 251,
265 G_FCOS = 252,
266 G_FSIN = 253,
267 G_FSINCOS = 254,
268 G_FTAN = 255,
269 G_FACOS = 256,
270 G_FASIN = 257,
271 G_FATAN = 258,
272 G_FATAN2 = 259,
273 G_FCOSH = 260,
274 G_FSINH = 261,
275 G_FTANH = 262,
276 G_FSQRT = 263,
277 G_FFLOOR = 264,
278 G_FRINT = 265,
279 G_FNEARBYINT = 266,
280 G_ADDRSPACE_CAST = 267,
281 G_BLOCK_ADDR = 268,
282 G_JUMP_TABLE = 269,
283 G_DYN_STACKALLOC = 270,
284 G_STACKSAVE = 271,
285 G_STACKRESTORE = 272,
286 G_STRICT_FADD = 273,
287 G_STRICT_FSUB = 274,
288 G_STRICT_FMUL = 275,
289 G_STRICT_FDIV = 276,
290 G_STRICT_FREM = 277,
291 G_STRICT_FMA = 278,
292 G_STRICT_FSQRT = 279,
293 G_STRICT_FLDEXP = 280,
294 G_READ_REGISTER = 281,
295 G_WRITE_REGISTER = 282,
296 G_MEMCPY = 283,
297 G_MEMCPY_INLINE = 284,
298 G_MEMMOVE = 285,
299 G_MEMSET = 286,
300 G_BZERO = 287,
301 G_TRAP = 288,
302 G_DEBUGTRAP = 289,
303 G_UBSANTRAP = 290,
304 G_VECREDUCE_SEQ_FADD = 291,
305 G_VECREDUCE_SEQ_FMUL = 292,
306 G_VECREDUCE_FADD = 293,
307 G_VECREDUCE_FMUL = 294,
308 G_VECREDUCE_FMAX = 295,
309 G_VECREDUCE_FMIN = 296,
310 G_VECREDUCE_FMAXIMUM = 297,
311 G_VECREDUCE_FMINIMUM = 298,
312 G_VECREDUCE_ADD = 299,
313 G_VECREDUCE_MUL = 300,
314 G_VECREDUCE_AND = 301,
315 G_VECREDUCE_OR = 302,
316 G_VECREDUCE_XOR = 303,
317 G_VECREDUCE_SMAX = 304,
318 G_VECREDUCE_SMIN = 305,
319 G_VECREDUCE_UMAX = 306,
320 G_VECREDUCE_UMIN = 307,
321 G_SBFX = 308,
322 G_UBFX = 309,
323 CALL_PARAMS = 310,
324 CALL_PARAMS_S = 311,
325 CALL_RESULTS = 312,
326 CALL_RESULTS_S = 313,
327 CATCHRET = 314,
328 CATCHRET_S = 315,
329 CLEANUPRET = 316,
330 CLEANUPRET_S = 317,
331 COMPILER_FENCE = 318,
332 COMPILER_FENCE_S = 319,
333 RET_CALL_RESULTS = 320,
334 RET_CALL_RESULTS_S = 321,
335 ABS_F16x8 = 322,
336 ABS_F16x8_S = 323,
337 ABS_F32 = 324,
338 ABS_F32_S = 325,
339 ABS_F32x4 = 326,
340 ABS_F32x4_S = 327,
341 ABS_F64 = 328,
342 ABS_F64_S = 329,
343 ABS_F64x2 = 330,
344 ABS_F64x2_S = 331,
345 ABS_I16x8 = 332,
346 ABS_I16x8_S = 333,
347 ABS_I32x4 = 334,
348 ABS_I32x4_S = 335,
349 ABS_I64x2 = 336,
350 ABS_I64x2_S = 337,
351 ABS_I8x16 = 338,
352 ABS_I8x16_S = 339,
353 ADD_F16x8 = 340,
354 ADD_F16x8_S = 341,
355 ADD_F32 = 342,
356 ADD_F32_S = 343,
357 ADD_F32x4 = 344,
358 ADD_F32x4_S = 345,
359 ADD_F64 = 346,
360 ADD_F64_S = 347,
361 ADD_F64x2 = 348,
362 ADD_F64x2_S = 349,
363 ADD_I16x8 = 350,
364 ADD_I16x8_S = 351,
365 ADD_I32 = 352,
366 ADD_I32_S = 353,
367 ADD_I32x4 = 354,
368 ADD_I32x4_S = 355,
369 ADD_I64 = 356,
370 ADD_I64_S = 357,
371 ADD_I64x2 = 358,
372 ADD_I64x2_S = 359,
373 ADD_I8x16 = 360,
374 ADD_I8x16_S = 361,
375 ADD_SAT_S_I16x8 = 362,
376 ADD_SAT_S_I16x8_S = 363,
377 ADD_SAT_S_I8x16 = 364,
378 ADD_SAT_S_I8x16_S = 365,
379 ADD_SAT_U_I16x8 = 366,
380 ADD_SAT_U_I16x8_S = 367,
381 ADD_SAT_U_I8x16 = 368,
382 ADD_SAT_U_I8x16_S = 369,
383 ADJCALLSTACKDOWN = 370,
384 ADJCALLSTACKDOWN_S = 371,
385 ADJCALLSTACKUP = 372,
386 ADJCALLSTACKUP_S = 373,
387 ALLTRUE_I16x8 = 374,
388 ALLTRUE_I16x8_S = 375,
389 ALLTRUE_I32x4 = 376,
390 ALLTRUE_I32x4_S = 377,
391 ALLTRUE_I64x2 = 378,
392 ALLTRUE_I64x2_S = 379,
393 ALLTRUE_I8x16 = 380,
394 ALLTRUE_I8x16_S = 381,
395 AND = 382,
396 ANDNOT = 383,
397 ANDNOT_S = 384,
398 AND_I32 = 385,
399 AND_I32_S = 386,
400 AND_I64 = 387,
401 AND_I64_S = 388,
402 AND_S = 389,
403 ANYTRUE = 390,
404 ANYTRUE_S = 391,
405 ARGUMENT_exnref = 392,
406 ARGUMENT_exnref_S = 393,
407 ARGUMENT_externref = 394,
408 ARGUMENT_externref_S = 395,
409 ARGUMENT_f32 = 396,
410 ARGUMENT_f32_S = 397,
411 ARGUMENT_f64 = 398,
412 ARGUMENT_f64_S = 399,
413 ARGUMENT_funcref = 400,
414 ARGUMENT_funcref_S = 401,
415 ARGUMENT_i32 = 402,
416 ARGUMENT_i32_S = 403,
417 ARGUMENT_i64 = 404,
418 ARGUMENT_i64_S = 405,
419 ARGUMENT_v16i8 = 406,
420 ARGUMENT_v16i8_S = 407,
421 ARGUMENT_v2f64 = 408,
422 ARGUMENT_v2f64_S = 409,
423 ARGUMENT_v2i64 = 410,
424 ARGUMENT_v2i64_S = 411,
425 ARGUMENT_v4f32 = 412,
426 ARGUMENT_v4f32_S = 413,
427 ARGUMENT_v4i32 = 414,
428 ARGUMENT_v4i32_S = 415,
429 ARGUMENT_v8f16 = 416,
430 ARGUMENT_v8f16_S = 417,
431 ARGUMENT_v8i16 = 418,
432 ARGUMENT_v8i16_S = 419,
433 ATOMIC_FENCE = 420,
434 ATOMIC_FENCE_S = 421,
435 ATOMIC_LOAD16_U_I32_A32 = 422,
436 ATOMIC_LOAD16_U_I32_A32_S = 423,
437 ATOMIC_LOAD16_U_I32_A64 = 424,
438 ATOMIC_LOAD16_U_I32_A64_S = 425,
439 ATOMIC_LOAD16_U_I64_A32 = 426,
440 ATOMIC_LOAD16_U_I64_A32_S = 427,
441 ATOMIC_LOAD16_U_I64_A64 = 428,
442 ATOMIC_LOAD16_U_I64_A64_S = 429,
443 ATOMIC_LOAD32_U_I64_A32 = 430,
444 ATOMIC_LOAD32_U_I64_A32_S = 431,
445 ATOMIC_LOAD32_U_I64_A64 = 432,
446 ATOMIC_LOAD32_U_I64_A64_S = 433,
447 ATOMIC_LOAD8_U_I32_A32 = 434,
448 ATOMIC_LOAD8_U_I32_A32_S = 435,
449 ATOMIC_LOAD8_U_I32_A64 = 436,
450 ATOMIC_LOAD8_U_I32_A64_S = 437,
451 ATOMIC_LOAD8_U_I64_A32 = 438,
452 ATOMIC_LOAD8_U_I64_A32_S = 439,
453 ATOMIC_LOAD8_U_I64_A64 = 440,
454 ATOMIC_LOAD8_U_I64_A64_S = 441,
455 ATOMIC_LOAD_I32_A32 = 442,
456 ATOMIC_LOAD_I32_A32_S = 443,
457 ATOMIC_LOAD_I32_A64 = 444,
458 ATOMIC_LOAD_I32_A64_S = 445,
459 ATOMIC_LOAD_I64_A32 = 446,
460 ATOMIC_LOAD_I64_A32_S = 447,
461 ATOMIC_LOAD_I64_A64 = 448,
462 ATOMIC_LOAD_I64_A64_S = 449,
463 ATOMIC_RMW16_U_ADD_I32_A32 = 450,
464 ATOMIC_RMW16_U_ADD_I32_A32_S = 451,
465 ATOMIC_RMW16_U_ADD_I32_A64 = 452,
466 ATOMIC_RMW16_U_ADD_I32_A64_S = 453,
467 ATOMIC_RMW16_U_ADD_I64_A32 = 454,
468 ATOMIC_RMW16_U_ADD_I64_A32_S = 455,
469 ATOMIC_RMW16_U_ADD_I64_A64 = 456,
470 ATOMIC_RMW16_U_ADD_I64_A64_S = 457,
471 ATOMIC_RMW16_U_AND_I32_A32 = 458,
472 ATOMIC_RMW16_U_AND_I32_A32_S = 459,
473 ATOMIC_RMW16_U_AND_I32_A64 = 460,
474 ATOMIC_RMW16_U_AND_I32_A64_S = 461,
475 ATOMIC_RMW16_U_AND_I64_A32 = 462,
476 ATOMIC_RMW16_U_AND_I64_A32_S = 463,
477 ATOMIC_RMW16_U_AND_I64_A64 = 464,
478 ATOMIC_RMW16_U_AND_I64_A64_S = 465,
479 ATOMIC_RMW16_U_CMPXCHG_I32_A32 = 466,
480 ATOMIC_RMW16_U_CMPXCHG_I32_A32_S = 467,
481 ATOMIC_RMW16_U_CMPXCHG_I32_A64 = 468,
482 ATOMIC_RMW16_U_CMPXCHG_I32_A64_S = 469,
483 ATOMIC_RMW16_U_CMPXCHG_I64_A32 = 470,
484 ATOMIC_RMW16_U_CMPXCHG_I64_A32_S = 471,
485 ATOMIC_RMW16_U_CMPXCHG_I64_A64 = 472,
486 ATOMIC_RMW16_U_CMPXCHG_I64_A64_S = 473,
487 ATOMIC_RMW16_U_OR_I32_A32 = 474,
488 ATOMIC_RMW16_U_OR_I32_A32_S = 475,
489 ATOMIC_RMW16_U_OR_I32_A64 = 476,
490 ATOMIC_RMW16_U_OR_I32_A64_S = 477,
491 ATOMIC_RMW16_U_OR_I64_A32 = 478,
492 ATOMIC_RMW16_U_OR_I64_A32_S = 479,
493 ATOMIC_RMW16_U_OR_I64_A64 = 480,
494 ATOMIC_RMW16_U_OR_I64_A64_S = 481,
495 ATOMIC_RMW16_U_SUB_I32_A32 = 482,
496 ATOMIC_RMW16_U_SUB_I32_A32_S = 483,
497 ATOMIC_RMW16_U_SUB_I32_A64 = 484,
498 ATOMIC_RMW16_U_SUB_I32_A64_S = 485,
499 ATOMIC_RMW16_U_SUB_I64_A32 = 486,
500 ATOMIC_RMW16_U_SUB_I64_A32_S = 487,
501 ATOMIC_RMW16_U_SUB_I64_A64 = 488,
502 ATOMIC_RMW16_U_SUB_I64_A64_S = 489,
503 ATOMIC_RMW16_U_XCHG_I32_A32 = 490,
504 ATOMIC_RMW16_U_XCHG_I32_A32_S = 491,
505 ATOMIC_RMW16_U_XCHG_I32_A64 = 492,
506 ATOMIC_RMW16_U_XCHG_I32_A64_S = 493,
507 ATOMIC_RMW16_U_XCHG_I64_A32 = 494,
508 ATOMIC_RMW16_U_XCHG_I64_A32_S = 495,
509 ATOMIC_RMW16_U_XCHG_I64_A64 = 496,
510 ATOMIC_RMW16_U_XCHG_I64_A64_S = 497,
511 ATOMIC_RMW16_U_XOR_I32_A32 = 498,
512 ATOMIC_RMW16_U_XOR_I32_A32_S = 499,
513 ATOMIC_RMW16_U_XOR_I32_A64 = 500,
514 ATOMIC_RMW16_U_XOR_I32_A64_S = 501,
515 ATOMIC_RMW16_U_XOR_I64_A32 = 502,
516 ATOMIC_RMW16_U_XOR_I64_A32_S = 503,
517 ATOMIC_RMW16_U_XOR_I64_A64 = 504,
518 ATOMIC_RMW16_U_XOR_I64_A64_S = 505,
519 ATOMIC_RMW32_U_ADD_I64_A32 = 506,
520 ATOMIC_RMW32_U_ADD_I64_A32_S = 507,
521 ATOMIC_RMW32_U_ADD_I64_A64 = 508,
522 ATOMIC_RMW32_U_ADD_I64_A64_S = 509,
523 ATOMIC_RMW32_U_AND_I64_A32 = 510,
524 ATOMIC_RMW32_U_AND_I64_A32_S = 511,
525 ATOMIC_RMW32_U_AND_I64_A64 = 512,
526 ATOMIC_RMW32_U_AND_I64_A64_S = 513,
527 ATOMIC_RMW32_U_CMPXCHG_I64_A32 = 514,
528 ATOMIC_RMW32_U_CMPXCHG_I64_A32_S = 515,
529 ATOMIC_RMW32_U_CMPXCHG_I64_A64 = 516,
530 ATOMIC_RMW32_U_CMPXCHG_I64_A64_S = 517,
531 ATOMIC_RMW32_U_OR_I64_A32 = 518,
532 ATOMIC_RMW32_U_OR_I64_A32_S = 519,
533 ATOMIC_RMW32_U_OR_I64_A64 = 520,
534 ATOMIC_RMW32_U_OR_I64_A64_S = 521,
535 ATOMIC_RMW32_U_SUB_I64_A32 = 522,
536 ATOMIC_RMW32_U_SUB_I64_A32_S = 523,
537 ATOMIC_RMW32_U_SUB_I64_A64 = 524,
538 ATOMIC_RMW32_U_SUB_I64_A64_S = 525,
539 ATOMIC_RMW32_U_XCHG_I64_A32 = 526,
540 ATOMIC_RMW32_U_XCHG_I64_A32_S = 527,
541 ATOMIC_RMW32_U_XCHG_I64_A64 = 528,
542 ATOMIC_RMW32_U_XCHG_I64_A64_S = 529,
543 ATOMIC_RMW32_U_XOR_I64_A32 = 530,
544 ATOMIC_RMW32_U_XOR_I64_A32_S = 531,
545 ATOMIC_RMW32_U_XOR_I64_A64 = 532,
546 ATOMIC_RMW32_U_XOR_I64_A64_S = 533,
547 ATOMIC_RMW8_U_ADD_I32_A32 = 534,
548 ATOMIC_RMW8_U_ADD_I32_A32_S = 535,
549 ATOMIC_RMW8_U_ADD_I32_A64 = 536,
550 ATOMIC_RMW8_U_ADD_I32_A64_S = 537,
551 ATOMIC_RMW8_U_ADD_I64_A32 = 538,
552 ATOMIC_RMW8_U_ADD_I64_A32_S = 539,
553 ATOMIC_RMW8_U_ADD_I64_A64 = 540,
554 ATOMIC_RMW8_U_ADD_I64_A64_S = 541,
555 ATOMIC_RMW8_U_AND_I32_A32 = 542,
556 ATOMIC_RMW8_U_AND_I32_A32_S = 543,
557 ATOMIC_RMW8_U_AND_I32_A64 = 544,
558 ATOMIC_RMW8_U_AND_I32_A64_S = 545,
559 ATOMIC_RMW8_U_AND_I64_A32 = 546,
560 ATOMIC_RMW8_U_AND_I64_A32_S = 547,
561 ATOMIC_RMW8_U_AND_I64_A64 = 548,
562 ATOMIC_RMW8_U_AND_I64_A64_S = 549,
563 ATOMIC_RMW8_U_CMPXCHG_I32_A32 = 550,
564 ATOMIC_RMW8_U_CMPXCHG_I32_A32_S = 551,
565 ATOMIC_RMW8_U_CMPXCHG_I32_A64 = 552,
566 ATOMIC_RMW8_U_CMPXCHG_I32_A64_S = 553,
567 ATOMIC_RMW8_U_CMPXCHG_I64_A32 = 554,
568 ATOMIC_RMW8_U_CMPXCHG_I64_A32_S = 555,
569 ATOMIC_RMW8_U_CMPXCHG_I64_A64 = 556,
570 ATOMIC_RMW8_U_CMPXCHG_I64_A64_S = 557,
571 ATOMIC_RMW8_U_OR_I32_A32 = 558,
572 ATOMIC_RMW8_U_OR_I32_A32_S = 559,
573 ATOMIC_RMW8_U_OR_I32_A64 = 560,
574 ATOMIC_RMW8_U_OR_I32_A64_S = 561,
575 ATOMIC_RMW8_U_OR_I64_A32 = 562,
576 ATOMIC_RMW8_U_OR_I64_A32_S = 563,
577 ATOMIC_RMW8_U_OR_I64_A64 = 564,
578 ATOMIC_RMW8_U_OR_I64_A64_S = 565,
579 ATOMIC_RMW8_U_SUB_I32_A32 = 566,
580 ATOMIC_RMW8_U_SUB_I32_A32_S = 567,
581 ATOMIC_RMW8_U_SUB_I32_A64 = 568,
582 ATOMIC_RMW8_U_SUB_I32_A64_S = 569,
583 ATOMIC_RMW8_U_SUB_I64_A32 = 570,
584 ATOMIC_RMW8_U_SUB_I64_A32_S = 571,
585 ATOMIC_RMW8_U_SUB_I64_A64 = 572,
586 ATOMIC_RMW8_U_SUB_I64_A64_S = 573,
587 ATOMIC_RMW8_U_XCHG_I32_A32 = 574,
588 ATOMIC_RMW8_U_XCHG_I32_A32_S = 575,
589 ATOMIC_RMW8_U_XCHG_I32_A64 = 576,
590 ATOMIC_RMW8_U_XCHG_I32_A64_S = 577,
591 ATOMIC_RMW8_U_XCHG_I64_A32 = 578,
592 ATOMIC_RMW8_U_XCHG_I64_A32_S = 579,
593 ATOMIC_RMW8_U_XCHG_I64_A64 = 580,
594 ATOMIC_RMW8_U_XCHG_I64_A64_S = 581,
595 ATOMIC_RMW8_U_XOR_I32_A32 = 582,
596 ATOMIC_RMW8_U_XOR_I32_A32_S = 583,
597 ATOMIC_RMW8_U_XOR_I32_A64 = 584,
598 ATOMIC_RMW8_U_XOR_I32_A64_S = 585,
599 ATOMIC_RMW8_U_XOR_I64_A32 = 586,
600 ATOMIC_RMW8_U_XOR_I64_A32_S = 587,
601 ATOMIC_RMW8_U_XOR_I64_A64 = 588,
602 ATOMIC_RMW8_U_XOR_I64_A64_S = 589,
603 ATOMIC_RMW_ADD_I32_A32 = 590,
604 ATOMIC_RMW_ADD_I32_A32_S = 591,
605 ATOMIC_RMW_ADD_I32_A64 = 592,
606 ATOMIC_RMW_ADD_I32_A64_S = 593,
607 ATOMIC_RMW_ADD_I64_A32 = 594,
608 ATOMIC_RMW_ADD_I64_A32_S = 595,
609 ATOMIC_RMW_ADD_I64_A64 = 596,
610 ATOMIC_RMW_ADD_I64_A64_S = 597,
611 ATOMIC_RMW_AND_I32_A32 = 598,
612 ATOMIC_RMW_AND_I32_A32_S = 599,
613 ATOMIC_RMW_AND_I32_A64 = 600,
614 ATOMIC_RMW_AND_I32_A64_S = 601,
615 ATOMIC_RMW_AND_I64_A32 = 602,
616 ATOMIC_RMW_AND_I64_A32_S = 603,
617 ATOMIC_RMW_AND_I64_A64 = 604,
618 ATOMIC_RMW_AND_I64_A64_S = 605,
619 ATOMIC_RMW_CMPXCHG_I32_A32 = 606,
620 ATOMIC_RMW_CMPXCHG_I32_A32_S = 607,
621 ATOMIC_RMW_CMPXCHG_I32_A64 = 608,
622 ATOMIC_RMW_CMPXCHG_I32_A64_S = 609,
623 ATOMIC_RMW_CMPXCHG_I64_A32 = 610,
624 ATOMIC_RMW_CMPXCHG_I64_A32_S = 611,
625 ATOMIC_RMW_CMPXCHG_I64_A64 = 612,
626 ATOMIC_RMW_CMPXCHG_I64_A64_S = 613,
627 ATOMIC_RMW_OR_I32_A32 = 614,
628 ATOMIC_RMW_OR_I32_A32_S = 615,
629 ATOMIC_RMW_OR_I32_A64 = 616,
630 ATOMIC_RMW_OR_I32_A64_S = 617,
631 ATOMIC_RMW_OR_I64_A32 = 618,
632 ATOMIC_RMW_OR_I64_A32_S = 619,
633 ATOMIC_RMW_OR_I64_A64 = 620,
634 ATOMIC_RMW_OR_I64_A64_S = 621,
635 ATOMIC_RMW_SUB_I32_A32 = 622,
636 ATOMIC_RMW_SUB_I32_A32_S = 623,
637 ATOMIC_RMW_SUB_I32_A64 = 624,
638 ATOMIC_RMW_SUB_I32_A64_S = 625,
639 ATOMIC_RMW_SUB_I64_A32 = 626,
640 ATOMIC_RMW_SUB_I64_A32_S = 627,
641 ATOMIC_RMW_SUB_I64_A64 = 628,
642 ATOMIC_RMW_SUB_I64_A64_S = 629,
643 ATOMIC_RMW_XCHG_I32_A32 = 630,
644 ATOMIC_RMW_XCHG_I32_A32_S = 631,
645 ATOMIC_RMW_XCHG_I32_A64 = 632,
646 ATOMIC_RMW_XCHG_I32_A64_S = 633,
647 ATOMIC_RMW_XCHG_I64_A32 = 634,
648 ATOMIC_RMW_XCHG_I64_A32_S = 635,
649 ATOMIC_RMW_XCHG_I64_A64 = 636,
650 ATOMIC_RMW_XCHG_I64_A64_S = 637,
651 ATOMIC_RMW_XOR_I32_A32 = 638,
652 ATOMIC_RMW_XOR_I32_A32_S = 639,
653 ATOMIC_RMW_XOR_I32_A64 = 640,
654 ATOMIC_RMW_XOR_I32_A64_S = 641,
655 ATOMIC_RMW_XOR_I64_A32 = 642,
656 ATOMIC_RMW_XOR_I64_A32_S = 643,
657 ATOMIC_RMW_XOR_I64_A64 = 644,
658 ATOMIC_RMW_XOR_I64_A64_S = 645,
659 ATOMIC_STORE16_I32_A32 = 646,
660 ATOMIC_STORE16_I32_A32_S = 647,
661 ATOMIC_STORE16_I32_A64 = 648,
662 ATOMIC_STORE16_I32_A64_S = 649,
663 ATOMIC_STORE16_I64_A32 = 650,
664 ATOMIC_STORE16_I64_A32_S = 651,
665 ATOMIC_STORE16_I64_A64 = 652,
666 ATOMIC_STORE16_I64_A64_S = 653,
667 ATOMIC_STORE32_I64_A32 = 654,
668 ATOMIC_STORE32_I64_A32_S = 655,
669 ATOMIC_STORE32_I64_A64 = 656,
670 ATOMIC_STORE32_I64_A64_S = 657,
671 ATOMIC_STORE8_I32_A32 = 658,
672 ATOMIC_STORE8_I32_A32_S = 659,
673 ATOMIC_STORE8_I32_A64 = 660,
674 ATOMIC_STORE8_I32_A64_S = 661,
675 ATOMIC_STORE8_I64_A32 = 662,
676 ATOMIC_STORE8_I64_A32_S = 663,
677 ATOMIC_STORE8_I64_A64 = 664,
678 ATOMIC_STORE8_I64_A64_S = 665,
679 ATOMIC_STORE_I32_A32 = 666,
680 ATOMIC_STORE_I32_A32_S = 667,
681 ATOMIC_STORE_I32_A64 = 668,
682 ATOMIC_STORE_I32_A64_S = 669,
683 ATOMIC_STORE_I64_A32 = 670,
684 ATOMIC_STORE_I64_A32_S = 671,
685 ATOMIC_STORE_I64_A64 = 672,
686 ATOMIC_STORE_I64_A64_S = 673,
687 AVGR_U_I16x8 = 674,
688 AVGR_U_I16x8_S = 675,
689 AVGR_U_I8x16 = 676,
690 AVGR_U_I8x16_S = 677,
691 BITMASK_I16x8 = 678,
692 BITMASK_I16x8_S = 679,
693 BITMASK_I32x4 = 680,
694 BITMASK_I32x4_S = 681,
695 BITMASK_I64x2 = 682,
696 BITMASK_I64x2_S = 683,
697 BITMASK_I8x16 = 684,
698 BITMASK_I8x16_S = 685,
699 BITSELECT = 686,
700 BITSELECT_S = 687,
701 BLOCK = 688,
702 BLOCK_S = 689,
703 BR = 690,
704 BR_IF = 691,
705 BR_IF_S = 692,
706 BR_S = 693,
707 BR_TABLE_I32 = 694,
708 BR_TABLE_I32_S = 695,
709 BR_TABLE_I64 = 696,
710 BR_TABLE_I64_S = 697,
711 BR_UNLESS = 698,
712 BR_UNLESS_S = 699,
713 CALL = 700,
714 CALL_INDIRECT = 701,
715 CALL_INDIRECT_S = 702,
716 CALL_S = 703,
717 CATCH = 704,
718 CATCH_ALL = 705,
719 CATCH_ALL_LEGACY = 706,
720 CATCH_ALL_LEGACY_S = 707,
721 CATCH_ALL_REF = 708,
722 CATCH_ALL_REF_S = 709,
723 CATCH_ALL_S = 710,
724 CATCH_LEGACY = 711,
725 CATCH_LEGACY_S = 712,
726 CATCH_REF = 713,
727 CATCH_REF_S = 714,
728 CATCH_S = 715,
729 CEIL_F16x8 = 716,
730 CEIL_F16x8_S = 717,
731 CEIL_F32 = 718,
732 CEIL_F32_S = 719,
733 CEIL_F32x4 = 720,
734 CEIL_F32x4_S = 721,
735 CEIL_F64 = 722,
736 CEIL_F64_S = 723,
737 CEIL_F64x2 = 724,
738 CEIL_F64x2_S = 725,
739 CLZ_I32 = 726,
740 CLZ_I32_S = 727,
741 CLZ_I64 = 728,
742 CLZ_I64_S = 729,
743 CONST_F32 = 730,
744 CONST_F32_S = 731,
745 CONST_F64 = 732,
746 CONST_F64_S = 733,
747 CONST_I32 = 734,
748 CONST_I32_S = 735,
749 CONST_I64 = 736,
750 CONST_I64_S = 737,
751 CONST_V128_F32x4 = 738,
752 CONST_V128_F32x4_S = 739,
753 CONST_V128_F64x2 = 740,
754 CONST_V128_F64x2_S = 741,
755 CONST_V128_I16x8 = 742,
756 CONST_V128_I16x8_S = 743,
757 CONST_V128_I32x4 = 744,
758 CONST_V128_I32x4_S = 745,
759 CONST_V128_I64x2 = 746,
760 CONST_V128_I64x2_S = 747,
761 CONST_V128_I8x16 = 748,
762 CONST_V128_I8x16_S = 749,
763 COPYSIGN_F32 = 750,
764 COPYSIGN_F32_S = 751,
765 COPYSIGN_F64 = 752,
766 COPYSIGN_F64_S = 753,
767 COPY_EXNREF = 754,
768 COPY_EXNREF_S = 755,
769 COPY_EXTERNREF = 756,
770 COPY_EXTERNREF_S = 757,
771 COPY_F32 = 758,
772 COPY_F32_S = 759,
773 COPY_F64 = 760,
774 COPY_F64_S = 761,
775 COPY_FUNCREF = 762,
776 COPY_FUNCREF_S = 763,
777 COPY_I32 = 764,
778 COPY_I32_S = 765,
779 COPY_I64 = 766,
780 COPY_I64_S = 767,
781 COPY_V128 = 768,
782 COPY_V128_S = 769,
783 CTZ_I32 = 770,
784 CTZ_I32_S = 771,
785 CTZ_I64 = 772,
786 CTZ_I64_S = 773,
787 DATA_DROP = 774,
788 DATA_DROP_S = 775,
789 DEBUG_UNREACHABLE = 776,
790 DEBUG_UNREACHABLE_S = 777,
791 DELEGATE = 778,
792 DELEGATE_S = 779,
793 DIV_F16x8 = 780,
794 DIV_F16x8_S = 781,
795 DIV_F32 = 782,
796 DIV_F32_S = 783,
797 DIV_F32x4 = 784,
798 DIV_F32x4_S = 785,
799 DIV_F64 = 786,
800 DIV_F64_S = 787,
801 DIV_F64x2 = 788,
802 DIV_F64x2_S = 789,
803 DIV_S_I32 = 790,
804 DIV_S_I32_S = 791,
805 DIV_S_I64 = 792,
806 DIV_S_I64_S = 793,
807 DIV_U_I32 = 794,
808 DIV_U_I32_S = 795,
809 DIV_U_I64 = 796,
810 DIV_U_I64_S = 797,
811 DOT = 798,
812 DOT_S = 799,
813 DROP_EXNREF = 800,
814 DROP_EXNREF_S = 801,
815 DROP_EXTERNREF = 802,
816 DROP_EXTERNREF_S = 803,
817 DROP_F32 = 804,
818 DROP_F32_S = 805,
819 DROP_F64 = 806,
820 DROP_F64_S = 807,
821 DROP_FUNCREF = 808,
822 DROP_FUNCREF_S = 809,
823 DROP_I32 = 810,
824 DROP_I32_S = 811,
825 DROP_I64 = 812,
826 DROP_I64_S = 813,
827 DROP_V128 = 814,
828 DROP_V128_S = 815,
829 ELSE = 816,
830 ELSE_S = 817,
831 END = 818,
832 END_BLOCK = 819,
833 END_BLOCK_S = 820,
834 END_FUNCTION = 821,
835 END_FUNCTION_S = 822,
836 END_IF = 823,
837 END_IF_S = 824,
838 END_LOOP = 825,
839 END_LOOP_S = 826,
840 END_S = 827,
841 END_TRY = 828,
842 END_TRY_S = 829,
843 END_TRY_TABLE = 830,
844 END_TRY_TABLE_S = 831,
845 EQZ_I32 = 832,
846 EQZ_I32_S = 833,
847 EQZ_I64 = 834,
848 EQZ_I64_S = 835,
849 EQ_F16x8 = 836,
850 EQ_F16x8_S = 837,
851 EQ_F32 = 838,
852 EQ_F32_S = 839,
853 EQ_F32x4 = 840,
854 EQ_F32x4_S = 841,
855 EQ_F64 = 842,
856 EQ_F64_S = 843,
857 EQ_F64x2 = 844,
858 EQ_F64x2_S = 845,
859 EQ_I16x8 = 846,
860 EQ_I16x8_S = 847,
861 EQ_I32 = 848,
862 EQ_I32_S = 849,
863 EQ_I32x4 = 850,
864 EQ_I32x4_S = 851,
865 EQ_I64 = 852,
866 EQ_I64_S = 853,
867 EQ_I64x2 = 854,
868 EQ_I64x2_S = 855,
869 EQ_I8x16 = 856,
870 EQ_I8x16_S = 857,
871 EXTMUL_HIGH_S_I16x8 = 858,
872 EXTMUL_HIGH_S_I16x8_S = 859,
873 EXTMUL_HIGH_S_I32x4 = 860,
874 EXTMUL_HIGH_S_I32x4_S = 861,
875 EXTMUL_HIGH_S_I64x2 = 862,
876 EXTMUL_HIGH_S_I64x2_S = 863,
877 EXTMUL_HIGH_U_I16x8 = 864,
878 EXTMUL_HIGH_U_I16x8_S = 865,
879 EXTMUL_HIGH_U_I32x4 = 866,
880 EXTMUL_HIGH_U_I32x4_S = 867,
881 EXTMUL_HIGH_U_I64x2 = 868,
882 EXTMUL_HIGH_U_I64x2_S = 869,
883 EXTMUL_LOW_S_I16x8 = 870,
884 EXTMUL_LOW_S_I16x8_S = 871,
885 EXTMUL_LOW_S_I32x4 = 872,
886 EXTMUL_LOW_S_I32x4_S = 873,
887 EXTMUL_LOW_S_I64x2 = 874,
888 EXTMUL_LOW_S_I64x2_S = 875,
889 EXTMUL_LOW_U_I16x8 = 876,
890 EXTMUL_LOW_U_I16x8_S = 877,
891 EXTMUL_LOW_U_I32x4 = 878,
892 EXTMUL_LOW_U_I32x4_S = 879,
893 EXTMUL_LOW_U_I64x2 = 880,
894 EXTMUL_LOW_U_I64x2_S = 881,
895 EXTRACT_LANE_F16x8 = 882,
896 EXTRACT_LANE_F16x8_S = 883,
897 EXTRACT_LANE_F32x4 = 884,
898 EXTRACT_LANE_F32x4_S = 885,
899 EXTRACT_LANE_F64x2 = 886,
900 EXTRACT_LANE_F64x2_S = 887,
901 EXTRACT_LANE_I16x8_s = 888,
902 EXTRACT_LANE_I16x8_s_S = 889,
903 EXTRACT_LANE_I16x8_u = 890,
904 EXTRACT_LANE_I16x8_u_S = 891,
905 EXTRACT_LANE_I32x4 = 892,
906 EXTRACT_LANE_I32x4_S = 893,
907 EXTRACT_LANE_I64x2 = 894,
908 EXTRACT_LANE_I64x2_S = 895,
909 EXTRACT_LANE_I8x16_s = 896,
910 EXTRACT_LANE_I8x16_s_S = 897,
911 EXTRACT_LANE_I8x16_u = 898,
912 EXTRACT_LANE_I8x16_u_S = 899,
913 F32_CONVERT_S_I32 = 900,
914 F32_CONVERT_S_I32_S = 901,
915 F32_CONVERT_S_I64 = 902,
916 F32_CONVERT_S_I64_S = 903,
917 F32_CONVERT_U_I32 = 904,
918 F32_CONVERT_U_I32_S = 905,
919 F32_CONVERT_U_I64 = 906,
920 F32_CONVERT_U_I64_S = 907,
921 F32_DEMOTE_F64 = 908,
922 F32_DEMOTE_F64_S = 909,
923 F32_REINTERPRET_I32 = 910,
924 F32_REINTERPRET_I32_S = 911,
925 F64_CONVERT_S_I32 = 912,
926 F64_CONVERT_S_I32_S = 913,
927 F64_CONVERT_S_I64 = 914,
928 F64_CONVERT_S_I64_S = 915,
929 F64_CONVERT_U_I32 = 916,
930 F64_CONVERT_U_I32_S = 917,
931 F64_CONVERT_U_I64 = 918,
932 F64_CONVERT_U_I64_S = 919,
933 F64_PROMOTE_F32 = 920,
934 F64_PROMOTE_F32_S = 921,
935 F64_REINTERPRET_I64 = 922,
936 F64_REINTERPRET_I64_S = 923,
937 FALLTHROUGH_RETURN = 924,
938 FALLTHROUGH_RETURN_S = 925,
939 FLOOR_F16x8 = 926,
940 FLOOR_F16x8_S = 927,
941 FLOOR_F32 = 928,
942 FLOOR_F32_S = 929,
943 FLOOR_F32x4 = 930,
944 FLOOR_F32x4_S = 931,
945 FLOOR_F64 = 932,
946 FLOOR_F64_S = 933,
947 FLOOR_F64x2 = 934,
948 FLOOR_F64x2_S = 935,
949 FP_TO_SINT_I32_F32 = 936,
950 FP_TO_SINT_I32_F32_S = 937,
951 FP_TO_SINT_I32_F64 = 938,
952 FP_TO_SINT_I32_F64_S = 939,
953 FP_TO_SINT_I64_F32 = 940,
954 FP_TO_SINT_I64_F32_S = 941,
955 FP_TO_SINT_I64_F64 = 942,
956 FP_TO_SINT_I64_F64_S = 943,
957 FP_TO_UINT_I32_F32 = 944,
958 FP_TO_UINT_I32_F32_S = 945,
959 FP_TO_UINT_I32_F64 = 946,
960 FP_TO_UINT_I32_F64_S = 947,
961 FP_TO_UINT_I64_F32 = 948,
962 FP_TO_UINT_I64_F32_S = 949,
963 FP_TO_UINT_I64_F64 = 950,
964 FP_TO_UINT_I64_F64_S = 951,
965 GE_F16x8 = 952,
966 GE_F16x8_S = 953,
967 GE_F32 = 954,
968 GE_F32_S = 955,
969 GE_F32x4 = 956,
970 GE_F32x4_S = 957,
971 GE_F64 = 958,
972 GE_F64_S = 959,
973 GE_F64x2 = 960,
974 GE_F64x2_S = 961,
975 GE_S_I16x8 = 962,
976 GE_S_I16x8_S = 963,
977 GE_S_I32 = 964,
978 GE_S_I32_S = 965,
979 GE_S_I32x4 = 966,
980 GE_S_I32x4_S = 967,
981 GE_S_I64 = 968,
982 GE_S_I64_S = 969,
983 GE_S_I64x2 = 970,
984 GE_S_I64x2_S = 971,
985 GE_S_I8x16 = 972,
986 GE_S_I8x16_S = 973,
987 GE_U_I16x8 = 974,
988 GE_U_I16x8_S = 975,
989 GE_U_I32 = 976,
990 GE_U_I32_S = 977,
991 GE_U_I32x4 = 978,
992 GE_U_I32x4_S = 979,
993 GE_U_I64 = 980,
994 GE_U_I64_S = 981,
995 GE_U_I8x16 = 982,
996 GE_U_I8x16_S = 983,
997 GLOBAL_GET_EXNREF = 984,
998 GLOBAL_GET_EXNREF_S = 985,
999 GLOBAL_GET_EXTERNREF = 986,
1000 GLOBAL_GET_EXTERNREF_S = 987,
1001 GLOBAL_GET_F32 = 988,
1002 GLOBAL_GET_F32_S = 989,
1003 GLOBAL_GET_F64 = 990,
1004 GLOBAL_GET_F64_S = 991,
1005 GLOBAL_GET_FUNCREF = 992,
1006 GLOBAL_GET_FUNCREF_S = 993,
1007 GLOBAL_GET_I32 = 994,
1008 GLOBAL_GET_I32_S = 995,
1009 GLOBAL_GET_I64 = 996,
1010 GLOBAL_GET_I64_S = 997,
1011 GLOBAL_GET_V128 = 998,
1012 GLOBAL_GET_V128_S = 999,
1013 GLOBAL_SET_EXNREF = 1000,
1014 GLOBAL_SET_EXNREF_S = 1001,
1015 GLOBAL_SET_EXTERNREF = 1002,
1016 GLOBAL_SET_EXTERNREF_S = 1003,
1017 GLOBAL_SET_F32 = 1004,
1018 GLOBAL_SET_F32_S = 1005,
1019 GLOBAL_SET_F64 = 1006,
1020 GLOBAL_SET_F64_S = 1007,
1021 GLOBAL_SET_FUNCREF = 1008,
1022 GLOBAL_SET_FUNCREF_S = 1009,
1023 GLOBAL_SET_I32 = 1010,
1024 GLOBAL_SET_I32_S = 1011,
1025 GLOBAL_SET_I64 = 1012,
1026 GLOBAL_SET_I64_S = 1013,
1027 GLOBAL_SET_V128 = 1014,
1028 GLOBAL_SET_V128_S = 1015,
1029 GT_F16x8 = 1016,
1030 GT_F16x8_S = 1017,
1031 GT_F32 = 1018,
1032 GT_F32_S = 1019,
1033 GT_F32x4 = 1020,
1034 GT_F32x4_S = 1021,
1035 GT_F64 = 1022,
1036 GT_F64_S = 1023,
1037 GT_F64x2 = 1024,
1038 GT_F64x2_S = 1025,
1039 GT_S_I16x8 = 1026,
1040 GT_S_I16x8_S = 1027,
1041 GT_S_I32 = 1028,
1042 GT_S_I32_S = 1029,
1043 GT_S_I32x4 = 1030,
1044 GT_S_I32x4_S = 1031,
1045 GT_S_I64 = 1032,
1046 GT_S_I64_S = 1033,
1047 GT_S_I64x2 = 1034,
1048 GT_S_I64x2_S = 1035,
1049 GT_S_I8x16 = 1036,
1050 GT_S_I8x16_S = 1037,
1051 GT_U_I16x8 = 1038,
1052 GT_U_I16x8_S = 1039,
1053 GT_U_I32 = 1040,
1054 GT_U_I32_S = 1041,
1055 GT_U_I32x4 = 1042,
1056 GT_U_I32x4_S = 1043,
1057 GT_U_I64 = 1044,
1058 GT_U_I64_S = 1045,
1059 GT_U_I8x16 = 1046,
1060 GT_U_I8x16_S = 1047,
1061 I32_EXTEND16_S_I32 = 1048,
1062 I32_EXTEND16_S_I32_S = 1049,
1063 I32_EXTEND8_S_I32 = 1050,
1064 I32_EXTEND8_S_I32_S = 1051,
1065 I32_REINTERPRET_F32 = 1052,
1066 I32_REINTERPRET_F32_S = 1053,
1067 I32_TRUNC_S_F32 = 1054,
1068 I32_TRUNC_S_F32_S = 1055,
1069 I32_TRUNC_S_F64 = 1056,
1070 I32_TRUNC_S_F64_S = 1057,
1071 I32_TRUNC_S_SAT_F32 = 1058,
1072 I32_TRUNC_S_SAT_F32_S = 1059,
1073 I32_TRUNC_S_SAT_F64 = 1060,
1074 I32_TRUNC_S_SAT_F64_S = 1061,
1075 I32_TRUNC_U_F32 = 1062,
1076 I32_TRUNC_U_F32_S = 1063,
1077 I32_TRUNC_U_F64 = 1064,
1078 I32_TRUNC_U_F64_S = 1065,
1079 I32_TRUNC_U_SAT_F32 = 1066,
1080 I32_TRUNC_U_SAT_F32_S = 1067,
1081 I32_TRUNC_U_SAT_F64 = 1068,
1082 I32_TRUNC_U_SAT_F64_S = 1069,
1083 I32_WRAP_I64 = 1070,
1084 I32_WRAP_I64_S = 1071,
1085 I64_ADD128 = 1072,
1086 I64_ADD128_S = 1073,
1087 I64_EXTEND16_S_I64 = 1074,
1088 I64_EXTEND16_S_I64_S = 1075,
1089 I64_EXTEND32_S_I64 = 1076,
1090 I64_EXTEND32_S_I64_S = 1077,
1091 I64_EXTEND8_S_I64 = 1078,
1092 I64_EXTEND8_S_I64_S = 1079,
1093 I64_EXTEND_S_I32 = 1080,
1094 I64_EXTEND_S_I32_S = 1081,
1095 I64_EXTEND_U_I32 = 1082,
1096 I64_EXTEND_U_I32_S = 1083,
1097 I64_MUL_WIDE_S = 1084,
1098 I64_MUL_WIDE_S_S = 1085,
1099 I64_MUL_WIDE_U = 1086,
1100 I64_MUL_WIDE_U_S = 1087,
1101 I64_REINTERPRET_F64 = 1088,
1102 I64_REINTERPRET_F64_S = 1089,
1103 I64_SUB128 = 1090,
1104 I64_SUB128_S = 1091,
1105 I64_TRUNC_S_F32 = 1092,
1106 I64_TRUNC_S_F32_S = 1093,
1107 I64_TRUNC_S_F64 = 1094,
1108 I64_TRUNC_S_F64_S = 1095,
1109 I64_TRUNC_S_SAT_F32 = 1096,
1110 I64_TRUNC_S_SAT_F32_S = 1097,
1111 I64_TRUNC_S_SAT_F64 = 1098,
1112 I64_TRUNC_S_SAT_F64_S = 1099,
1113 I64_TRUNC_U_F32 = 1100,
1114 I64_TRUNC_U_F32_S = 1101,
1115 I64_TRUNC_U_F64 = 1102,
1116 I64_TRUNC_U_F64_S = 1103,
1117 I64_TRUNC_U_SAT_F32 = 1104,
1118 I64_TRUNC_U_SAT_F32_S = 1105,
1119 I64_TRUNC_U_SAT_F64 = 1106,
1120 I64_TRUNC_U_SAT_F64_S = 1107,
1121 IF = 1108,
1122 IF_S = 1109,
1123 LANESELECT_I16x8 = 1110,
1124 LANESELECT_I16x8_S = 1111,
1125 LANESELECT_I32x4 = 1112,
1126 LANESELECT_I32x4_S = 1113,
1127 LANESELECT_I64x2 = 1114,
1128 LANESELECT_I64x2_S = 1115,
1129 LANESELECT_I8x16 = 1116,
1130 LANESELECT_I8x16_S = 1117,
1131 LE_F16x8 = 1118,
1132 LE_F16x8_S = 1119,
1133 LE_F32 = 1120,
1134 LE_F32_S = 1121,
1135 LE_F32x4 = 1122,
1136 LE_F32x4_S = 1123,
1137 LE_F64 = 1124,
1138 LE_F64_S = 1125,
1139 LE_F64x2 = 1126,
1140 LE_F64x2_S = 1127,
1141 LE_S_I16x8 = 1128,
1142 LE_S_I16x8_S = 1129,
1143 LE_S_I32 = 1130,
1144 LE_S_I32_S = 1131,
1145 LE_S_I32x4 = 1132,
1146 LE_S_I32x4_S = 1133,
1147 LE_S_I64 = 1134,
1148 LE_S_I64_S = 1135,
1149 LE_S_I64x2 = 1136,
1150 LE_S_I64x2_S = 1137,
1151 LE_S_I8x16 = 1138,
1152 LE_S_I8x16_S = 1139,
1153 LE_U_I16x8 = 1140,
1154 LE_U_I16x8_S = 1141,
1155 LE_U_I32 = 1142,
1156 LE_U_I32_S = 1143,
1157 LE_U_I32x4 = 1144,
1158 LE_U_I32x4_S = 1145,
1159 LE_U_I64 = 1146,
1160 LE_U_I64_S = 1147,
1161 LE_U_I8x16 = 1148,
1162 LE_U_I8x16_S = 1149,
1163 LOAD16_SPLAT_A32 = 1150,
1164 LOAD16_SPLAT_A32_S = 1151,
1165 LOAD16_SPLAT_A64 = 1152,
1166 LOAD16_SPLAT_A64_S = 1153,
1167 LOAD16_S_I32_A32 = 1154,
1168 LOAD16_S_I32_A32_S = 1155,
1169 LOAD16_S_I32_A64 = 1156,
1170 LOAD16_S_I32_A64_S = 1157,
1171 LOAD16_S_I64_A32 = 1158,
1172 LOAD16_S_I64_A32_S = 1159,
1173 LOAD16_S_I64_A64 = 1160,
1174 LOAD16_S_I64_A64_S = 1161,
1175 LOAD16_U_I32_A32 = 1162,
1176 LOAD16_U_I32_A32_S = 1163,
1177 LOAD16_U_I32_A64 = 1164,
1178 LOAD16_U_I32_A64_S = 1165,
1179 LOAD16_U_I64_A32 = 1166,
1180 LOAD16_U_I64_A32_S = 1167,
1181 LOAD16_U_I64_A64 = 1168,
1182 LOAD16_U_I64_A64_S = 1169,
1183 LOAD32_SPLAT_A32 = 1170,
1184 LOAD32_SPLAT_A32_S = 1171,
1185 LOAD32_SPLAT_A64 = 1172,
1186 LOAD32_SPLAT_A64_S = 1173,
1187 LOAD32_S_I64_A32 = 1174,
1188 LOAD32_S_I64_A32_S = 1175,
1189 LOAD32_S_I64_A64 = 1176,
1190 LOAD32_S_I64_A64_S = 1177,
1191 LOAD32_U_I64_A32 = 1178,
1192 LOAD32_U_I64_A32_S = 1179,
1193 LOAD32_U_I64_A64 = 1180,
1194 LOAD32_U_I64_A64_S = 1181,
1195 LOAD64_SPLAT_A32 = 1182,
1196 LOAD64_SPLAT_A32_S = 1183,
1197 LOAD64_SPLAT_A64 = 1184,
1198 LOAD64_SPLAT_A64_S = 1185,
1199 LOAD8_SPLAT_A32 = 1186,
1200 LOAD8_SPLAT_A32_S = 1187,
1201 LOAD8_SPLAT_A64 = 1188,
1202 LOAD8_SPLAT_A64_S = 1189,
1203 LOAD8_S_I32_A32 = 1190,
1204 LOAD8_S_I32_A32_S = 1191,
1205 LOAD8_S_I32_A64 = 1192,
1206 LOAD8_S_I32_A64_S = 1193,
1207 LOAD8_S_I64_A32 = 1194,
1208 LOAD8_S_I64_A32_S = 1195,
1209 LOAD8_S_I64_A64 = 1196,
1210 LOAD8_S_I64_A64_S = 1197,
1211 LOAD8_U_I32_A32 = 1198,
1212 LOAD8_U_I32_A32_S = 1199,
1213 LOAD8_U_I32_A64 = 1200,
1214 LOAD8_U_I32_A64_S = 1201,
1215 LOAD8_U_I64_A32 = 1202,
1216 LOAD8_U_I64_A32_S = 1203,
1217 LOAD8_U_I64_A64 = 1204,
1218 LOAD8_U_I64_A64_S = 1205,
1219 LOAD_EXTEND_S_I16x8_A32 = 1206,
1220 LOAD_EXTEND_S_I16x8_A32_S = 1207,
1221 LOAD_EXTEND_S_I16x8_A64 = 1208,
1222 LOAD_EXTEND_S_I16x8_A64_S = 1209,
1223 LOAD_EXTEND_S_I32x4_A32 = 1210,
1224 LOAD_EXTEND_S_I32x4_A32_S = 1211,
1225 LOAD_EXTEND_S_I32x4_A64 = 1212,
1226 LOAD_EXTEND_S_I32x4_A64_S = 1213,
1227 LOAD_EXTEND_S_I64x2_A32 = 1214,
1228 LOAD_EXTEND_S_I64x2_A32_S = 1215,
1229 LOAD_EXTEND_S_I64x2_A64 = 1216,
1230 LOAD_EXTEND_S_I64x2_A64_S = 1217,
1231 LOAD_EXTEND_U_I16x8_A32 = 1218,
1232 LOAD_EXTEND_U_I16x8_A32_S = 1219,
1233 LOAD_EXTEND_U_I16x8_A64 = 1220,
1234 LOAD_EXTEND_U_I16x8_A64_S = 1221,
1235 LOAD_EXTEND_U_I32x4_A32 = 1222,
1236 LOAD_EXTEND_U_I32x4_A32_S = 1223,
1237 LOAD_EXTEND_U_I32x4_A64 = 1224,
1238 LOAD_EXTEND_U_I32x4_A64_S = 1225,
1239 LOAD_EXTEND_U_I64x2_A32 = 1226,
1240 LOAD_EXTEND_U_I64x2_A32_S = 1227,
1241 LOAD_EXTEND_U_I64x2_A64 = 1228,
1242 LOAD_EXTEND_U_I64x2_A64_S = 1229,
1243 LOAD_F16_F32_A32 = 1230,
1244 LOAD_F16_F32_A32_S = 1231,
1245 LOAD_F16_F32_A64 = 1232,
1246 LOAD_F16_F32_A64_S = 1233,
1247 LOAD_F32_A32 = 1234,
1248 LOAD_F32_A32_S = 1235,
1249 LOAD_F32_A64 = 1236,
1250 LOAD_F32_A64_S = 1237,
1251 LOAD_F64_A32 = 1238,
1252 LOAD_F64_A32_S = 1239,
1253 LOAD_F64_A64 = 1240,
1254 LOAD_F64_A64_S = 1241,
1255 LOAD_I32_A32 = 1242,
1256 LOAD_I32_A32_S = 1243,
1257 LOAD_I32_A64 = 1244,
1258 LOAD_I32_A64_S = 1245,
1259 LOAD_I64_A32 = 1246,
1260 LOAD_I64_A32_S = 1247,
1261 LOAD_I64_A64 = 1248,
1262 LOAD_I64_A64_S = 1249,
1263 LOAD_LANE_16_A32 = 1250,
1264 LOAD_LANE_16_A32_S = 1251,
1265 LOAD_LANE_16_A64 = 1252,
1266 LOAD_LANE_16_A64_S = 1253,
1267 LOAD_LANE_32_A32 = 1254,
1268 LOAD_LANE_32_A32_S = 1255,
1269 LOAD_LANE_32_A64 = 1256,
1270 LOAD_LANE_32_A64_S = 1257,
1271 LOAD_LANE_64_A32 = 1258,
1272 LOAD_LANE_64_A32_S = 1259,
1273 LOAD_LANE_64_A64 = 1260,
1274 LOAD_LANE_64_A64_S = 1261,
1275 LOAD_LANE_8_A32 = 1262,
1276 LOAD_LANE_8_A32_S = 1263,
1277 LOAD_LANE_8_A64 = 1264,
1278 LOAD_LANE_8_A64_S = 1265,
1279 LOAD_V128_A32 = 1266,
1280 LOAD_V128_A32_S = 1267,
1281 LOAD_V128_A64 = 1268,
1282 LOAD_V128_A64_S = 1269,
1283 LOAD_ZERO_32_A32 = 1270,
1284 LOAD_ZERO_32_A32_S = 1271,
1285 LOAD_ZERO_32_A64 = 1272,
1286 LOAD_ZERO_32_A64_S = 1273,
1287 LOAD_ZERO_64_A32 = 1274,
1288 LOAD_ZERO_64_A32_S = 1275,
1289 LOAD_ZERO_64_A64 = 1276,
1290 LOAD_ZERO_64_A64_S = 1277,
1291 LOCAL_GET_EXNREF = 1278,
1292 LOCAL_GET_EXNREF_S = 1279,
1293 LOCAL_GET_EXTERNREF = 1280,
1294 LOCAL_GET_EXTERNREF_S = 1281,
1295 LOCAL_GET_F32 = 1282,
1296 LOCAL_GET_F32_S = 1283,
1297 LOCAL_GET_F64 = 1284,
1298 LOCAL_GET_F64_S = 1285,
1299 LOCAL_GET_FUNCREF = 1286,
1300 LOCAL_GET_FUNCREF_S = 1287,
1301 LOCAL_GET_I32 = 1288,
1302 LOCAL_GET_I32_S = 1289,
1303 LOCAL_GET_I64 = 1290,
1304 LOCAL_GET_I64_S = 1291,
1305 LOCAL_GET_V128 = 1292,
1306 LOCAL_GET_V128_S = 1293,
1307 LOCAL_SET_EXNREF = 1294,
1308 LOCAL_SET_EXNREF_S = 1295,
1309 LOCAL_SET_EXTERNREF = 1296,
1310 LOCAL_SET_EXTERNREF_S = 1297,
1311 LOCAL_SET_F32 = 1298,
1312 LOCAL_SET_F32_S = 1299,
1313 LOCAL_SET_F64 = 1300,
1314 LOCAL_SET_F64_S = 1301,
1315 LOCAL_SET_FUNCREF = 1302,
1316 LOCAL_SET_FUNCREF_S = 1303,
1317 LOCAL_SET_I32 = 1304,
1318 LOCAL_SET_I32_S = 1305,
1319 LOCAL_SET_I64 = 1306,
1320 LOCAL_SET_I64_S = 1307,
1321 LOCAL_SET_V128 = 1308,
1322 LOCAL_SET_V128_S = 1309,
1323 LOCAL_TEE_EXNREF = 1310,
1324 LOCAL_TEE_EXNREF_S = 1311,
1325 LOCAL_TEE_EXTERNREF = 1312,
1326 LOCAL_TEE_EXTERNREF_S = 1313,
1327 LOCAL_TEE_F32 = 1314,
1328 LOCAL_TEE_F32_S = 1315,
1329 LOCAL_TEE_F64 = 1316,
1330 LOCAL_TEE_F64_S = 1317,
1331 LOCAL_TEE_FUNCREF = 1318,
1332 LOCAL_TEE_FUNCREF_S = 1319,
1333 LOCAL_TEE_I32 = 1320,
1334 LOCAL_TEE_I32_S = 1321,
1335 LOCAL_TEE_I64 = 1322,
1336 LOCAL_TEE_I64_S = 1323,
1337 LOCAL_TEE_V128 = 1324,
1338 LOCAL_TEE_V128_S = 1325,
1339 LOOP = 1326,
1340 LOOP_S = 1327,
1341 LT_F16x8 = 1328,
1342 LT_F16x8_S = 1329,
1343 LT_F32 = 1330,
1344 LT_F32_S = 1331,
1345 LT_F32x4 = 1332,
1346 LT_F32x4_S = 1333,
1347 LT_F64 = 1334,
1348 LT_F64_S = 1335,
1349 LT_F64x2 = 1336,
1350 LT_F64x2_S = 1337,
1351 LT_S_I16x8 = 1338,
1352 LT_S_I16x8_S = 1339,
1353 LT_S_I32 = 1340,
1354 LT_S_I32_S = 1341,
1355 LT_S_I32x4 = 1342,
1356 LT_S_I32x4_S = 1343,
1357 LT_S_I64 = 1344,
1358 LT_S_I64_S = 1345,
1359 LT_S_I64x2 = 1346,
1360 LT_S_I64x2_S = 1347,
1361 LT_S_I8x16 = 1348,
1362 LT_S_I8x16_S = 1349,
1363 LT_U_I16x8 = 1350,
1364 LT_U_I16x8_S = 1351,
1365 LT_U_I32 = 1352,
1366 LT_U_I32_S = 1353,
1367 LT_U_I32x4 = 1354,
1368 LT_U_I32x4_S = 1355,
1369 LT_U_I64 = 1356,
1370 LT_U_I64_S = 1357,
1371 LT_U_I8x16 = 1358,
1372 LT_U_I8x16_S = 1359,
1373 MADD_F16x8 = 1360,
1374 MADD_F16x8_S = 1361,
1375 MADD_F32x4 = 1362,
1376 MADD_F32x4_S = 1363,
1377 MADD_F64x2 = 1364,
1378 MADD_F64x2_S = 1365,
1379 MAX_F16x8 = 1366,
1380 MAX_F16x8_S = 1367,
1381 MAX_F32 = 1368,
1382 MAX_F32_S = 1369,
1383 MAX_F32x4 = 1370,
1384 MAX_F32x4_S = 1371,
1385 MAX_F64 = 1372,
1386 MAX_F64_S = 1373,
1387 MAX_F64x2 = 1374,
1388 MAX_F64x2_S = 1375,
1389 MAX_S_I16x8 = 1376,
1390 MAX_S_I16x8_S = 1377,
1391 MAX_S_I32x4 = 1378,
1392 MAX_S_I32x4_S = 1379,
1393 MAX_S_I8x16 = 1380,
1394 MAX_S_I8x16_S = 1381,
1395 MAX_U_I16x8 = 1382,
1396 MAX_U_I16x8_S = 1383,
1397 MAX_U_I32x4 = 1384,
1398 MAX_U_I32x4_S = 1385,
1399 MAX_U_I8x16 = 1386,
1400 MAX_U_I8x16_S = 1387,
1401 MEMCPY_A32 = 1388,
1402 MEMCPY_A32_S = 1389,
1403 MEMCPY_A64 = 1390,
1404 MEMCPY_A64_S = 1391,
1405 MEMORY_ATOMIC_NOTIFY_A32 = 1392,
1406 MEMORY_ATOMIC_NOTIFY_A32_S = 1393,
1407 MEMORY_ATOMIC_NOTIFY_A64 = 1394,
1408 MEMORY_ATOMIC_NOTIFY_A64_S = 1395,
1409 MEMORY_ATOMIC_WAIT32_A32 = 1396,
1410 MEMORY_ATOMIC_WAIT32_A32_S = 1397,
1411 MEMORY_ATOMIC_WAIT32_A64 = 1398,
1412 MEMORY_ATOMIC_WAIT32_A64_S = 1399,
1413 MEMORY_ATOMIC_WAIT64_A32 = 1400,
1414 MEMORY_ATOMIC_WAIT64_A32_S = 1401,
1415 MEMORY_ATOMIC_WAIT64_A64 = 1402,
1416 MEMORY_ATOMIC_WAIT64_A64_S = 1403,
1417 MEMORY_COPY_A32 = 1404,
1418 MEMORY_COPY_A32_S = 1405,
1419 MEMORY_COPY_A64 = 1406,
1420 MEMORY_COPY_A64_S = 1407,
1421 MEMORY_FILL_A32 = 1408,
1422 MEMORY_FILL_A32_S = 1409,
1423 MEMORY_FILL_A64 = 1410,
1424 MEMORY_FILL_A64_S = 1411,
1425 MEMORY_INIT_A32 = 1412,
1426 MEMORY_INIT_A32_S = 1413,
1427 MEMORY_INIT_A64 = 1414,
1428 MEMORY_INIT_A64_S = 1415,
1429 MEMSET_A32 = 1416,
1430 MEMSET_A32_S = 1417,
1431 MEMSET_A64 = 1418,
1432 MEMSET_A64_S = 1419,
1433 MIN_F16x8 = 1420,
1434 MIN_F16x8_S = 1421,
1435 MIN_F32 = 1422,
1436 MIN_F32_S = 1423,
1437 MIN_F32x4 = 1424,
1438 MIN_F32x4_S = 1425,
1439 MIN_F64 = 1426,
1440 MIN_F64_S = 1427,
1441 MIN_F64x2 = 1428,
1442 MIN_F64x2_S = 1429,
1443 MIN_S_I16x8 = 1430,
1444 MIN_S_I16x8_S = 1431,
1445 MIN_S_I32x4 = 1432,
1446 MIN_S_I32x4_S = 1433,
1447 MIN_S_I8x16 = 1434,
1448 MIN_S_I8x16_S = 1435,
1449 MIN_U_I16x8 = 1436,
1450 MIN_U_I16x8_S = 1437,
1451 MIN_U_I32x4 = 1438,
1452 MIN_U_I32x4_S = 1439,
1453 MIN_U_I8x16 = 1440,
1454 MIN_U_I8x16_S = 1441,
1455 MUL_F16x8 = 1442,
1456 MUL_F16x8_S = 1443,
1457 MUL_F32 = 1444,
1458 MUL_F32_S = 1445,
1459 MUL_F32x4 = 1446,
1460 MUL_F32x4_S = 1447,
1461 MUL_F64 = 1448,
1462 MUL_F64_S = 1449,
1463 MUL_F64x2 = 1450,
1464 MUL_F64x2_S = 1451,
1465 MUL_I16x8 = 1452,
1466 MUL_I16x8_S = 1453,
1467 MUL_I32 = 1454,
1468 MUL_I32_S = 1455,
1469 MUL_I32x4 = 1456,
1470 MUL_I32x4_S = 1457,
1471 MUL_I64 = 1458,
1472 MUL_I64_S = 1459,
1473 MUL_I64x2 = 1460,
1474 MUL_I64x2_S = 1461,
1475 NARROW_S_I16x8 = 1462,
1476 NARROW_S_I16x8_S = 1463,
1477 NARROW_S_I8x16 = 1464,
1478 NARROW_S_I8x16_S = 1465,
1479 NARROW_U_I16x8 = 1466,
1480 NARROW_U_I16x8_S = 1467,
1481 NARROW_U_I8x16 = 1468,
1482 NARROW_U_I8x16_S = 1469,
1483 NEAREST_F16x8 = 1470,
1484 NEAREST_F16x8_S = 1471,
1485 NEAREST_F32 = 1472,
1486 NEAREST_F32_S = 1473,
1487 NEAREST_F32x4 = 1474,
1488 NEAREST_F32x4_S = 1475,
1489 NEAREST_F64 = 1476,
1490 NEAREST_F64_S = 1477,
1491 NEAREST_F64x2 = 1478,
1492 NEAREST_F64x2_S = 1479,
1493 NEG_F16x8 = 1480,
1494 NEG_F16x8_S = 1481,
1495 NEG_F32 = 1482,
1496 NEG_F32_S = 1483,
1497 NEG_F32x4 = 1484,
1498 NEG_F32x4_S = 1485,
1499 NEG_F64 = 1486,
1500 NEG_F64_S = 1487,
1501 NEG_F64x2 = 1488,
1502 NEG_F64x2_S = 1489,
1503 NEG_I16x8 = 1490,
1504 NEG_I16x8_S = 1491,
1505 NEG_I32x4 = 1492,
1506 NEG_I32x4_S = 1493,
1507 NEG_I64x2 = 1494,
1508 NEG_I64x2_S = 1495,
1509 NEG_I8x16 = 1496,
1510 NEG_I8x16_S = 1497,
1511 NE_F16x8 = 1498,
1512 NE_F16x8_S = 1499,
1513 NE_F32 = 1500,
1514 NE_F32_S = 1501,
1515 NE_F32x4 = 1502,
1516 NE_F32x4_S = 1503,
1517 NE_F64 = 1504,
1518 NE_F64_S = 1505,
1519 NE_F64x2 = 1506,
1520 NE_F64x2_S = 1507,
1521 NE_I16x8 = 1508,
1522 NE_I16x8_S = 1509,
1523 NE_I32 = 1510,
1524 NE_I32_S = 1511,
1525 NE_I32x4 = 1512,
1526 NE_I32x4_S = 1513,
1527 NE_I64 = 1514,
1528 NE_I64_S = 1515,
1529 NE_I64x2 = 1516,
1530 NE_I64x2_S = 1517,
1531 NE_I8x16 = 1518,
1532 NE_I8x16_S = 1519,
1533 NMADD_F16x8 = 1520,
1534 NMADD_F16x8_S = 1521,
1535 NMADD_F32x4 = 1522,
1536 NMADD_F32x4_S = 1523,
1537 NMADD_F64x2 = 1524,
1538 NMADD_F64x2_S = 1525,
1539 NOP = 1526,
1540 NOP_S = 1527,
1541 NOT = 1528,
1542 NOT_S = 1529,
1543 OR = 1530,
1544 OR_I32 = 1531,
1545 OR_I32_S = 1532,
1546 OR_I64 = 1533,
1547 OR_I64_S = 1534,
1548 OR_S = 1535,
1549 PMAX_F16x8 = 1536,
1550 PMAX_F16x8_S = 1537,
1551 PMAX_F32x4 = 1538,
1552 PMAX_F32x4_S = 1539,
1553 PMAX_F64x2 = 1540,
1554 PMAX_F64x2_S = 1541,
1555 PMIN_F16x8 = 1542,
1556 PMIN_F16x8_S = 1543,
1557 PMIN_F32x4 = 1544,
1558 PMIN_F32x4_S = 1545,
1559 PMIN_F64x2 = 1546,
1560 PMIN_F64x2_S = 1547,
1561 POPCNT_I32 = 1548,
1562 POPCNT_I32_S = 1549,
1563 POPCNT_I64 = 1550,
1564 POPCNT_I64_S = 1551,
1565 POPCNT_I8x16 = 1552,
1566 POPCNT_I8x16_S = 1553,
1567 Q15MULR_SAT_S_I16x8 = 1554,
1568 Q15MULR_SAT_S_I16x8_S = 1555,
1569 REF_IS_NULL_EXNREF = 1556,
1570 REF_IS_NULL_EXNREF_S = 1557,
1571 REF_IS_NULL_EXTERNREF = 1558,
1572 REF_IS_NULL_EXTERNREF_S = 1559,
1573 REF_IS_NULL_FUNCREF = 1560,
1574 REF_IS_NULL_FUNCREF_S = 1561,
1575 REF_NULL_EXNREF = 1562,
1576 REF_NULL_EXNREF_S = 1563,
1577 REF_NULL_EXTERNREF = 1564,
1578 REF_NULL_EXTERNREF_S = 1565,
1579 REF_NULL_FUNCREF = 1566,
1580 REF_NULL_FUNCREF_S = 1567,
1581 RELAXED_DOT = 1568,
1582 RELAXED_DOT_ADD = 1569,
1583 RELAXED_DOT_ADD_S = 1570,
1584 RELAXED_DOT_BFLOAT = 1571,
1585 RELAXED_DOT_BFLOAT_S = 1572,
1586 RELAXED_DOT_S = 1573,
1587 RELAXED_Q15MULR_S_I16x8 = 1574,
1588 RELAXED_Q15MULR_S_I16x8_S = 1575,
1589 RELAXED_SWIZZLE = 1576,
1590 RELAXED_SWIZZLE_S = 1577,
1591 REM_S_I32 = 1578,
1592 REM_S_I32_S = 1579,
1593 REM_S_I64 = 1580,
1594 REM_S_I64_S = 1581,
1595 REM_U_I32 = 1582,
1596 REM_U_I32_S = 1583,
1597 REM_U_I64 = 1584,
1598 REM_U_I64_S = 1585,
1599 REPLACE_LANE_F16x8 = 1586,
1600 REPLACE_LANE_F16x8_S = 1587,
1601 REPLACE_LANE_F32x4 = 1588,
1602 REPLACE_LANE_F32x4_S = 1589,
1603 REPLACE_LANE_F64x2 = 1590,
1604 REPLACE_LANE_F64x2_S = 1591,
1605 REPLACE_LANE_I16x8 = 1592,
1606 REPLACE_LANE_I16x8_S = 1593,
1607 REPLACE_LANE_I32x4 = 1594,
1608 REPLACE_LANE_I32x4_S = 1595,
1609 REPLACE_LANE_I64x2 = 1596,
1610 REPLACE_LANE_I64x2_S = 1597,
1611 REPLACE_LANE_I8x16 = 1598,
1612 REPLACE_LANE_I8x16_S = 1599,
1613 RETHROW = 1600,
1614 RETHROW_S = 1601,
1615 RETURN = 1602,
1616 RETURN_S = 1603,
1617 RET_CALL = 1604,
1618 RET_CALL_INDIRECT = 1605,
1619 RET_CALL_INDIRECT_S = 1606,
1620 RET_CALL_S = 1607,
1621 ROTL_I32 = 1608,
1622 ROTL_I32_S = 1609,
1623 ROTL_I64 = 1610,
1624 ROTL_I64_S = 1611,
1625 ROTR_I32 = 1612,
1626 ROTR_I32_S = 1613,
1627 ROTR_I64 = 1614,
1628 ROTR_I64_S = 1615,
1629 SELECT_EXNREF = 1616,
1630 SELECT_EXNREF_S = 1617,
1631 SELECT_EXTERNREF = 1618,
1632 SELECT_EXTERNREF_S = 1619,
1633 SELECT_F32 = 1620,
1634 SELECT_F32_S = 1621,
1635 SELECT_F64 = 1622,
1636 SELECT_F64_S = 1623,
1637 SELECT_FUNCREF = 1624,
1638 SELECT_FUNCREF_S = 1625,
1639 SELECT_I32 = 1626,
1640 SELECT_I32_S = 1627,
1641 SELECT_I64 = 1628,
1642 SELECT_I64_S = 1629,
1643 SELECT_V128 = 1630,
1644 SELECT_V128_S = 1631,
1645 SHL_I16x8 = 1632,
1646 SHL_I16x8_S = 1633,
1647 SHL_I32 = 1634,
1648 SHL_I32_S = 1635,
1649 SHL_I32x4 = 1636,
1650 SHL_I32x4_S = 1637,
1651 SHL_I64 = 1638,
1652 SHL_I64_S = 1639,
1653 SHL_I64x2 = 1640,
1654 SHL_I64x2_S = 1641,
1655 SHL_I8x16 = 1642,
1656 SHL_I8x16_S = 1643,
1657 SHR_S_I16x8 = 1644,
1658 SHR_S_I16x8_S = 1645,
1659 SHR_S_I32 = 1646,
1660 SHR_S_I32_S = 1647,
1661 SHR_S_I32x4 = 1648,
1662 SHR_S_I32x4_S = 1649,
1663 SHR_S_I64 = 1650,
1664 SHR_S_I64_S = 1651,
1665 SHR_S_I64x2 = 1652,
1666 SHR_S_I64x2_S = 1653,
1667 SHR_S_I8x16 = 1654,
1668 SHR_S_I8x16_S = 1655,
1669 SHR_U_I16x8 = 1656,
1670 SHR_U_I16x8_S = 1657,
1671 SHR_U_I32 = 1658,
1672 SHR_U_I32_S = 1659,
1673 SHR_U_I32x4 = 1660,
1674 SHR_U_I32x4_S = 1661,
1675 SHR_U_I64 = 1662,
1676 SHR_U_I64_S = 1663,
1677 SHR_U_I64x2 = 1664,
1678 SHR_U_I64x2_S = 1665,
1679 SHR_U_I8x16 = 1666,
1680 SHR_U_I8x16_S = 1667,
1681 SHUFFLE = 1668,
1682 SHUFFLE_S = 1669,
1683 SIMD_RELAXED_FMAX_F32x4 = 1670,
1684 SIMD_RELAXED_FMAX_F32x4_S = 1671,
1685 SIMD_RELAXED_FMAX_F64x2 = 1672,
1686 SIMD_RELAXED_FMAX_F64x2_S = 1673,
1687 SIMD_RELAXED_FMIN_F32x4 = 1674,
1688 SIMD_RELAXED_FMIN_F32x4_S = 1675,
1689 SIMD_RELAXED_FMIN_F64x2 = 1676,
1690 SIMD_RELAXED_FMIN_F64x2_S = 1677,
1691 SPLAT_F16x8 = 1678,
1692 SPLAT_F16x8_S = 1679,
1693 SPLAT_F32x4 = 1680,
1694 SPLAT_F32x4_S = 1681,
1695 SPLAT_F64x2 = 1682,
1696 SPLAT_F64x2_S = 1683,
1697 SPLAT_I16x8 = 1684,
1698 SPLAT_I16x8_S = 1685,
1699 SPLAT_I32x4 = 1686,
1700 SPLAT_I32x4_S = 1687,
1701 SPLAT_I64x2 = 1688,
1702 SPLAT_I64x2_S = 1689,
1703 SPLAT_I8x16 = 1690,
1704 SPLAT_I8x16_S = 1691,
1705 SQRT_F16x8 = 1692,
1706 SQRT_F16x8_S = 1693,
1707 SQRT_F32 = 1694,
1708 SQRT_F32_S = 1695,
1709 SQRT_F32x4 = 1696,
1710 SQRT_F32x4_S = 1697,
1711 SQRT_F64 = 1698,
1712 SQRT_F64_S = 1699,
1713 SQRT_F64x2 = 1700,
1714 SQRT_F64x2_S = 1701,
1715 STORE16_I32_A32 = 1702,
1716 STORE16_I32_A32_S = 1703,
1717 STORE16_I32_A64 = 1704,
1718 STORE16_I32_A64_S = 1705,
1719 STORE16_I64_A32 = 1706,
1720 STORE16_I64_A32_S = 1707,
1721 STORE16_I64_A64 = 1708,
1722 STORE16_I64_A64_S = 1709,
1723 STORE32_I64_A32 = 1710,
1724 STORE32_I64_A32_S = 1711,
1725 STORE32_I64_A64 = 1712,
1726 STORE32_I64_A64_S = 1713,
1727 STORE8_I32_A32 = 1714,
1728 STORE8_I32_A32_S = 1715,
1729 STORE8_I32_A64 = 1716,
1730 STORE8_I32_A64_S = 1717,
1731 STORE8_I64_A32 = 1718,
1732 STORE8_I64_A32_S = 1719,
1733 STORE8_I64_A64 = 1720,
1734 STORE8_I64_A64_S = 1721,
1735 STORE_F16_F32_A32 = 1722,
1736 STORE_F16_F32_A32_S = 1723,
1737 STORE_F16_F32_A64 = 1724,
1738 STORE_F16_F32_A64_S = 1725,
1739 STORE_F32_A32 = 1726,
1740 STORE_F32_A32_S = 1727,
1741 STORE_F32_A64 = 1728,
1742 STORE_F32_A64_S = 1729,
1743 STORE_F64_A32 = 1730,
1744 STORE_F64_A32_S = 1731,
1745 STORE_F64_A64 = 1732,
1746 STORE_F64_A64_S = 1733,
1747 STORE_I32_A32 = 1734,
1748 STORE_I32_A32_S = 1735,
1749 STORE_I32_A64 = 1736,
1750 STORE_I32_A64_S = 1737,
1751 STORE_I64_A32 = 1738,
1752 STORE_I64_A32_S = 1739,
1753 STORE_I64_A64 = 1740,
1754 STORE_I64_A64_S = 1741,
1755 STORE_LANE_I16x8_A32 = 1742,
1756 STORE_LANE_I16x8_A32_S = 1743,
1757 STORE_LANE_I16x8_A64 = 1744,
1758 STORE_LANE_I16x8_A64_S = 1745,
1759 STORE_LANE_I32x4_A32 = 1746,
1760 STORE_LANE_I32x4_A32_S = 1747,
1761 STORE_LANE_I32x4_A64 = 1748,
1762 STORE_LANE_I32x4_A64_S = 1749,
1763 STORE_LANE_I64x2_A32 = 1750,
1764 STORE_LANE_I64x2_A32_S = 1751,
1765 STORE_LANE_I64x2_A64 = 1752,
1766 STORE_LANE_I64x2_A64_S = 1753,
1767 STORE_LANE_I8x16_A32 = 1754,
1768 STORE_LANE_I8x16_A32_S = 1755,
1769 STORE_LANE_I8x16_A64 = 1756,
1770 STORE_LANE_I8x16_A64_S = 1757,
1771 STORE_V128_A32 = 1758,
1772 STORE_V128_A32_S = 1759,
1773 STORE_V128_A64 = 1760,
1774 STORE_V128_A64_S = 1761,
1775 SUB_F16x8 = 1762,
1776 SUB_F16x8_S = 1763,
1777 SUB_F32 = 1764,
1778 SUB_F32_S = 1765,
1779 SUB_F32x4 = 1766,
1780 SUB_F32x4_S = 1767,
1781 SUB_F64 = 1768,
1782 SUB_F64_S = 1769,
1783 SUB_F64x2 = 1770,
1784 SUB_F64x2_S = 1771,
1785 SUB_I16x8 = 1772,
1786 SUB_I16x8_S = 1773,
1787 SUB_I32 = 1774,
1788 SUB_I32_S = 1775,
1789 SUB_I32x4 = 1776,
1790 SUB_I32x4_S = 1777,
1791 SUB_I64 = 1778,
1792 SUB_I64_S = 1779,
1793 SUB_I64x2 = 1780,
1794 SUB_I64x2_S = 1781,
1795 SUB_I8x16 = 1782,
1796 SUB_I8x16_S = 1783,
1797 SUB_SAT_S_I16x8 = 1784,
1798 SUB_SAT_S_I16x8_S = 1785,
1799 SUB_SAT_S_I8x16 = 1786,
1800 SUB_SAT_S_I8x16_S = 1787,
1801 SUB_SAT_U_I16x8 = 1788,
1802 SUB_SAT_U_I16x8_S = 1789,
1803 SUB_SAT_U_I8x16 = 1790,
1804 SUB_SAT_U_I8x16_S = 1791,
1805 SWIZZLE = 1792,
1806 SWIZZLE_S = 1793,
1807 TABLE_COPY = 1794,
1808 TABLE_COPY_S = 1795,
1809 TABLE_FILL_EXNREF = 1796,
1810 TABLE_FILL_EXNREF_S = 1797,
1811 TABLE_FILL_EXTERNREF = 1798,
1812 TABLE_FILL_EXTERNREF_S = 1799,
1813 TABLE_FILL_FUNCREF = 1800,
1814 TABLE_FILL_FUNCREF_S = 1801,
1815 TABLE_GET_EXNREF = 1802,
1816 TABLE_GET_EXNREF_S = 1803,
1817 TABLE_GET_EXTERNREF = 1804,
1818 TABLE_GET_EXTERNREF_S = 1805,
1819 TABLE_GET_FUNCREF = 1806,
1820 TABLE_GET_FUNCREF_S = 1807,
1821 TABLE_GROW_EXNREF = 1808,
1822 TABLE_GROW_EXNREF_S = 1809,
1823 TABLE_GROW_EXTERNREF = 1810,
1824 TABLE_GROW_EXTERNREF_S = 1811,
1825 TABLE_GROW_FUNCREF = 1812,
1826 TABLE_GROW_FUNCREF_S = 1813,
1827 TABLE_SET_EXNREF = 1814,
1828 TABLE_SET_EXNREF_S = 1815,
1829 TABLE_SET_EXTERNREF = 1816,
1830 TABLE_SET_EXTERNREF_S = 1817,
1831 TABLE_SET_FUNCREF = 1818,
1832 TABLE_SET_FUNCREF_S = 1819,
1833 TABLE_SIZE = 1820,
1834 TABLE_SIZE_S = 1821,
1835 TEE_EXNREF = 1822,
1836 TEE_EXNREF_S = 1823,
1837 TEE_EXTERNREF = 1824,
1838 TEE_EXTERNREF_S = 1825,
1839 TEE_F32 = 1826,
1840 TEE_F32_S = 1827,
1841 TEE_F64 = 1828,
1842 TEE_F64_S = 1829,
1843 TEE_FUNCREF = 1830,
1844 TEE_FUNCREF_S = 1831,
1845 TEE_I32 = 1832,
1846 TEE_I32_S = 1833,
1847 TEE_I64 = 1834,
1848 TEE_I64_S = 1835,
1849 TEE_V128 = 1836,
1850 TEE_V128_S = 1837,
1851 THROW = 1838,
1852 THROW_REF = 1839,
1853 THROW_REF_S = 1840,
1854 THROW_S = 1841,
1855 TRUNC_F16x8 = 1842,
1856 TRUNC_F16x8_S = 1843,
1857 TRUNC_F32 = 1844,
1858 TRUNC_F32_S = 1845,
1859 TRUNC_F32x4 = 1846,
1860 TRUNC_F32x4_S = 1847,
1861 TRUNC_F64 = 1848,
1862 TRUNC_F64_S = 1849,
1863 TRUNC_F64x2 = 1850,
1864 TRUNC_F64x2_S = 1851,
1865 TRY = 1852,
1866 TRY_S = 1853,
1867 TRY_TABLE = 1854,
1868 TRY_TABLE_S = 1855,
1869 UNREACHABLE = 1856,
1870 UNREACHABLE_S = 1857,
1871 XOR = 1858,
1872 XOR_I32 = 1859,
1873 XOR_I32_S = 1860,
1874 XOR_I64 = 1861,
1875 XOR_I64_S = 1862,
1876 XOR_S = 1863,
1877 anonymous_8818MEMORY_GROW_A32 = 1864,
1878 anonymous_8818MEMORY_GROW_A32_S = 1865,
1879 anonymous_8818MEMORY_SIZE_A32 = 1866,
1880 anonymous_8818MEMORY_SIZE_A32_S = 1867,
1881 anonymous_8819MEMORY_GROW_A64 = 1868,
1882 anonymous_8819MEMORY_GROW_A64_S = 1869,
1883 anonymous_8819MEMORY_SIZE_A64 = 1870,
1884 anonymous_8819MEMORY_SIZE_A64_S = 1871,
1885 convert_low_s_F64x2 = 1872,
1886 convert_low_s_F64x2_S = 1873,
1887 convert_low_u_F64x2 = 1874,
1888 convert_low_u_F64x2_S = 1875,
1889 demote_zero_F32x4 = 1876,
1890 demote_zero_F32x4_S = 1877,
1891 extend_high_s_I16x8 = 1878,
1892 extend_high_s_I16x8_S = 1879,
1893 extend_high_s_I32x4 = 1880,
1894 extend_high_s_I32x4_S = 1881,
1895 extend_high_s_I64x2 = 1882,
1896 extend_high_s_I64x2_S = 1883,
1897 extend_high_u_I16x8 = 1884,
1898 extend_high_u_I16x8_S = 1885,
1899 extend_high_u_I32x4 = 1886,
1900 extend_high_u_I32x4_S = 1887,
1901 extend_high_u_I64x2 = 1888,
1902 extend_high_u_I64x2_S = 1889,
1903 extend_low_s_I16x8 = 1890,
1904 extend_low_s_I16x8_S = 1891,
1905 extend_low_s_I32x4 = 1892,
1906 extend_low_s_I32x4_S = 1893,
1907 extend_low_s_I64x2 = 1894,
1908 extend_low_s_I64x2_S = 1895,
1909 extend_low_u_I16x8 = 1896,
1910 extend_low_u_I16x8_S = 1897,
1911 extend_low_u_I32x4 = 1898,
1912 extend_low_u_I32x4_S = 1899,
1913 extend_low_u_I64x2 = 1900,
1914 extend_low_u_I64x2_S = 1901,
1915 fp_to_sint_I16x8 = 1902,
1916 fp_to_sint_I16x8_S = 1903,
1917 fp_to_sint_I32x4 = 1904,
1918 fp_to_sint_I32x4_S = 1905,
1919 fp_to_uint_I16x8 = 1906,
1920 fp_to_uint_I16x8_S = 1907,
1921 fp_to_uint_I32x4 = 1908,
1922 fp_to_uint_I32x4_S = 1909,
1923 int_wasm_extadd_pairwise_signed_I16x8 = 1910,
1924 int_wasm_extadd_pairwise_signed_I16x8_S = 1911,
1925 int_wasm_extadd_pairwise_signed_I32x4 = 1912,
1926 int_wasm_extadd_pairwise_signed_I32x4_S = 1913,
1927 int_wasm_extadd_pairwise_unsigned_I16x8 = 1914,
1928 int_wasm_extadd_pairwise_unsigned_I16x8_S = 1915,
1929 int_wasm_extadd_pairwise_unsigned_I32x4 = 1916,
1930 int_wasm_extadd_pairwise_unsigned_I32x4_S = 1917,
1931 int_wasm_relaxed_trunc_signed_I32x4 = 1918,
1932 int_wasm_relaxed_trunc_signed_I32x4_S = 1919,
1933 int_wasm_relaxed_trunc_signed_zero_I32x4 = 1920,
1934 int_wasm_relaxed_trunc_signed_zero_I32x4_S = 1921,
1935 int_wasm_relaxed_trunc_unsigned_I32x4 = 1922,
1936 int_wasm_relaxed_trunc_unsigned_I32x4_S = 1923,
1937 int_wasm_relaxed_trunc_unsigned_zero_I32x4 = 1924,
1938 int_wasm_relaxed_trunc_unsigned_zero_I32x4_S = 1925,
1939 promote_low_F64x2 = 1926,
1940 promote_low_F64x2_S = 1927,
1941 sint_to_fp_F16x8 = 1928,
1942 sint_to_fp_F16x8_S = 1929,
1943 sint_to_fp_F32x4 = 1930,
1944 sint_to_fp_F32x4_S = 1931,
1945 trunc_sat_zero_s_I32x4 = 1932,
1946 trunc_sat_zero_s_I32x4_S = 1933,
1947 trunc_sat_zero_u_I32x4 = 1934,
1948 trunc_sat_zero_u_I32x4_S = 1935,
1949 uint_to_fp_F16x8 = 1936,
1950 uint_to_fp_F16x8_S = 1937,
1951 uint_to_fp_F32x4 = 1938,
1952 uint_to_fp_F32x4_S = 1939,
1953 INSTRUCTION_LIST_END = 1940
1954 };
1955
1956} // end namespace llvm::WebAssembly
1957#endif // GET_INSTRINFO_ENUM
1958
1959#ifdef GET_INSTRINFO_SCHED_ENUM
1960#undef GET_INSTRINFO_SCHED_ENUM
1961namespace llvm::WebAssembly::Sched {
1962
1963 enum {
1964 NoInstrModel = 0,
1965 SCHED_LIST_END = 1
1966 };
1967} // end namespace llvm::WebAssembly::Sched
1968#endif // GET_INSTRINFO_SCHED_ENUM
1969
1970#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
1971namespace llvm {
1972
1973struct WebAssemblyInstrTable {
1974 MCInstrDesc Insts[1940];
1975 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
1976 MCOperandInfo OperandInfo[820];
1977 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
1978 MCPhysReg ImplicitOps[10];
1979};
1980
1981} // end namespace llvm
1982#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
1983
1984#ifdef GET_INSTRINFO_MC_DESC
1985#undef GET_INSTRINFO_MC_DESC
1986namespace llvm {
1987
1988static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
1989static constexpr unsigned WebAssemblyImpOpBase = sizeof WebAssemblyInstrTable::OperandInfo / (sizeof(MCPhysReg));
1990
1991extern const WebAssemblyInstrTable WebAssemblyDescs = {
1992 {
1993 { 1939, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1939 = uint_to_fp_F32x4_S
1994 { 1938, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1938 = uint_to_fp_F32x4
1995 { 1937, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1937 = uint_to_fp_F16x8_S
1996 { 1936, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1936 = uint_to_fp_F16x8
1997 { 1935, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1935 = trunc_sat_zero_u_I32x4_S
1998 { 1934, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1934 = trunc_sat_zero_u_I32x4
1999 { 1933, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1933 = trunc_sat_zero_s_I32x4_S
2000 { 1932, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1932 = trunc_sat_zero_s_I32x4
2001 { 1931, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1931 = sint_to_fp_F32x4_S
2002 { 1930, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1930 = sint_to_fp_F32x4
2003 { 1929, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1929 = sint_to_fp_F16x8_S
2004 { 1928, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1928 = sint_to_fp_F16x8
2005 { 1927, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1927 = promote_low_F64x2_S
2006 { 1926, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1926 = promote_low_F64x2
2007 { 1925, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1925 = int_wasm_relaxed_trunc_unsigned_zero_I32x4_S
2008 { 1924, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1924 = int_wasm_relaxed_trunc_unsigned_zero_I32x4
2009 { 1923, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1923 = int_wasm_relaxed_trunc_unsigned_I32x4_S
2010 { 1922, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1922 = int_wasm_relaxed_trunc_unsigned_I32x4
2011 { 1921, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1921 = int_wasm_relaxed_trunc_signed_zero_I32x4_S
2012 { 1920, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1920 = int_wasm_relaxed_trunc_signed_zero_I32x4
2013 { 1919, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1919 = int_wasm_relaxed_trunc_signed_I32x4_S
2014 { 1918, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1918 = int_wasm_relaxed_trunc_signed_I32x4
2015 { 1917, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1917 = int_wasm_extadd_pairwise_unsigned_I32x4_S
2016 { 1916, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1916 = int_wasm_extadd_pairwise_unsigned_I32x4
2017 { 1915, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1915 = int_wasm_extadd_pairwise_unsigned_I16x8_S
2018 { 1914, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1914 = int_wasm_extadd_pairwise_unsigned_I16x8
2019 { 1913, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1913 = int_wasm_extadd_pairwise_signed_I32x4_S
2020 { 1912, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1912 = int_wasm_extadd_pairwise_signed_I32x4
2021 { 1911, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1911 = int_wasm_extadd_pairwise_signed_I16x8_S
2022 { 1910, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1910 = int_wasm_extadd_pairwise_signed_I16x8
2023 { 1909, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1909 = fp_to_uint_I32x4_S
2024 { 1908, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1908 = fp_to_uint_I32x4
2025 { 1907, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1907 = fp_to_uint_I16x8_S
2026 { 1906, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1906 = fp_to_uint_I16x8
2027 { 1905, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1905 = fp_to_sint_I32x4_S
2028 { 1904, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1904 = fp_to_sint_I32x4
2029 { 1903, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1903 = fp_to_sint_I16x8_S
2030 { 1902, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1902 = fp_to_sint_I16x8
2031 { 1901, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1901 = extend_low_u_I64x2_S
2032 { 1900, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1900 = extend_low_u_I64x2
2033 { 1899, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1899 = extend_low_u_I32x4_S
2034 { 1898, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1898 = extend_low_u_I32x4
2035 { 1897, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1897 = extend_low_u_I16x8_S
2036 { 1896, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1896 = extend_low_u_I16x8
2037 { 1895, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1895 = extend_low_s_I64x2_S
2038 { 1894, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1894 = extend_low_s_I64x2
2039 { 1893, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1893 = extend_low_s_I32x4_S
2040 { 1892, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1892 = extend_low_s_I32x4
2041 { 1891, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1891 = extend_low_s_I16x8_S
2042 { 1890, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1890 = extend_low_s_I16x8
2043 { 1889, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1889 = extend_high_u_I64x2_S
2044 { 1888, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1888 = extend_high_u_I64x2
2045 { 1887, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1887 = extend_high_u_I32x4_S
2046 { 1886, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1886 = extend_high_u_I32x4
2047 { 1885, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1885 = extend_high_u_I16x8_S
2048 { 1884, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1884 = extend_high_u_I16x8
2049 { 1883, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1883 = extend_high_s_I64x2_S
2050 { 1882, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1882 = extend_high_s_I64x2
2051 { 1881, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1881 = extend_high_s_I32x4_S
2052 { 1880, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1880 = extend_high_s_I32x4
2053 { 1879, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1879 = extend_high_s_I16x8_S
2054 { 1878, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1878 = extend_high_s_I16x8
2055 { 1877, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1877 = demote_zero_F32x4_S
2056 { 1876, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1876 = demote_zero_F32x4
2057 { 1875, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1875 = convert_low_u_F64x2_S
2058 { 1874, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1874 = convert_low_u_F64x2
2059 { 1873, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1873 = convert_low_s_F64x2_S
2060 { 1872, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1872 = convert_low_s_F64x2
2061 { 1871, 1, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1871 = anonymous_8819MEMORY_SIZE_A64_S
2062 { 1870, 2, 1, 0, 0, 0, 1, 191, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1870 = anonymous_8819MEMORY_SIZE_A64
2063 { 1869, 1, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1869 = anonymous_8819MEMORY_GROW_A64_S
2064 { 1868, 3, 1, 0, 0, 0, 1, 817, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1868 = anonymous_8819MEMORY_GROW_A64
2065 { 1867, 1, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1867 = anonymous_8818MEMORY_SIZE_A32_S
2066 { 1866, 2, 1, 0, 0, 0, 1, 189, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1866 = anonymous_8818MEMORY_SIZE_A32
2067 { 1865, 1, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1865 = anonymous_8818MEMORY_GROW_A32_S
2068 { 1864, 3, 1, 0, 0, 0, 1, 814, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1864 = anonymous_8818MEMORY_GROW_A32
2069 { 1863, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1863 = XOR_S
2070 { 1862, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1862 = XOR_I64_S
2071 { 1861, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1861 = XOR_I64
2072 { 1860, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1860 = XOR_I32_S
2073 { 1859, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1859 = XOR_I32
2074 { 1858, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1858 = XOR
2075 { 1857, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1857 = UNREACHABLE_S
2076 { 1856, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1856 = UNREACHABLE
2077 { 1855, 2, 0, 0, 0, 1, 1, 812, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1855 = TRY_TABLE_S
2078 { 1854, 1, 0, 0, 0, 1, 1, 279, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1854 = TRY_TABLE
2079 { 1853, 1, 0, 0, 0, 1, 1, 279, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1853 = TRY_S
2080 { 1852, 1, 0, 0, 0, 1, 1, 279, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1852 = TRY
2081 { 1851, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1851 = TRUNC_F64x2_S
2082 { 1850, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1850 = TRUNC_F64x2
2083 { 1849, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1849 = TRUNC_F64_S
2084 { 1848, 2, 1, 0, 0, 0, 1, 160, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1848 = TRUNC_F64
2085 { 1847, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1847 = TRUNC_F32x4_S
2086 { 1846, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1846 = TRUNC_F32x4
2087 { 1845, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1845 = TRUNC_F32_S
2088 { 1844, 2, 1, 0, 0, 0, 1, 158, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1844 = TRUNC_F32
2089 { 1843, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1843 = TRUNC_F16x8_S
2090 { 1842, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1842 = TRUNC_F16x8
2091 { 1841, 1, 0, 0, 0, 0, 1, 287, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1841 = THROW_S
2092 { 1840, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1840 = THROW_REF_S
2093 { 1839, 1, 0, 0, 0, 0, 1, 288, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1839 = THROW_REF
2094 { 1838, 1, 0, 0, 0, 0, 1, 287, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1838 = THROW
2095 { 1837, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1837 = TEE_V128_S
2096 { 1836, 3, 2, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1836 = TEE_V128
2097 { 1835, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1835 = TEE_I64_S
2098 { 1834, 3, 2, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1834 = TEE_I64
2099 { 1833, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1833 = TEE_I32_S
2100 { 1832, 3, 2, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1832 = TEE_I32
2101 { 1831, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1831 = TEE_FUNCREF_S
2102 { 1830, 3, 2, 0, 0, 0, 1, 809, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1830 = TEE_FUNCREF
2103 { 1829, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1829 = TEE_F64_S
2104 { 1828, 3, 2, 0, 0, 0, 1, 168, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1828 = TEE_F64
2105 { 1827, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1827 = TEE_F32_S
2106 { 1826, 3, 2, 0, 0, 0, 1, 165, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1826 = TEE_F32
2107 { 1825, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1825 = TEE_EXTERNREF_S
2108 { 1824, 3, 2, 0, 0, 0, 1, 806, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1824 = TEE_EXTERNREF
2109 { 1823, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1823 = TEE_EXNREF_S
2110 { 1822, 3, 2, 0, 0, 0, 1, 803, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1822 = TEE_EXNREF
2111 { 1821, 1, 0, 0, 0, 0, 1, 762, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1821 = TABLE_SIZE_S
2112 { 1820, 2, 1, 0, 0, 0, 1, 801, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1820 = TABLE_SIZE
2113 { 1819, 1, 0, 0, 0, 0, 1, 762, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1819 = TABLE_SET_FUNCREF_S
2114 { 1818, 3, 0, 0, 0, 0, 1, 798, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1818 = TABLE_SET_FUNCREF
2115 { 1817, 1, 0, 0, 0, 0, 1, 762, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1817 = TABLE_SET_EXTERNREF_S
2116 { 1816, 3, 0, 0, 0, 0, 1, 795, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1816 = TABLE_SET_EXTERNREF
2117 { 1815, 1, 0, 0, 0, 0, 1, 762, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1815 = TABLE_SET_EXNREF_S
2118 { 1814, 3, 0, 0, 0, 0, 1, 792, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1814 = TABLE_SET_EXNREF
2119 { 1813, 1, 0, 0, 0, 0, 1, 762, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1813 = TABLE_GROW_FUNCREF_S
2120 { 1812, 4, 1, 0, 0, 0, 1, 788, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1812 = TABLE_GROW_FUNCREF
2121 { 1811, 1, 0, 0, 0, 0, 1, 762, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1811 = TABLE_GROW_EXTERNREF_S
2122 { 1810, 4, 1, 0, 0, 0, 1, 784, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1810 = TABLE_GROW_EXTERNREF
2123 { 1809, 1, 0, 0, 0, 0, 1, 762, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1809 = TABLE_GROW_EXNREF_S
2124 { 1808, 4, 1, 0, 0, 0, 1, 780, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1808 = TABLE_GROW_EXNREF
2125 { 1807, 1, 0, 0, 0, 0, 1, 762, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1807 = TABLE_GET_FUNCREF_S
2126 { 1806, 3, 1, 0, 0, 0, 1, 777, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1806 = TABLE_GET_FUNCREF
2127 { 1805, 1, 0, 0, 0, 0, 1, 762, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1805 = TABLE_GET_EXTERNREF_S
2128 { 1804, 3, 1, 0, 0, 0, 1, 774, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1804 = TABLE_GET_EXTERNREF
2129 { 1803, 1, 0, 0, 0, 0, 1, 762, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1803 = TABLE_GET_EXNREF_S
2130 { 1802, 3, 1, 0, 0, 0, 1, 771, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1802 = TABLE_GET_EXNREF
2131 { 1801, 1, 0, 0, 0, 0, 1, 762, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1801 = TABLE_FILL_FUNCREF_S
2132 { 1800, 4, 0, 0, 0, 0, 1, 767, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1800 = TABLE_FILL_FUNCREF
2133 { 1799, 1, 0, 0, 0, 0, 1, 762, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1799 = TABLE_FILL_EXTERNREF_S
2134 { 1798, 4, 0, 0, 0, 0, 1, 763, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1798 = TABLE_FILL_EXTERNREF
2135 { 1797, 1, 0, 0, 0, 0, 1, 762, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1797 = TABLE_FILL_EXNREF_S
2136 { 1796, 4, 0, 0, 0, 0, 1, 758, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1796 = TABLE_FILL_EXNREF
2137 { 1795, 2, 0, 0, 0, 0, 1, 756, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1795 = TABLE_COPY_S
2138 { 1794, 5, 0, 0, 0, 0, 1, 751, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1794 = TABLE_COPY
2139 { 1793, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1793 = SWIZZLE_S
2140 { 1792, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1792 = SWIZZLE
2141 { 1791, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1791 = SUB_SAT_U_I8x16_S
2142 { 1790, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1790 = SUB_SAT_U_I8x16
2143 { 1789, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1789 = SUB_SAT_U_I16x8_S
2144 { 1788, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1788 = SUB_SAT_U_I16x8
2145 { 1787, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1787 = SUB_SAT_S_I8x16_S
2146 { 1786, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1786 = SUB_SAT_S_I8x16
2147 { 1785, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1785 = SUB_SAT_S_I16x8_S
2148 { 1784, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1784 = SUB_SAT_S_I16x8
2149 { 1783, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1783 = SUB_I8x16_S
2150 { 1782, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1782 = SUB_I8x16
2151 { 1781, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1781 = SUB_I64x2_S
2152 { 1780, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1780 = SUB_I64x2
2153 { 1779, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1779 = SUB_I64_S
2154 { 1778, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1778 = SUB_I64
2155 { 1777, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1777 = SUB_I32x4_S
2156 { 1776, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1776 = SUB_I32x4
2157 { 1775, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1775 = SUB_I32_S
2158 { 1774, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1774 = SUB_I32
2159 { 1773, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1773 = SUB_I16x8_S
2160 { 1772, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1772 = SUB_I16x8
2161 { 1771, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1771 = SUB_F64x2_S
2162 { 1770, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1770 = SUB_F64x2
2163 { 1769, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1769 = SUB_F64_S
2164 { 1768, 3, 1, 0, 0, 0, 1, 168, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1768 = SUB_F64
2165 { 1767, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1767 = SUB_F32x4_S
2166 { 1766, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1766 = SUB_F32x4
2167 { 1765, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1765 = SUB_F32_S
2168 { 1764, 3, 1, 0, 0, 0, 1, 165, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1764 = SUB_F32
2169 { 1763, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1763 = SUB_F16x8_S
2170 { 1762, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1762 = SUB_F16x8
2171 { 1761, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1761 = STORE_V128_A64_S
2172 { 1760, 4, 0, 0, 0, 0, 1, 747, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1760 = STORE_V128_A64
2173 { 1759, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1759 = STORE_V128_A32_S
2174 { 1758, 4, 0, 0, 0, 0, 1, 743, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1758 = STORE_V128_A32
2175 { 1757, 3, 0, 0, 0, 0, 1, 524, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1757 = STORE_LANE_I8x16_A64_S
2176 { 1756, 5, 0, 0, 0, 0, 1, 738, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1756 = STORE_LANE_I8x16_A64
2177 { 1755, 3, 0, 0, 0, 0, 1, 515, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1755 = STORE_LANE_I8x16_A32_S
2178 { 1754, 5, 0, 0, 0, 0, 1, 733, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1754 = STORE_LANE_I8x16_A32
2179 { 1753, 3, 0, 0, 0, 0, 1, 524, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1753 = STORE_LANE_I64x2_A64_S
2180 { 1752, 5, 0, 0, 0, 0, 1, 738, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1752 = STORE_LANE_I64x2_A64
2181 { 1751, 3, 0, 0, 0, 0, 1, 515, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1751 = STORE_LANE_I64x2_A32_S
2182 { 1750, 5, 0, 0, 0, 0, 1, 733, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1750 = STORE_LANE_I64x2_A32
2183 { 1749, 3, 0, 0, 0, 0, 1, 524, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1749 = STORE_LANE_I32x4_A64_S
2184 { 1748, 5, 0, 0, 0, 0, 1, 738, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1748 = STORE_LANE_I32x4_A64
2185 { 1747, 3, 0, 0, 0, 0, 1, 515, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1747 = STORE_LANE_I32x4_A32_S
2186 { 1746, 5, 0, 0, 0, 0, 1, 733, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1746 = STORE_LANE_I32x4_A32
2187 { 1745, 3, 0, 0, 0, 0, 1, 524, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1745 = STORE_LANE_I16x8_A64_S
2188 { 1744, 5, 0, 0, 0, 0, 1, 738, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1744 = STORE_LANE_I16x8_A64
2189 { 1743, 3, 0, 0, 0, 0, 1, 515, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1743 = STORE_LANE_I16x8_A32_S
2190 { 1742, 5, 0, 0, 0, 0, 1, 733, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1742 = STORE_LANE_I16x8_A32
2191 { 1741, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1741 = STORE_I64_A64_S
2192 { 1740, 4, 0, 0, 0, 0, 1, 271, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1740 = STORE_I64_A64
2193 { 1739, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1739 = STORE_I64_A32_S
2194 { 1738, 4, 0, 0, 0, 0, 1, 267, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1738 = STORE_I64_A32
2195 { 1737, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1737 = STORE_I32_A64_S
2196 { 1736, 4, 0, 0, 0, 0, 1, 263, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1736 = STORE_I32_A64
2197 { 1735, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1735 = STORE_I32_A32_S
2198 { 1734, 4, 0, 0, 0, 0, 1, 259, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1734 = STORE_I32_A32
2199 { 1733, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1733 = STORE_F64_A64_S
2200 { 1732, 4, 0, 0, 0, 0, 1, 729, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1732 = STORE_F64_A64
2201 { 1731, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1731 = STORE_F64_A32_S
2202 { 1730, 4, 0, 0, 0, 0, 1, 725, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1730 = STORE_F64_A32
2203 { 1729, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1729 = STORE_F32_A64_S
2204 { 1728, 4, 0, 0, 0, 0, 1, 721, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1728 = STORE_F32_A64
2205 { 1727, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1727 = STORE_F32_A32_S
2206 { 1726, 4, 0, 0, 0, 0, 1, 717, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1726 = STORE_F32_A32
2207 { 1725, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1725 = STORE_F16_F32_A64_S
2208 { 1724, 4, 0, 0, 0, 0, 1, 721, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1724 = STORE_F16_F32_A64
2209 { 1723, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1723 = STORE_F16_F32_A32_S
2210 { 1722, 4, 0, 0, 0, 0, 1, 717, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1722 = STORE_F16_F32_A32
2211 { 1721, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1721 = STORE8_I64_A64_S
2212 { 1720, 4, 0, 0, 0, 0, 1, 271, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1720 = STORE8_I64_A64
2213 { 1719, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1719 = STORE8_I64_A32_S
2214 { 1718, 4, 0, 0, 0, 0, 1, 267, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1718 = STORE8_I64_A32
2215 { 1717, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1717 = STORE8_I32_A64_S
2216 { 1716, 4, 0, 0, 0, 0, 1, 263, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1716 = STORE8_I32_A64
2217 { 1715, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1715 = STORE8_I32_A32_S
2218 { 1714, 4, 0, 0, 0, 0, 1, 259, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1714 = STORE8_I32_A32
2219 { 1713, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1713 = STORE32_I64_A64_S
2220 { 1712, 4, 0, 0, 0, 0, 1, 271, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1712 = STORE32_I64_A64
2221 { 1711, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1711 = STORE32_I64_A32_S
2222 { 1710, 4, 0, 0, 0, 0, 1, 267, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1710 = STORE32_I64_A32
2223 { 1709, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1709 = STORE16_I64_A64_S
2224 { 1708, 4, 0, 0, 0, 0, 1, 271, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1708 = STORE16_I64_A64
2225 { 1707, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1707 = STORE16_I64_A32_S
2226 { 1706, 4, 0, 0, 0, 0, 1, 267, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1706 = STORE16_I64_A32
2227 { 1705, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1705 = STORE16_I32_A64_S
2228 { 1704, 4, 0, 0, 0, 0, 1, 263, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1704 = STORE16_I32_A64
2229 { 1703, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1703 = STORE16_I32_A32_S
2230 { 1702, 4, 0, 0, 0, 0, 1, 259, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1702 = STORE16_I32_A32
2231 { 1701, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1701 = SQRT_F64x2_S
2232 { 1700, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1700 = SQRT_F64x2
2233 { 1699, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1699 = SQRT_F64_S
2234 { 1698, 2, 1, 0, 0, 0, 1, 160, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1698 = SQRT_F64
2235 { 1697, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1697 = SQRT_F32x4_S
2236 { 1696, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1696 = SQRT_F32x4
2237 { 1695, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1695 = SQRT_F32_S
2238 { 1694, 2, 1, 0, 0, 0, 1, 158, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1694 = SQRT_F32
2239 { 1693, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1693 = SQRT_F16x8_S
2240 { 1692, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1692 = SQRT_F16x8
2241 { 1691, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1691 = SPLAT_I8x16_S
2242 { 1690, 2, 1, 0, 0, 0, 1, 713, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1690 = SPLAT_I8x16
2243 { 1689, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1689 = SPLAT_I64x2_S
2244 { 1688, 2, 1, 0, 0, 0, 1, 715, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1688 = SPLAT_I64x2
2245 { 1687, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1687 = SPLAT_I32x4_S
2246 { 1686, 2, 1, 0, 0, 0, 1, 713, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1686 = SPLAT_I32x4
2247 { 1685, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1685 = SPLAT_I16x8_S
2248 { 1684, 2, 1, 0, 0, 0, 1, 713, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1684 = SPLAT_I16x8
2249 { 1683, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1683 = SPLAT_F64x2_S
2250 { 1682, 2, 1, 0, 0, 0, 1, 711, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1682 = SPLAT_F64x2
2251 { 1681, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1681 = SPLAT_F32x4_S
2252 { 1680, 2, 1, 0, 0, 0, 1, 709, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1680 = SPLAT_F32x4
2253 { 1679, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1679 = SPLAT_F16x8_S
2254 { 1678, 2, 1, 0, 0, 0, 1, 709, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1678 = SPLAT_F16x8
2255 { 1677, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1677 = SIMD_RELAXED_FMIN_F64x2_S
2256 { 1676, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1676 = SIMD_RELAXED_FMIN_F64x2
2257 { 1675, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1675 = SIMD_RELAXED_FMIN_F32x4_S
2258 { 1674, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1674 = SIMD_RELAXED_FMIN_F32x4
2259 { 1673, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1673 = SIMD_RELAXED_FMAX_F64x2_S
2260 { 1672, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1672 = SIMD_RELAXED_FMAX_F64x2
2261 { 1671, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1671 = SIMD_RELAXED_FMAX_F32x4_S
2262 { 1670, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1670 = SIMD_RELAXED_FMAX_F32x4
2263 { 1669, 16, 0, 0, 0, 0, 1, 367, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1669 = SHUFFLE_S
2264 { 1668, 19, 1, 0, 0, 0, 1, 690, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1668 = SHUFFLE
2265 { 1667, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1667 = SHR_U_I8x16_S
2266 { 1666, 3, 1, 0, 0, 0, 1, 687, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1666 = SHR_U_I8x16
2267 { 1665, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1665 = SHR_U_I64x2_S
2268 { 1664, 3, 1, 0, 0, 0, 1, 687, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1664 = SHR_U_I64x2
2269 { 1663, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1663 = SHR_U_I64_S
2270 { 1662, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1662 = SHR_U_I64
2271 { 1661, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1661 = SHR_U_I32x4_S
2272 { 1660, 3, 1, 0, 0, 0, 1, 687, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1660 = SHR_U_I32x4
2273 { 1659, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1659 = SHR_U_I32_S
2274 { 1658, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1658 = SHR_U_I32
2275 { 1657, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1657 = SHR_U_I16x8_S
2276 { 1656, 3, 1, 0, 0, 0, 1, 687, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1656 = SHR_U_I16x8
2277 { 1655, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1655 = SHR_S_I8x16_S
2278 { 1654, 3, 1, 0, 0, 0, 1, 687, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1654 = SHR_S_I8x16
2279 { 1653, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1653 = SHR_S_I64x2_S
2280 { 1652, 3, 1, 0, 0, 0, 1, 687, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1652 = SHR_S_I64x2
2281 { 1651, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1651 = SHR_S_I64_S
2282 { 1650, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1650 = SHR_S_I64
2283 { 1649, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1649 = SHR_S_I32x4_S
2284 { 1648, 3, 1, 0, 0, 0, 1, 687, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1648 = SHR_S_I32x4
2285 { 1647, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1647 = SHR_S_I32_S
2286 { 1646, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1646 = SHR_S_I32
2287 { 1645, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1645 = SHR_S_I16x8_S
2288 { 1644, 3, 1, 0, 0, 0, 1, 687, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1644 = SHR_S_I16x8
2289 { 1643, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1643 = SHL_I8x16_S
2290 { 1642, 3, 1, 0, 0, 0, 1, 687, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1642 = SHL_I8x16
2291 { 1641, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1641 = SHL_I64x2_S
2292 { 1640, 3, 1, 0, 0, 0, 1, 687, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1640 = SHL_I64x2
2293 { 1639, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1639 = SHL_I64_S
2294 { 1638, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1638 = SHL_I64
2295 { 1637, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1637 = SHL_I32x4_S
2296 { 1636, 3, 1, 0, 0, 0, 1, 687, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1636 = SHL_I32x4
2297 { 1635, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1635 = SHL_I32_S
2298 { 1634, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1634 = SHL_I32
2299 { 1633, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1633 = SHL_I16x8_S
2300 { 1632, 3, 1, 0, 0, 0, 1, 687, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1632 = SHL_I16x8
2301 { 1631, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1631 = SELECT_V128_S
2302 { 1630, 4, 1, 0, 0, 0, 1, 683, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1630 = SELECT_V128
2303 { 1629, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1629 = SELECT_I64_S
2304 { 1628, 4, 1, 0, 0, 0, 1, 679, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1628 = SELECT_I64
2305 { 1627, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1627 = SELECT_I32_S
2306 { 1626, 4, 1, 0, 0, 0, 1, 675, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1626 = SELECT_I32
2307 { 1625, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1625 = SELECT_FUNCREF_S
2308 { 1624, 4, 1, 0, 0, 0, 1, 671, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1624 = SELECT_FUNCREF
2309 { 1623, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1623 = SELECT_F64_S
2310 { 1622, 4, 1, 0, 0, 0, 1, 667, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1622 = SELECT_F64
2311 { 1621, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1621 = SELECT_F32_S
2312 { 1620, 4, 1, 0, 0, 0, 1, 663, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1620 = SELECT_F32
2313 { 1619, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1619 = SELECT_EXTERNREF_S
2314 { 1618, 4, 1, 0, 0, 0, 1, 659, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1618 = SELECT_EXTERNREF
2315 { 1617, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1617 = SELECT_EXNREF_S
2316 { 1616, 4, 1, 0, 0, 0, 1, 655, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1616 = SELECT_EXNREF
2317 { 1615, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1615 = ROTR_I64_S
2318 { 1614, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1614 = ROTR_I64
2319 { 1613, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1613 = ROTR_I32_S
2320 { 1612, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1612 = ROTR_I32
2321 { 1611, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1611 = ROTL_I64_S
2322 { 1610, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1610 = ROTL_I64
2323 { 1609, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1609 = ROTL_I32_S
2324 { 1608, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1608 = ROTL_I32
2325 { 1607, 1, 0, 0, 0, 2, 1, 152, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1607 = RET_CALL_S
2326 { 1606, 2, 0, 0, 0, 2, 1, 285, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1606 = RET_CALL_INDIRECT_S
2327 { 1605, 2, 0, 0, 0, 2, 1, 285, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1605 = RET_CALL_INDIRECT
2328 { 1604, 1, 0, 0, 0, 2, 1, 152, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1604 = RET_CALL
2329 { 1603, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1603 = RETURN_S
2330 { 1602, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1602 = RETURN
2331 { 1601, 1, 0, 0, 0, 0, 1, 155, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1601 = RETHROW_S
2332 { 1600, 1, 0, 0, 0, 0, 1, 155, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1600 = RETHROW
2333 { 1599, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1599 = REPLACE_LANE_I8x16_S
2334 { 1598, 4, 1, 0, 0, 0, 1, 647, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1598 = REPLACE_LANE_I8x16
2335 { 1597, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1597 = REPLACE_LANE_I64x2_S
2336 { 1596, 4, 1, 0, 0, 0, 1, 651, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1596 = REPLACE_LANE_I64x2
2337 { 1595, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1595 = REPLACE_LANE_I32x4_S
2338 { 1594, 4, 1, 0, 0, 0, 1, 647, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1594 = REPLACE_LANE_I32x4
2339 { 1593, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1593 = REPLACE_LANE_I16x8_S
2340 { 1592, 4, 1, 0, 0, 0, 1, 647, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1592 = REPLACE_LANE_I16x8
2341 { 1591, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1591 = REPLACE_LANE_F64x2_S
2342 { 1590, 4, 1, 0, 0, 0, 1, 643, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1590 = REPLACE_LANE_F64x2
2343 { 1589, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1589 = REPLACE_LANE_F32x4_S
2344 { 1588, 4, 1, 0, 0, 0, 1, 639, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1588 = REPLACE_LANE_F32x4
2345 { 1587, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1587 = REPLACE_LANE_F16x8_S
2346 { 1586, 4, 1, 0, 0, 0, 1, 639, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1586 = REPLACE_LANE_F16x8
2347 { 1585, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1585 = REM_U_I64_S
2348 { 1584, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1584 = REM_U_I64
2349 { 1583, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1583 = REM_U_I32_S
2350 { 1582, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1582 = REM_U_I32
2351 { 1581, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1581 = REM_S_I64_S
2352 { 1580, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1580 = REM_S_I64
2353 { 1579, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1579 = REM_S_I32_S
2354 { 1578, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1578 = REM_S_I32
2355 { 1577, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1577 = RELAXED_SWIZZLE_S
2356 { 1576, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1576 = RELAXED_SWIZZLE
2357 { 1575, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1575 = RELAXED_Q15MULR_S_I16x8_S
2358 { 1574, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1574 = RELAXED_Q15MULR_S_I16x8
2359 { 1573, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1573 = RELAXED_DOT_S
2360 { 1572, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1572 = RELAXED_DOT_BFLOAT_S
2361 { 1571, 4, 1, 0, 0, 0, 1, 275, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1571 = RELAXED_DOT_BFLOAT
2362 { 1570, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1570 = RELAXED_DOT_ADD_S
2363 { 1569, 4, 1, 0, 0, 0, 1, 275, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1569 = RELAXED_DOT_ADD
2364 { 1568, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1568 = RELAXED_DOT
2365 { 1567, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1567 = REF_NULL_FUNCREF_S
2366 { 1566, 1, 1, 0, 0, 0, 1, 392, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1566 = REF_NULL_FUNCREF
2367 { 1565, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1565 = REF_NULL_EXTERNREF_S
2368 { 1564, 1, 1, 0, 0, 0, 1, 389, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1564 = REF_NULL_EXTERNREF
2369 { 1563, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1563 = REF_NULL_EXNREF_S
2370 { 1562, 1, 1, 0, 0, 0, 1, 288, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1562 = REF_NULL_EXNREF
2371 { 1561, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1561 = REF_IS_NULL_FUNCREF_S
2372 { 1560, 2, 1, 0, 0, 0, 1, 637, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1560 = REF_IS_NULL_FUNCREF
2373 { 1559, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1559 = REF_IS_NULL_EXTERNREF_S
2374 { 1558, 2, 1, 0, 0, 0, 1, 635, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1558 = REF_IS_NULL_EXTERNREF
2375 { 1557, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1557 = REF_IS_NULL_EXNREF_S
2376 { 1556, 2, 1, 0, 0, 0, 1, 633, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1556 = REF_IS_NULL_EXNREF
2377 { 1555, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1555 = Q15MULR_SAT_S_I16x8_S
2378 { 1554, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1554 = Q15MULR_SAT_S_I16x8
2379 { 1553, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1553 = POPCNT_I8x16_S
2380 { 1552, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1552 = POPCNT_I8x16
2381 { 1551, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1551 = POPCNT_I64_S
2382 { 1550, 2, 1, 0, 0, 0, 1, 291, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1550 = POPCNT_I64
2383 { 1549, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1549 = POPCNT_I32_S
2384 { 1548, 2, 1, 0, 0, 0, 1, 289, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1548 = POPCNT_I32
2385 { 1547, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1547 = PMIN_F64x2_S
2386 { 1546, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1546 = PMIN_F64x2
2387 { 1545, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1545 = PMIN_F32x4_S
2388 { 1544, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1544 = PMIN_F32x4
2389 { 1543, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1543 = PMIN_F16x8_S
2390 { 1542, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1542 = PMIN_F16x8
2391 { 1541, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1541 = PMAX_F64x2_S
2392 { 1540, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1540 = PMAX_F64x2
2393 { 1539, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1539 = PMAX_F32x4_S
2394 { 1538, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1538 = PMAX_F32x4
2395 { 1537, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1537 = PMAX_F16x8_S
2396 { 1536, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1536 = PMAX_F16x8
2397 { 1535, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1535 = OR_S
2398 { 1534, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1534 = OR_I64_S
2399 { 1533, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1533 = OR_I64
2400 { 1532, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1532 = OR_I32_S
2401 { 1531, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1531 = OR_I32
2402 { 1530, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1530 = OR
2403 { 1529, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1529 = NOT_S
2404 { 1528, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1528 = NOT
2405 { 1527, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1527 = NOP_S
2406 { 1526, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1526 = NOP
2407 { 1525, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1525 = NMADD_F64x2_S
2408 { 1524, 4, 1, 0, 0, 0, 1, 275, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1524 = NMADD_F64x2
2409 { 1523, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1523 = NMADD_F32x4_S
2410 { 1522, 4, 1, 0, 0, 0, 1, 275, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1522 = NMADD_F32x4
2411 { 1521, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1521 = NMADD_F16x8_S
2412 { 1520, 4, 1, 0, 0, 0, 1, 275, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1520 = NMADD_F16x8
2413 { 1519, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1519 = NE_I8x16_S
2414 { 1518, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1518 = NE_I8x16
2415 { 1517, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1517 = NE_I64x2_S
2416 { 1516, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1516 = NE_I64x2
2417 { 1515, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1515 = NE_I64_S
2418 { 1514, 3, 1, 0, 0, 0, 1, 402, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1514 = NE_I64
2419 { 1513, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1513 = NE_I32x4_S
2420 { 1512, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1512 = NE_I32x4
2421 { 1511, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1511 = NE_I32_S
2422 { 1510, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1510 = NE_I32
2423 { 1509, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1509 = NE_I16x8_S
2424 { 1508, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1508 = NE_I16x8
2425 { 1507, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1507 = NE_F64x2_S
2426 { 1506, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1506 = NE_F64x2
2427 { 1505, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1505 = NE_F64_S
2428 { 1504, 3, 1, 0, 0, 0, 1, 399, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1504 = NE_F64
2429 { 1503, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1503 = NE_F32x4_S
2430 { 1502, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1502 = NE_F32x4
2431 { 1501, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1501 = NE_F32_S
2432 { 1500, 3, 1, 0, 0, 0, 1, 396, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1500 = NE_F32
2433 { 1499, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1499 = NE_F16x8_S
2434 { 1498, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1498 = NE_F16x8
2435 { 1497, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1497 = NEG_I8x16_S
2436 { 1496, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1496 = NEG_I8x16
2437 { 1495, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1495 = NEG_I64x2_S
2438 { 1494, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1494 = NEG_I64x2
2439 { 1493, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1493 = NEG_I32x4_S
2440 { 1492, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1492 = NEG_I32x4
2441 { 1491, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1491 = NEG_I16x8_S
2442 { 1490, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1490 = NEG_I16x8
2443 { 1489, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1489 = NEG_F64x2_S
2444 { 1488, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1488 = NEG_F64x2
2445 { 1487, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1487 = NEG_F64_S
2446 { 1486, 2, 1, 0, 0, 0, 1, 160, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1486 = NEG_F64
2447 { 1485, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1485 = NEG_F32x4_S
2448 { 1484, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1484 = NEG_F32x4
2449 { 1483, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1483 = NEG_F32_S
2450 { 1482, 2, 1, 0, 0, 0, 1, 158, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1482 = NEG_F32
2451 { 1481, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1481 = NEG_F16x8_S
2452 { 1480, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1480 = NEG_F16x8
2453 { 1479, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1479 = NEAREST_F64x2_S
2454 { 1478, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1478 = NEAREST_F64x2
2455 { 1477, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1477 = NEAREST_F64_S
2456 { 1476, 2, 1, 0, 0, 0, 1, 160, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1476 = NEAREST_F64
2457 { 1475, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1475 = NEAREST_F32x4_S
2458 { 1474, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1474 = NEAREST_F32x4
2459 { 1473, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1473 = NEAREST_F32_S
2460 { 1472, 2, 1, 0, 0, 0, 1, 158, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1472 = NEAREST_F32
2461 { 1471, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1471 = NEAREST_F16x8_S
2462 { 1470, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1470 = NEAREST_F16x8
2463 { 1469, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1469 = NARROW_U_I8x16_S
2464 { 1468, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1468 = NARROW_U_I8x16
2465 { 1467, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1467 = NARROW_U_I16x8_S
2466 { 1466, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1466 = NARROW_U_I16x8
2467 { 1465, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1465 = NARROW_S_I8x16_S
2468 { 1464, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1464 = NARROW_S_I8x16
2469 { 1463, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1463 = NARROW_S_I16x8_S
2470 { 1462, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1462 = NARROW_S_I16x8
2471 { 1461, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1461 = MUL_I64x2_S
2472 { 1460, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1460 = MUL_I64x2
2473 { 1459, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1459 = MUL_I64_S
2474 { 1458, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1458 = MUL_I64
2475 { 1457, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1457 = MUL_I32x4_S
2476 { 1456, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1456 = MUL_I32x4
2477 { 1455, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1455 = MUL_I32_S
2478 { 1454, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1454 = MUL_I32
2479 { 1453, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1453 = MUL_I16x8_S
2480 { 1452, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1452 = MUL_I16x8
2481 { 1451, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1451 = MUL_F64x2_S
2482 { 1450, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1450 = MUL_F64x2
2483 { 1449, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1449 = MUL_F64_S
2484 { 1448, 3, 1, 0, 0, 0, 1, 168, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1448 = MUL_F64
2485 { 1447, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1447 = MUL_F32x4_S
2486 { 1446, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1446 = MUL_F32x4
2487 { 1445, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1445 = MUL_F32_S
2488 { 1444, 3, 1, 0, 0, 0, 1, 165, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1444 = MUL_F32
2489 { 1443, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1443 = MUL_F16x8_S
2490 { 1442, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1442 = MUL_F16x8
2491 { 1441, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1441 = MIN_U_I8x16_S
2492 { 1440, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1440 = MIN_U_I8x16
2493 { 1439, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1439 = MIN_U_I32x4_S
2494 { 1438, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1438 = MIN_U_I32x4
2495 { 1437, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1437 = MIN_U_I16x8_S
2496 { 1436, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1436 = MIN_U_I16x8
2497 { 1435, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1435 = MIN_S_I8x16_S
2498 { 1434, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1434 = MIN_S_I8x16
2499 { 1433, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1433 = MIN_S_I32x4_S
2500 { 1432, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1432 = MIN_S_I32x4
2501 { 1431, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1431 = MIN_S_I16x8_S
2502 { 1430, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1430 = MIN_S_I16x8
2503 { 1429, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1429 = MIN_F64x2_S
2504 { 1428, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1428 = MIN_F64x2
2505 { 1427, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1427 = MIN_F64_S
2506 { 1426, 3, 1, 0, 0, 0, 1, 168, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1426 = MIN_F64
2507 { 1425, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1425 = MIN_F32x4_S
2508 { 1424, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1424 = MIN_F32x4
2509 { 1423, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1423 = MIN_F32_S
2510 { 1422, 3, 1, 0, 0, 0, 1, 165, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1422 = MIN_F32
2511 { 1421, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1421 = MIN_F16x8_S
2512 { 1420, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1420 = MIN_F16x8
2513 { 1419, 1, 0, 0, 0, 0, 1, 301, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1419 = MEMSET_A64_S
2514 { 1418, 4, 0, 0, 0, 0, 1, 624, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1418 = MEMSET_A64
2515 { 1417, 1, 0, 0, 0, 0, 1, 301, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1417 = MEMSET_A32_S
2516 { 1416, 4, 0, 0, 0, 0, 1, 620, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1416 = MEMSET_A32
2517 { 1415, 2, 0, 0, 0, 0, 1, 589, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1415 = MEMORY_INIT_A64_S
2518 { 1414, 5, 0, 0, 0, 0, 1, 628, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1414 = MEMORY_INIT_A64
2519 { 1413, 2, 0, 0, 0, 0, 1, 589, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1413 = MEMORY_INIT_A32_S
2520 { 1412, 5, 0, 0, 0, 0, 1, 584, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1412 = MEMORY_INIT_A32
2521 { 1411, 1, 0, 0, 0, 0, 1, 301, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1411 = MEMORY_FILL_A64_S
2522 { 1410, 4, 0, 0, 0, 0, 1, 624, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1410 = MEMORY_FILL_A64
2523 { 1409, 1, 0, 0, 0, 0, 1, 301, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1409 = MEMORY_FILL_A32_S
2524 { 1408, 4, 0, 0, 0, 0, 1, 620, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1408 = MEMORY_FILL_A32
2525 { 1407, 2, 0, 0, 0, 0, 1, 589, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1407 = MEMORY_COPY_A64_S
2526 { 1406, 5, 0, 0, 0, 0, 1, 591, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1406 = MEMORY_COPY_A64
2527 { 1405, 2, 0, 0, 0, 0, 1, 589, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1405 = MEMORY_COPY_A32_S
2528 { 1404, 5, 0, 0, 0, 0, 1, 584, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1404 = MEMORY_COPY_A32
2529 { 1403, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1403 = MEMORY_ATOMIC_WAIT64_A64_S
2530 { 1402, 6, 1, 0, 0, 0, 1, 614, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1402 = MEMORY_ATOMIC_WAIT64_A64
2531 { 1401, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1401 = MEMORY_ATOMIC_WAIT64_A32_S
2532 { 1400, 6, 1, 0, 0, 0, 1, 608, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1400 = MEMORY_ATOMIC_WAIT64_A32
2533 { 1399, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1399 = MEMORY_ATOMIC_WAIT32_A64_S
2534 { 1398, 6, 1, 0, 0, 0, 1, 602, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1398 = MEMORY_ATOMIC_WAIT32_A64
2535 { 1397, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1397 = MEMORY_ATOMIC_WAIT32_A32_S
2536 { 1396, 6, 1, 0, 0, 0, 1, 596, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1396 = MEMORY_ATOMIC_WAIT32_A32
2537 { 1395, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1395 = MEMORY_ATOMIC_NOTIFY_A64_S
2538 { 1394, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1394 = MEMORY_ATOMIC_NOTIFY_A64
2539 { 1393, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1393 = MEMORY_ATOMIC_NOTIFY_A32_S
2540 { 1392, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1392 = MEMORY_ATOMIC_NOTIFY_A32
2541 { 1391, 2, 0, 0, 0, 0, 1, 589, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1391 = MEMCPY_A64_S
2542 { 1390, 5, 0, 0, 0, 0, 1, 591, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1390 = MEMCPY_A64
2543 { 1389, 2, 0, 0, 0, 0, 1, 589, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1389 = MEMCPY_A32_S
2544 { 1388, 5, 0, 0, 0, 0, 1, 584, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1388 = MEMCPY_A32
2545 { 1387, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1387 = MAX_U_I8x16_S
2546 { 1386, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1386 = MAX_U_I8x16
2547 { 1385, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1385 = MAX_U_I32x4_S
2548 { 1384, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1384 = MAX_U_I32x4
2549 { 1383, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1383 = MAX_U_I16x8_S
2550 { 1382, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1382 = MAX_U_I16x8
2551 { 1381, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1381 = MAX_S_I8x16_S
2552 { 1380, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1380 = MAX_S_I8x16
2553 { 1379, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1379 = MAX_S_I32x4_S
2554 { 1378, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1378 = MAX_S_I32x4
2555 { 1377, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1377 = MAX_S_I16x8_S
2556 { 1376, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1376 = MAX_S_I16x8
2557 { 1375, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1375 = MAX_F64x2_S
2558 { 1374, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1374 = MAX_F64x2
2559 { 1373, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1373 = MAX_F64_S
2560 { 1372, 3, 1, 0, 0, 0, 1, 168, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1372 = MAX_F64
2561 { 1371, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1371 = MAX_F32x4_S
2562 { 1370, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1370 = MAX_F32x4
2563 { 1369, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1369 = MAX_F32_S
2564 { 1368, 3, 1, 0, 0, 0, 1, 165, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1368 = MAX_F32
2565 { 1367, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1367 = MAX_F16x8_S
2566 { 1366, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1366 = MAX_F16x8
2567 { 1365, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1365 = MADD_F64x2_S
2568 { 1364, 4, 1, 0, 0, 0, 1, 275, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1364 = MADD_F64x2
2569 { 1363, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1363 = MADD_F32x4_S
2570 { 1362, 4, 1, 0, 0, 0, 1, 275, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1362 = MADD_F32x4
2571 { 1361, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1361 = MADD_F16x8_S
2572 { 1360, 4, 1, 0, 0, 0, 1, 275, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1360 = MADD_F16x8
2573 { 1359, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1359 = LT_U_I8x16_S
2574 { 1358, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1358 = LT_U_I8x16
2575 { 1357, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1357 = LT_U_I64_S
2576 { 1356, 3, 1, 0, 0, 0, 1, 402, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1356 = LT_U_I64
2577 { 1355, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1355 = LT_U_I32x4_S
2578 { 1354, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1354 = LT_U_I32x4
2579 { 1353, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1353 = LT_U_I32_S
2580 { 1352, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1352 = LT_U_I32
2581 { 1351, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1351 = LT_U_I16x8_S
2582 { 1350, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1350 = LT_U_I16x8
2583 { 1349, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1349 = LT_S_I8x16_S
2584 { 1348, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1348 = LT_S_I8x16
2585 { 1347, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1347 = LT_S_I64x2_S
2586 { 1346, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1346 = LT_S_I64x2
2587 { 1345, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1345 = LT_S_I64_S
2588 { 1344, 3, 1, 0, 0, 0, 1, 402, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1344 = LT_S_I64
2589 { 1343, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1343 = LT_S_I32x4_S
2590 { 1342, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1342 = LT_S_I32x4
2591 { 1341, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1341 = LT_S_I32_S
2592 { 1340, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1340 = LT_S_I32
2593 { 1339, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1339 = LT_S_I16x8_S
2594 { 1338, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1338 = LT_S_I16x8
2595 { 1337, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1337 = LT_F64x2_S
2596 { 1336, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1336 = LT_F64x2
2597 { 1335, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1335 = LT_F64_S
2598 { 1334, 3, 1, 0, 0, 0, 1, 399, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1334 = LT_F64
2599 { 1333, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1333 = LT_F32x4_S
2600 { 1332, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1332 = LT_F32x4
2601 { 1331, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1331 = LT_F32_S
2602 { 1330, 3, 1, 0, 0, 0, 1, 396, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1330 = LT_F32
2603 { 1329, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1329 = LT_F16x8_S
2604 { 1328, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1328 = LT_F16x8
2605 { 1327, 1, 0, 0, 0, 1, 1, 279, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1327 = LOOP_S
2606 { 1326, 1, 0, 0, 0, 1, 1, 279, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1326 = LOOP
2607 { 1325, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1325 = LOCAL_TEE_V128_S
2608 { 1324, 3, 1, 0, 0, 0, 1, 581, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1324 = LOCAL_TEE_V128
2609 { 1323, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1323 = LOCAL_TEE_I64_S
2610 { 1322, 3, 1, 0, 0, 0, 1, 578, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1322 = LOCAL_TEE_I64
2611 { 1321, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1321 = LOCAL_TEE_I32_S
2612 { 1320, 3, 1, 0, 0, 0, 1, 575, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1320 = LOCAL_TEE_I32
2613 { 1319, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1319 = LOCAL_TEE_FUNCREF_S
2614 { 1318, 3, 1, 0, 0, 0, 1, 572, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1318 = LOCAL_TEE_FUNCREF
2615 { 1317, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1317 = LOCAL_TEE_F64_S
2616 { 1316, 3, 1, 0, 0, 0, 1, 569, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1316 = LOCAL_TEE_F64
2617 { 1315, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1315 = LOCAL_TEE_F32_S
2618 { 1314, 3, 1, 0, 0, 0, 1, 566, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1314 = LOCAL_TEE_F32
2619 { 1313, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1313 = LOCAL_TEE_EXTERNREF_S
2620 { 1312, 3, 1, 0, 0, 0, 1, 563, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1312 = LOCAL_TEE_EXTERNREF
2621 { 1311, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1311 = LOCAL_TEE_EXNREF_S
2622 { 1310, 3, 1, 0, 0, 0, 1, 560, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1310 = LOCAL_TEE_EXNREF
2623 { 1309, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1309 = LOCAL_SET_V128_S
2624 { 1308, 2, 0, 0, 0, 0, 1, 558, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1308 = LOCAL_SET_V128
2625 { 1307, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1307 = LOCAL_SET_I64_S
2626 { 1306, 2, 0, 0, 0, 0, 1, 556, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1306 = LOCAL_SET_I64
2627 { 1305, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1305 = LOCAL_SET_I32_S
2628 { 1304, 2, 0, 0, 0, 0, 1, 554, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1304 = LOCAL_SET_I32
2629 { 1303, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1303 = LOCAL_SET_FUNCREF_S
2630 { 1302, 2, 0, 0, 0, 0, 1, 552, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1302 = LOCAL_SET_FUNCREF
2631 { 1301, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1301 = LOCAL_SET_F64_S
2632 { 1300, 2, 0, 0, 0, 0, 1, 550, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1300 = LOCAL_SET_F64
2633 { 1299, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1299 = LOCAL_SET_F32_S
2634 { 1298, 2, 0, 0, 0, 0, 1, 548, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1298 = LOCAL_SET_F32
2635 { 1297, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1297 = LOCAL_SET_EXTERNREF_S
2636 { 1296, 2, 0, 0, 0, 0, 1, 546, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1296 = LOCAL_SET_EXTERNREF
2637 { 1295, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1295 = LOCAL_SET_EXNREF_S
2638 { 1294, 2, 0, 0, 0, 0, 1, 544, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1294 = LOCAL_SET_EXNREF
2639 { 1293, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1293 = LOCAL_GET_V128_S
2640 { 1292, 2, 1, 0, 0, 0, 1, 542, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1292 = LOCAL_GET_V128
2641 { 1291, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1291 = LOCAL_GET_I64_S
2642 { 1290, 2, 1, 0, 0, 0, 1, 540, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1290 = LOCAL_GET_I64
2643 { 1289, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1289 = LOCAL_GET_I32_S
2644 { 1288, 2, 1, 0, 0, 0, 1, 538, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1288 = LOCAL_GET_I32
2645 { 1287, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1287 = LOCAL_GET_FUNCREF_S
2646 { 1286, 2, 1, 0, 0, 0, 1, 536, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1286 = LOCAL_GET_FUNCREF
2647 { 1285, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1285 = LOCAL_GET_F64_S
2648 { 1284, 2, 1, 0, 0, 0, 1, 534, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1284 = LOCAL_GET_F64
2649 { 1283, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1283 = LOCAL_GET_F32_S
2650 { 1282, 2, 1, 0, 0, 0, 1, 532, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1282 = LOCAL_GET_F32
2651 { 1281, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1281 = LOCAL_GET_EXTERNREF_S
2652 { 1280, 2, 1, 0, 0, 0, 1, 530, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1280 = LOCAL_GET_EXTERNREF
2653 { 1279, 1, 0, 0, 0, 0, 1, 529, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1279 = LOCAL_GET_EXNREF_S
2654 { 1278, 2, 1, 0, 0, 0, 1, 527, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1278 = LOCAL_GET_EXNREF
2655 { 1277, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1277 = LOAD_ZERO_64_A64_S
2656 { 1276, 4, 1, 0, 0, 0, 1, 489, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1276 = LOAD_ZERO_64_A64
2657 { 1275, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1275 = LOAD_ZERO_64_A32_S
2658 { 1274, 4, 1, 0, 0, 0, 1, 485, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1274 = LOAD_ZERO_64_A32
2659 { 1273, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1273 = LOAD_ZERO_32_A64_S
2660 { 1272, 4, 1, 0, 0, 0, 1, 489, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1272 = LOAD_ZERO_32_A64
2661 { 1271, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1271 = LOAD_ZERO_32_A32_S
2662 { 1270, 4, 1, 0, 0, 0, 1, 485, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1270 = LOAD_ZERO_32_A32
2663 { 1269, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1269 = LOAD_V128_A64_S
2664 { 1268, 4, 1, 0, 0, 0, 1, 489, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1268 = LOAD_V128_A64
2665 { 1267, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1267 = LOAD_V128_A32_S
2666 { 1266, 4, 1, 0, 0, 0, 1, 485, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1266 = LOAD_V128_A32
2667 { 1265, 3, 0, 0, 0, 0, 1, 524, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1265 = LOAD_LANE_8_A64_S
2668 { 1264, 6, 1, 0, 0, 0, 1, 518, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1264 = LOAD_LANE_8_A64
2669 { 1263, 3, 0, 0, 0, 0, 1, 515, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1263 = LOAD_LANE_8_A32_S
2670 { 1262, 6, 1, 0, 0, 0, 1, 509, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1262 = LOAD_LANE_8_A32
2671 { 1261, 3, 0, 0, 0, 0, 1, 524, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1261 = LOAD_LANE_64_A64_S
2672 { 1260, 6, 1, 0, 0, 0, 1, 518, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1260 = LOAD_LANE_64_A64
2673 { 1259, 3, 0, 0, 0, 0, 1, 515, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1259 = LOAD_LANE_64_A32_S
2674 { 1258, 6, 1, 0, 0, 0, 1, 509, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1258 = LOAD_LANE_64_A32
2675 { 1257, 3, 0, 0, 0, 0, 1, 524, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1257 = LOAD_LANE_32_A64_S
2676 { 1256, 6, 1, 0, 0, 0, 1, 518, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1256 = LOAD_LANE_32_A64
2677 { 1255, 3, 0, 0, 0, 0, 1, 515, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1255 = LOAD_LANE_32_A32_S
2678 { 1254, 6, 1, 0, 0, 0, 1, 509, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1254 = LOAD_LANE_32_A32
2679 { 1253, 3, 0, 0, 0, 0, 1, 524, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1253 = LOAD_LANE_16_A64_S
2680 { 1252, 6, 1, 0, 0, 0, 1, 518, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1252 = LOAD_LANE_16_A64
2681 { 1251, 3, 0, 0, 0, 0, 1, 515, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1251 = LOAD_LANE_16_A32_S
2682 { 1250, 6, 1, 0, 0, 0, 1, 509, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1250 = LOAD_LANE_16_A32
2683 { 1249, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1249 = LOAD_I64_A64_S
2684 { 1248, 4, 1, 0, 0, 0, 1, 211, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1248 = LOAD_I64_A64
2685 { 1247, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1247 = LOAD_I64_A32_S
2686 { 1246, 4, 1, 0, 0, 0, 1, 207, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1246 = LOAD_I64_A32
2687 { 1245, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1245 = LOAD_I32_A64_S
2688 { 1244, 4, 1, 0, 0, 0, 1, 201, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1244 = LOAD_I32_A64
2689 { 1243, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1243 = LOAD_I32_A32_S
2690 { 1242, 4, 1, 0, 0, 0, 1, 195, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1242 = LOAD_I32_A32
2691 { 1241, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1241 = LOAD_F64_A64_S
2692 { 1240, 4, 1, 0, 0, 0, 1, 505, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1240 = LOAD_F64_A64
2693 { 1239, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1239 = LOAD_F64_A32_S
2694 { 1238, 4, 1, 0, 0, 0, 1, 501, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1238 = LOAD_F64_A32
2695 { 1237, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1237 = LOAD_F32_A64_S
2696 { 1236, 4, 1, 0, 0, 0, 1, 497, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1236 = LOAD_F32_A64
2697 { 1235, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1235 = LOAD_F32_A32_S
2698 { 1234, 4, 1, 0, 0, 0, 1, 493, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1234 = LOAD_F32_A32
2699 { 1233, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1233 = LOAD_F16_F32_A64_S
2700 { 1232, 4, 1, 0, 0, 0, 1, 497, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1232 = LOAD_F16_F32_A64
2701 { 1231, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1231 = LOAD_F16_F32_A32_S
2702 { 1230, 4, 1, 0, 0, 0, 1, 493, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1230 = LOAD_F16_F32_A32
2703 { 1229, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1229 = LOAD_EXTEND_U_I64x2_A64_S
2704 { 1228, 4, 1, 0, 0, 0, 1, 489, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1228 = LOAD_EXTEND_U_I64x2_A64
2705 { 1227, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1227 = LOAD_EXTEND_U_I64x2_A32_S
2706 { 1226, 4, 1, 0, 0, 0, 1, 485, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1226 = LOAD_EXTEND_U_I64x2_A32
2707 { 1225, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1225 = LOAD_EXTEND_U_I32x4_A64_S
2708 { 1224, 4, 1, 0, 0, 0, 1, 489, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1224 = LOAD_EXTEND_U_I32x4_A64
2709 { 1223, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1223 = LOAD_EXTEND_U_I32x4_A32_S
2710 { 1222, 4, 1, 0, 0, 0, 1, 485, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1222 = LOAD_EXTEND_U_I32x4_A32
2711 { 1221, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1221 = LOAD_EXTEND_U_I16x8_A64_S
2712 { 1220, 4, 1, 0, 0, 0, 1, 489, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1220 = LOAD_EXTEND_U_I16x8_A64
2713 { 1219, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1219 = LOAD_EXTEND_U_I16x8_A32_S
2714 { 1218, 4, 1, 0, 0, 0, 1, 485, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1218 = LOAD_EXTEND_U_I16x8_A32
2715 { 1217, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1217 = LOAD_EXTEND_S_I64x2_A64_S
2716 { 1216, 4, 1, 0, 0, 0, 1, 489, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1216 = LOAD_EXTEND_S_I64x2_A64
2717 { 1215, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1215 = LOAD_EXTEND_S_I64x2_A32_S
2718 { 1214, 4, 1, 0, 0, 0, 1, 485, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1214 = LOAD_EXTEND_S_I64x2_A32
2719 { 1213, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1213 = LOAD_EXTEND_S_I32x4_A64_S
2720 { 1212, 4, 1, 0, 0, 0, 1, 489, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1212 = LOAD_EXTEND_S_I32x4_A64
2721 { 1211, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1211 = LOAD_EXTEND_S_I32x4_A32_S
2722 { 1210, 4, 1, 0, 0, 0, 1, 485, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1210 = LOAD_EXTEND_S_I32x4_A32
2723 { 1209, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1209 = LOAD_EXTEND_S_I16x8_A64_S
2724 { 1208, 4, 1, 0, 0, 0, 1, 489, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1208 = LOAD_EXTEND_S_I16x8_A64
2725 { 1207, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1207 = LOAD_EXTEND_S_I16x8_A32_S
2726 { 1206, 4, 1, 0, 0, 0, 1, 485, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1206 = LOAD_EXTEND_S_I16x8_A32
2727 { 1205, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1205 = LOAD8_U_I64_A64_S
2728 { 1204, 4, 1, 0, 0, 0, 1, 211, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1204 = LOAD8_U_I64_A64
2729 { 1203, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1203 = LOAD8_U_I64_A32_S
2730 { 1202, 4, 1, 0, 0, 0, 1, 207, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1202 = LOAD8_U_I64_A32
2731 { 1201, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1201 = LOAD8_U_I32_A64_S
2732 { 1200, 4, 1, 0, 0, 0, 1, 201, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1200 = LOAD8_U_I32_A64
2733 { 1199, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1199 = LOAD8_U_I32_A32_S
2734 { 1198, 4, 1, 0, 0, 0, 1, 195, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1198 = LOAD8_U_I32_A32
2735 { 1197, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1197 = LOAD8_S_I64_A64_S
2736 { 1196, 4, 1, 0, 0, 0, 1, 211, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1196 = LOAD8_S_I64_A64
2737 { 1195, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1195 = LOAD8_S_I64_A32_S
2738 { 1194, 4, 1, 0, 0, 0, 1, 207, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1194 = LOAD8_S_I64_A32
2739 { 1193, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1193 = LOAD8_S_I32_A64_S
2740 { 1192, 4, 1, 0, 0, 0, 1, 201, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1192 = LOAD8_S_I32_A64
2741 { 1191, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1191 = LOAD8_S_I32_A32_S
2742 { 1190, 4, 1, 0, 0, 0, 1, 195, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1190 = LOAD8_S_I32_A32
2743 { 1189, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1189 = LOAD8_SPLAT_A64_S
2744 { 1188, 4, 1, 0, 0, 0, 1, 489, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1188 = LOAD8_SPLAT_A64
2745 { 1187, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1187 = LOAD8_SPLAT_A32_S
2746 { 1186, 4, 1, 0, 0, 0, 1, 485, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1186 = LOAD8_SPLAT_A32
2747 { 1185, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1185 = LOAD64_SPLAT_A64_S
2748 { 1184, 4, 1, 0, 0, 0, 1, 489, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1184 = LOAD64_SPLAT_A64
2749 { 1183, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1183 = LOAD64_SPLAT_A32_S
2750 { 1182, 4, 1, 0, 0, 0, 1, 485, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1182 = LOAD64_SPLAT_A32
2751 { 1181, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1181 = LOAD32_U_I64_A64_S
2752 { 1180, 4, 1, 0, 0, 0, 1, 211, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1180 = LOAD32_U_I64_A64
2753 { 1179, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1179 = LOAD32_U_I64_A32_S
2754 { 1178, 4, 1, 0, 0, 0, 1, 207, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1178 = LOAD32_U_I64_A32
2755 { 1177, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1177 = LOAD32_S_I64_A64_S
2756 { 1176, 4, 1, 0, 0, 0, 1, 211, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1176 = LOAD32_S_I64_A64
2757 { 1175, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1175 = LOAD32_S_I64_A32_S
2758 { 1174, 4, 1, 0, 0, 0, 1, 207, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1174 = LOAD32_S_I64_A32
2759 { 1173, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1173 = LOAD32_SPLAT_A64_S
2760 { 1172, 4, 1, 0, 0, 0, 1, 489, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1172 = LOAD32_SPLAT_A64
2761 { 1171, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1171 = LOAD32_SPLAT_A32_S
2762 { 1170, 4, 1, 0, 0, 0, 1, 485, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1170 = LOAD32_SPLAT_A32
2763 { 1169, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1169 = LOAD16_U_I64_A64_S
2764 { 1168, 4, 1, 0, 0, 0, 1, 211, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1168 = LOAD16_U_I64_A64
2765 { 1167, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1167 = LOAD16_U_I64_A32_S
2766 { 1166, 4, 1, 0, 0, 0, 1, 207, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1166 = LOAD16_U_I64_A32
2767 { 1165, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1165 = LOAD16_U_I32_A64_S
2768 { 1164, 4, 1, 0, 0, 0, 1, 201, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1164 = LOAD16_U_I32_A64
2769 { 1163, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1163 = LOAD16_U_I32_A32_S
2770 { 1162, 4, 1, 0, 0, 0, 1, 195, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1162 = LOAD16_U_I32_A32
2771 { 1161, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1161 = LOAD16_S_I64_A64_S
2772 { 1160, 4, 1, 0, 0, 0, 1, 211, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1160 = LOAD16_S_I64_A64
2773 { 1159, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1159 = LOAD16_S_I64_A32_S
2774 { 1158, 4, 1, 0, 0, 0, 1, 207, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1158 = LOAD16_S_I64_A32
2775 { 1157, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1157 = LOAD16_S_I32_A64_S
2776 { 1156, 4, 1, 0, 0, 0, 1, 201, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1156 = LOAD16_S_I32_A64
2777 { 1155, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1155 = LOAD16_S_I32_A32_S
2778 { 1154, 4, 1, 0, 0, 0, 1, 195, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1154 = LOAD16_S_I32_A32
2779 { 1153, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1153 = LOAD16_SPLAT_A64_S
2780 { 1152, 4, 1, 0, 0, 0, 1, 489, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1152 = LOAD16_SPLAT_A64
2781 { 1151, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1151 = LOAD16_SPLAT_A32_S
2782 { 1150, 4, 1, 0, 0, 0, 1, 485, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1150 = LOAD16_SPLAT_A32
2783 { 1149, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1149 = LE_U_I8x16_S
2784 { 1148, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1148 = LE_U_I8x16
2785 { 1147, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1147 = LE_U_I64_S
2786 { 1146, 3, 1, 0, 0, 0, 1, 402, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1146 = LE_U_I64
2787 { 1145, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1145 = LE_U_I32x4_S
2788 { 1144, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1144 = LE_U_I32x4
2789 { 1143, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1143 = LE_U_I32_S
2790 { 1142, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1142 = LE_U_I32
2791 { 1141, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1141 = LE_U_I16x8_S
2792 { 1140, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1140 = LE_U_I16x8
2793 { 1139, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1139 = LE_S_I8x16_S
2794 { 1138, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1138 = LE_S_I8x16
2795 { 1137, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1137 = LE_S_I64x2_S
2796 { 1136, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1136 = LE_S_I64x2
2797 { 1135, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1135 = LE_S_I64_S
2798 { 1134, 3, 1, 0, 0, 0, 1, 402, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1134 = LE_S_I64
2799 { 1133, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1133 = LE_S_I32x4_S
2800 { 1132, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1132 = LE_S_I32x4
2801 { 1131, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1131 = LE_S_I32_S
2802 { 1130, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1130 = LE_S_I32
2803 { 1129, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1129 = LE_S_I16x8_S
2804 { 1128, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1128 = LE_S_I16x8
2805 { 1127, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1127 = LE_F64x2_S
2806 { 1126, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1126 = LE_F64x2
2807 { 1125, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1125 = LE_F64_S
2808 { 1124, 3, 1, 0, 0, 0, 1, 399, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1124 = LE_F64
2809 { 1123, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1123 = LE_F32x4_S
2810 { 1122, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1122 = LE_F32x4
2811 { 1121, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1121 = LE_F32_S
2812 { 1120, 3, 1, 0, 0, 0, 1, 396, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1120 = LE_F32
2813 { 1119, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1119 = LE_F16x8_S
2814 { 1118, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1118 = LE_F16x8
2815 { 1117, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1117 = LANESELECT_I8x16_S
2816 { 1116, 4, 1, 0, 0, 0, 1, 275, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1116 = LANESELECT_I8x16
2817 { 1115, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1115 = LANESELECT_I64x2_S
2818 { 1114, 4, 1, 0, 0, 0, 1, 275, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1114 = LANESELECT_I64x2
2819 { 1113, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1113 = LANESELECT_I32x4_S
2820 { 1112, 4, 1, 0, 0, 0, 1, 275, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1112 = LANESELECT_I32x4
2821 { 1111, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1111 = LANESELECT_I16x8_S
2822 { 1110, 4, 1, 0, 0, 0, 1, 275, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1110 = LANESELECT_I16x8
2823 { 1109, 1, 0, 0, 0, 1, 1, 279, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1109 = IF_S
2824 { 1108, 2, 0, 0, 0, 1, 1, 483, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1108 = IF
2825 { 1107, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1107 = I64_TRUNC_U_SAT_F64_S
2826 { 1106, 2, 1, 0, 0, 0, 1, 436, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1106 = I64_TRUNC_U_SAT_F64
2827 { 1105, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1105 = I64_TRUNC_U_SAT_F32_S
2828 { 1104, 2, 1, 0, 0, 0, 1, 434, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1104 = I64_TRUNC_U_SAT_F32
2829 { 1103, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1103 = I64_TRUNC_U_F64_S
2830 { 1102, 2, 1, 0, 0, 0, 1, 436, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1102 = I64_TRUNC_U_F64
2831 { 1101, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1101 = I64_TRUNC_U_F32_S
2832 { 1100, 2, 1, 0, 0, 0, 1, 434, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1100 = I64_TRUNC_U_F32
2833 { 1099, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1099 = I64_TRUNC_S_SAT_F64_S
2834 { 1098, 2, 1, 0, 0, 0, 1, 436, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1098 = I64_TRUNC_S_SAT_F64
2835 { 1097, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1097 = I64_TRUNC_S_SAT_F32_S
2836 { 1096, 2, 1, 0, 0, 0, 1, 434, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1096 = I64_TRUNC_S_SAT_F32
2837 { 1095, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1095 = I64_TRUNC_S_F64_S
2838 { 1094, 2, 1, 0, 0, 0, 1, 436, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1094 = I64_TRUNC_S_F64
2839 { 1093, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1093 = I64_TRUNC_S_F32_S
2840 { 1092, 2, 1, 0, 0, 0, 1, 434, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1092 = I64_TRUNC_S_F32
2841 { 1091, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1091 = I64_SUB128_S
2842 { 1090, 6, 2, 0, 0, 0, 1, 471, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1090 = I64_SUB128
2843 { 1089, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1089 = I64_REINTERPRET_F64_S
2844 { 1088, 2, 1, 0, 0, 0, 1, 436, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1088 = I64_REINTERPRET_F64
2845 { 1087, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1087 = I64_MUL_WIDE_U_S
2846 { 1086, 4, 2, 0, 0, 0, 1, 479, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1086 = I64_MUL_WIDE_U
2847 { 1085, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1085 = I64_MUL_WIDE_S_S
2848 { 1084, 4, 2, 0, 0, 0, 1, 479, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1084 = I64_MUL_WIDE_S
2849 { 1083, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1083 = I64_EXTEND_U_I32_S
2850 { 1082, 2, 1, 0, 0, 0, 1, 477, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1082 = I64_EXTEND_U_I32
2851 { 1081, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1081 = I64_EXTEND_S_I32_S
2852 { 1080, 2, 1, 0, 0, 0, 1, 477, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1080 = I64_EXTEND_S_I32
2853 { 1079, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1079 = I64_EXTEND8_S_I64_S
2854 { 1078, 2, 1, 0, 0, 0, 1, 291, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1078 = I64_EXTEND8_S_I64
2855 { 1077, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1077 = I64_EXTEND32_S_I64_S
2856 { 1076, 2, 1, 0, 0, 0, 1, 291, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1076 = I64_EXTEND32_S_I64
2857 { 1075, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1075 = I64_EXTEND16_S_I64_S
2858 { 1074, 2, 1, 0, 0, 0, 1, 291, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1074 = I64_EXTEND16_S_I64
2859 { 1073, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1073 = I64_ADD128_S
2860 { 1072, 6, 2, 0, 0, 0, 1, 471, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1072 = I64_ADD128
2861 { 1071, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1071 = I32_WRAP_I64_S
2862 { 1070, 2, 1, 0, 0, 0, 1, 394, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1070 = I32_WRAP_I64
2863 { 1069, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1069 = I32_TRUNC_U_SAT_F64_S
2864 { 1068, 2, 1, 0, 0, 0, 1, 432, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1068 = I32_TRUNC_U_SAT_F64
2865 { 1067, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1067 = I32_TRUNC_U_SAT_F32_S
2866 { 1066, 2, 1, 0, 0, 0, 1, 430, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1066 = I32_TRUNC_U_SAT_F32
2867 { 1065, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1065 = I32_TRUNC_U_F64_S
2868 { 1064, 2, 1, 0, 0, 0, 1, 432, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1064 = I32_TRUNC_U_F64
2869 { 1063, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1063 = I32_TRUNC_U_F32_S
2870 { 1062, 2, 1, 0, 0, 0, 1, 430, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1062 = I32_TRUNC_U_F32
2871 { 1061, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1061 = I32_TRUNC_S_SAT_F64_S
2872 { 1060, 2, 1, 0, 0, 0, 1, 432, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1060 = I32_TRUNC_S_SAT_F64
2873 { 1059, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1059 = I32_TRUNC_S_SAT_F32_S
2874 { 1058, 2, 1, 0, 0, 0, 1, 430, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1058 = I32_TRUNC_S_SAT_F32
2875 { 1057, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1057 = I32_TRUNC_S_F64_S
2876 { 1056, 2, 1, 0, 0, 0, 1, 432, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1056 = I32_TRUNC_S_F64
2877 { 1055, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1055 = I32_TRUNC_S_F32_S
2878 { 1054, 2, 1, 0, 0, 0, 1, 430, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1054 = I32_TRUNC_S_F32
2879 { 1053, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1053 = I32_REINTERPRET_F32_S
2880 { 1052, 2, 1, 0, 0, 0, 1, 430, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1052 = I32_REINTERPRET_F32
2881 { 1051, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1051 = I32_EXTEND8_S_I32_S
2882 { 1050, 2, 1, 0, 0, 0, 1, 289, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1050 = I32_EXTEND8_S_I32
2883 { 1049, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1049 = I32_EXTEND16_S_I32_S
2884 { 1048, 2, 1, 0, 0, 0, 1, 289, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1048 = I32_EXTEND16_S_I32
2885 { 1047, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1047 = GT_U_I8x16_S
2886 { 1046, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1046 = GT_U_I8x16
2887 { 1045, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1045 = GT_U_I64_S
2888 { 1044, 3, 1, 0, 0, 0, 1, 402, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1044 = GT_U_I64
2889 { 1043, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1043 = GT_U_I32x4_S
2890 { 1042, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1042 = GT_U_I32x4
2891 { 1041, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1041 = GT_U_I32_S
2892 { 1040, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1040 = GT_U_I32
2893 { 1039, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1039 = GT_U_I16x8_S
2894 { 1038, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1038 = GT_U_I16x8
2895 { 1037, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1037 = GT_S_I8x16_S
2896 { 1036, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1036 = GT_S_I8x16
2897 { 1035, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1035 = GT_S_I64x2_S
2898 { 1034, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1034 = GT_S_I64x2
2899 { 1033, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1033 = GT_S_I64_S
2900 { 1032, 3, 1, 0, 0, 0, 1, 402, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1032 = GT_S_I64
2901 { 1031, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1031 = GT_S_I32x4_S
2902 { 1030, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1030 = GT_S_I32x4
2903 { 1029, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1029 = GT_S_I32_S
2904 { 1028, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1028 = GT_S_I32
2905 { 1027, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1027 = GT_S_I16x8_S
2906 { 1026, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1026 = GT_S_I16x8
2907 { 1025, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1025 = GT_F64x2_S
2908 { 1024, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1024 = GT_F64x2
2909 { 1023, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1023 = GT_F64_S
2910 { 1022, 3, 1, 0, 0, 0, 1, 399, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1022 = GT_F64
2911 { 1021, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1021 = GT_F32x4_S
2912 { 1020, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1020 = GT_F32x4
2913 { 1019, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1019 = GT_F32_S
2914 { 1018, 3, 1, 0, 0, 0, 1, 396, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1018 = GT_F32
2915 { 1017, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1017 = GT_F16x8_S
2916 { 1016, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1016 = GT_F16x8
2917 { 1015, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1015 = GLOBAL_SET_V128_S
2918 { 1014, 2, 0, 0, 0, 0, 1, 469, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1014 = GLOBAL_SET_V128
2919 { 1013, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1013 = GLOBAL_SET_I64_S
2920 { 1012, 2, 0, 0, 0, 0, 1, 467, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1012 = GLOBAL_SET_I64
2921 { 1011, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1011 = GLOBAL_SET_I32_S
2922 { 1010, 2, 0, 0, 0, 0, 1, 465, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1010 = GLOBAL_SET_I32
2923 { 1009, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1009 = GLOBAL_SET_FUNCREF_S
2924 { 1008, 2, 0, 0, 0, 0, 1, 463, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1008 = GLOBAL_SET_FUNCREF
2925 { 1007, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1007 = GLOBAL_SET_F64_S
2926 { 1006, 2, 0, 0, 0, 0, 1, 461, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1006 = GLOBAL_SET_F64
2927 { 1005, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1005 = GLOBAL_SET_F32_S
2928 { 1004, 2, 0, 0, 0, 0, 1, 459, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1004 = GLOBAL_SET_F32
2929 { 1003, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1003 = GLOBAL_SET_EXTERNREF_S
2930 { 1002, 2, 0, 0, 0, 0, 1, 457, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1002 = GLOBAL_SET_EXTERNREF
2931 { 1001, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1001 = GLOBAL_SET_EXNREF_S
2932 { 1000, 2, 0, 0, 0, 0, 1, 455, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1000 = GLOBAL_SET_EXNREF
2933 { 999, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #999 = GLOBAL_GET_V128_S
2934 { 998, 2, 1, 0, 0, 0, 1, 453, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #998 = GLOBAL_GET_V128
2935 { 997, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #997 = GLOBAL_GET_I64_S
2936 { 996, 2, 1, 0, 0, 0, 1, 451, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #996 = GLOBAL_GET_I64
2937 { 995, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #995 = GLOBAL_GET_I32_S
2938 { 994, 2, 1, 0, 0, 0, 1, 449, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #994 = GLOBAL_GET_I32
2939 { 993, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #993 = GLOBAL_GET_FUNCREF_S
2940 { 992, 2, 1, 0, 0, 0, 1, 447, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #992 = GLOBAL_GET_FUNCREF
2941 { 991, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #991 = GLOBAL_GET_F64_S
2942 { 990, 2, 1, 0, 0, 0, 1, 445, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #990 = GLOBAL_GET_F64
2943 { 989, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #989 = GLOBAL_GET_F32_S
2944 { 988, 2, 1, 0, 0, 0, 1, 443, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #988 = GLOBAL_GET_F32
2945 { 987, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #987 = GLOBAL_GET_EXTERNREF_S
2946 { 986, 2, 1, 0, 0, 0, 1, 441, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #986 = GLOBAL_GET_EXTERNREF
2947 { 985, 1, 0, 0, 0, 0, 1, 440, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #985 = GLOBAL_GET_EXNREF_S
2948 { 984, 2, 1, 0, 0, 0, 1, 438, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #984 = GLOBAL_GET_EXNREF
2949 { 983, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #983 = GE_U_I8x16_S
2950 { 982, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #982 = GE_U_I8x16
2951 { 981, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #981 = GE_U_I64_S
2952 { 980, 3, 1, 0, 0, 0, 1, 402, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #980 = GE_U_I64
2953 { 979, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #979 = GE_U_I32x4_S
2954 { 978, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #978 = GE_U_I32x4
2955 { 977, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #977 = GE_U_I32_S
2956 { 976, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #976 = GE_U_I32
2957 { 975, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #975 = GE_U_I16x8_S
2958 { 974, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #974 = GE_U_I16x8
2959 { 973, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #973 = GE_S_I8x16_S
2960 { 972, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #972 = GE_S_I8x16
2961 { 971, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #971 = GE_S_I64x2_S
2962 { 970, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #970 = GE_S_I64x2
2963 { 969, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #969 = GE_S_I64_S
2964 { 968, 3, 1, 0, 0, 0, 1, 402, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #968 = GE_S_I64
2965 { 967, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #967 = GE_S_I32x4_S
2966 { 966, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #966 = GE_S_I32x4
2967 { 965, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #965 = GE_S_I32_S
2968 { 964, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #964 = GE_S_I32
2969 { 963, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #963 = GE_S_I16x8_S
2970 { 962, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #962 = GE_S_I16x8
2971 { 961, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #961 = GE_F64x2_S
2972 { 960, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #960 = GE_F64x2
2973 { 959, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #959 = GE_F64_S
2974 { 958, 3, 1, 0, 0, 0, 1, 399, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #958 = GE_F64
2975 { 957, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #957 = GE_F32x4_S
2976 { 956, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #956 = GE_F32x4
2977 { 955, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #955 = GE_F32_S
2978 { 954, 3, 1, 0, 0, 0, 1, 396, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #954 = GE_F32
2979 { 953, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #953 = GE_F16x8_S
2980 { 952, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #952 = GE_F16x8
2981 { 951, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #951 = FP_TO_UINT_I64_F64_S
2982 { 950, 2, 1, 0, 0, 0, 1, 436, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #950 = FP_TO_UINT_I64_F64
2983 { 949, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #949 = FP_TO_UINT_I64_F32_S
2984 { 948, 2, 1, 0, 0, 0, 1, 434, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #948 = FP_TO_UINT_I64_F32
2985 { 947, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #947 = FP_TO_UINT_I32_F64_S
2986 { 946, 2, 1, 0, 0, 0, 1, 432, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #946 = FP_TO_UINT_I32_F64
2987 { 945, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #945 = FP_TO_UINT_I32_F32_S
2988 { 944, 2, 1, 0, 0, 0, 1, 430, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #944 = FP_TO_UINT_I32_F32
2989 { 943, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #943 = FP_TO_SINT_I64_F64_S
2990 { 942, 2, 1, 0, 0, 0, 1, 436, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #942 = FP_TO_SINT_I64_F64
2991 { 941, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #941 = FP_TO_SINT_I64_F32_S
2992 { 940, 2, 1, 0, 0, 0, 1, 434, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #940 = FP_TO_SINT_I64_F32
2993 { 939, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #939 = FP_TO_SINT_I32_F64_S
2994 { 938, 2, 1, 0, 0, 0, 1, 432, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #938 = FP_TO_SINT_I32_F64
2995 { 937, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #937 = FP_TO_SINT_I32_F32_S
2996 { 936, 2, 1, 0, 0, 0, 1, 430, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #936 = FP_TO_SINT_I32_F32
2997 { 935, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #935 = FLOOR_F64x2_S
2998 { 934, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #934 = FLOOR_F64x2
2999 { 933, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #933 = FLOOR_F64_S
3000 { 932, 2, 1, 0, 0, 0, 1, 160, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #932 = FLOOR_F64
3001 { 931, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #931 = FLOOR_F32x4_S
3002 { 930, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #930 = FLOOR_F32x4
3003 { 929, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #929 = FLOOR_F32_S
3004 { 928, 2, 1, 0, 0, 0, 1, 158, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #928 = FLOOR_F32
3005 { 927, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #927 = FLOOR_F16x8_S
3006 { 926, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #926 = FLOOR_F16x8
3007 { 925, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #925 = FALLTHROUGH_RETURN_S
3008 { 924, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #924 = FALLTHROUGH_RETURN
3009 { 923, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #923 = F64_REINTERPRET_I64_S
3010 { 922, 2, 1, 0, 0, 0, 1, 426, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #922 = F64_REINTERPRET_I64
3011 { 921, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #921 = F64_PROMOTE_F32_S
3012 { 920, 2, 1, 0, 0, 0, 1, 428, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #920 = F64_PROMOTE_F32
3013 { 919, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #919 = F64_CONVERT_U_I64_S
3014 { 918, 2, 1, 0, 0, 0, 1, 426, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #918 = F64_CONVERT_U_I64
3015 { 917, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #917 = F64_CONVERT_U_I32_S
3016 { 916, 2, 1, 0, 0, 0, 1, 424, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #916 = F64_CONVERT_U_I32
3017 { 915, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #915 = F64_CONVERT_S_I64_S
3018 { 914, 2, 1, 0, 0, 0, 1, 426, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #914 = F64_CONVERT_S_I64
3019 { 913, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #913 = F64_CONVERT_S_I32_S
3020 { 912, 2, 1, 0, 0, 0, 1, 424, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #912 = F64_CONVERT_S_I32
3021 { 911, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #911 = F32_REINTERPRET_I32_S
3022 { 910, 2, 1, 0, 0, 0, 1, 418, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #910 = F32_REINTERPRET_I32
3023 { 909, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #909 = F32_DEMOTE_F64_S
3024 { 908, 2, 1, 0, 0, 0, 1, 422, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #908 = F32_DEMOTE_F64
3025 { 907, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #907 = F32_CONVERT_U_I64_S
3026 { 906, 2, 1, 0, 0, 0, 1, 420, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #906 = F32_CONVERT_U_I64
3027 { 905, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #905 = F32_CONVERT_U_I32_S
3028 { 904, 2, 1, 0, 0, 0, 1, 418, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #904 = F32_CONVERT_U_I32
3029 { 903, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #903 = F32_CONVERT_S_I64_S
3030 { 902, 2, 1, 0, 0, 0, 1, 420, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #902 = F32_CONVERT_S_I64
3031 { 901, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #901 = F32_CONVERT_S_I32_S
3032 { 900, 2, 1, 0, 0, 0, 1, 418, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #900 = F32_CONVERT_S_I32
3033 { 899, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #899 = EXTRACT_LANE_I8x16_u_S
3034 { 898, 3, 1, 0, 0, 0, 1, 412, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #898 = EXTRACT_LANE_I8x16_u
3035 { 897, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #897 = EXTRACT_LANE_I8x16_s_S
3036 { 896, 3, 1, 0, 0, 0, 1, 412, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #896 = EXTRACT_LANE_I8x16_s
3037 { 895, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #895 = EXTRACT_LANE_I64x2_S
3038 { 894, 3, 1, 0, 0, 0, 1, 415, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #894 = EXTRACT_LANE_I64x2
3039 { 893, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #893 = EXTRACT_LANE_I32x4_S
3040 { 892, 3, 1, 0, 0, 0, 1, 412, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #892 = EXTRACT_LANE_I32x4
3041 { 891, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #891 = EXTRACT_LANE_I16x8_u_S
3042 { 890, 3, 1, 0, 0, 0, 1, 412, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #890 = EXTRACT_LANE_I16x8_u
3043 { 889, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #889 = EXTRACT_LANE_I16x8_s_S
3044 { 888, 3, 1, 0, 0, 0, 1, 412, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #888 = EXTRACT_LANE_I16x8_s
3045 { 887, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #887 = EXTRACT_LANE_F64x2_S
3046 { 886, 3, 1, 0, 0, 0, 1, 409, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #886 = EXTRACT_LANE_F64x2
3047 { 885, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #885 = EXTRACT_LANE_F32x4_S
3048 { 884, 3, 1, 0, 0, 0, 1, 405, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #884 = EXTRACT_LANE_F32x4
3049 { 883, 1, 0, 0, 0, 0, 1, 408, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #883 = EXTRACT_LANE_F16x8_S
3050 { 882, 3, 1, 0, 0, 0, 1, 405, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #882 = EXTRACT_LANE_F16x8
3051 { 881, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #881 = EXTMUL_LOW_U_I64x2_S
3052 { 880, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #880 = EXTMUL_LOW_U_I64x2
3053 { 879, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #879 = EXTMUL_LOW_U_I32x4_S
3054 { 878, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #878 = EXTMUL_LOW_U_I32x4
3055 { 877, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #877 = EXTMUL_LOW_U_I16x8_S
3056 { 876, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #876 = EXTMUL_LOW_U_I16x8
3057 { 875, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #875 = EXTMUL_LOW_S_I64x2_S
3058 { 874, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #874 = EXTMUL_LOW_S_I64x2
3059 { 873, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #873 = EXTMUL_LOW_S_I32x4_S
3060 { 872, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #872 = EXTMUL_LOW_S_I32x4
3061 { 871, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #871 = EXTMUL_LOW_S_I16x8_S
3062 { 870, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #870 = EXTMUL_LOW_S_I16x8
3063 { 869, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #869 = EXTMUL_HIGH_U_I64x2_S
3064 { 868, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #868 = EXTMUL_HIGH_U_I64x2
3065 { 867, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #867 = EXTMUL_HIGH_U_I32x4_S
3066 { 866, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #866 = EXTMUL_HIGH_U_I32x4
3067 { 865, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #865 = EXTMUL_HIGH_U_I16x8_S
3068 { 864, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #864 = EXTMUL_HIGH_U_I16x8
3069 { 863, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #863 = EXTMUL_HIGH_S_I64x2_S
3070 { 862, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #862 = EXTMUL_HIGH_S_I64x2
3071 { 861, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #861 = EXTMUL_HIGH_S_I32x4_S
3072 { 860, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #860 = EXTMUL_HIGH_S_I32x4
3073 { 859, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #859 = EXTMUL_HIGH_S_I16x8_S
3074 { 858, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #858 = EXTMUL_HIGH_S_I16x8
3075 { 857, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #857 = EQ_I8x16_S
3076 { 856, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #856 = EQ_I8x16
3077 { 855, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #855 = EQ_I64x2_S
3078 { 854, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #854 = EQ_I64x2
3079 { 853, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #853 = EQ_I64_S
3080 { 852, 3, 1, 0, 0, 0, 1, 402, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #852 = EQ_I64
3081 { 851, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #851 = EQ_I32x4_S
3082 { 850, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #850 = EQ_I32x4
3083 { 849, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #849 = EQ_I32_S
3084 { 848, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #848 = EQ_I32
3085 { 847, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #847 = EQ_I16x8_S
3086 { 846, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #846 = EQ_I16x8
3087 { 845, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #845 = EQ_F64x2_S
3088 { 844, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #844 = EQ_F64x2
3089 { 843, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #843 = EQ_F64_S
3090 { 842, 3, 1, 0, 0, 0, 1, 399, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #842 = EQ_F64
3091 { 841, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #841 = EQ_F32x4_S
3092 { 840, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #840 = EQ_F32x4
3093 { 839, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #839 = EQ_F32_S
3094 { 838, 3, 1, 0, 0, 0, 1, 396, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #838 = EQ_F32
3095 { 837, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #837 = EQ_F16x8_S
3096 { 836, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #836 = EQ_F16x8
3097 { 835, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #835 = EQZ_I64_S
3098 { 834, 2, 1, 0, 0, 0, 1, 394, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #834 = EQZ_I64
3099 { 833, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #833 = EQZ_I32_S
3100 { 832, 2, 1, 0, 0, 0, 1, 289, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #832 = EQZ_I32
3101 { 831, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #831 = END_TRY_TABLE_S
3102 { 830, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #830 = END_TRY_TABLE
3103 { 829, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #829 = END_TRY_S
3104 { 828, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #828 = END_TRY
3105 { 827, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #827 = END_S
3106 { 826, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #826 = END_LOOP_S
3107 { 825, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #825 = END_LOOP
3108 { 824, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #824 = END_IF_S
3109 { 823, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #823 = END_IF
3110 { 822, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #822 = END_FUNCTION_S
3111 { 821, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #821 = END_FUNCTION
3112 { 820, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #820 = END_BLOCK_S
3113 { 819, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #819 = END_BLOCK
3114 { 818, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #818 = END
3115 { 817, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #817 = ELSE_S
3116 { 816, 0, 0, 0, 0, 1, 1, 1, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #816 = ELSE
3117 { 815, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #815 = DROP_V128_S
3118 { 814, 1, 0, 0, 0, 0, 1, 393, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #814 = DROP_V128
3119 { 813, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #813 = DROP_I64_S
3120 { 812, 1, 0, 0, 0, 0, 1, 284, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #812 = DROP_I64
3121 { 811, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #811 = DROP_I32_S
3122 { 810, 1, 0, 0, 0, 0, 1, 282, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #810 = DROP_I32
3123 { 809, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #809 = DROP_FUNCREF_S
3124 { 808, 1, 0, 0, 0, 0, 1, 392, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #808 = DROP_FUNCREF
3125 { 807, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #807 = DROP_F64_S
3126 { 806, 1, 0, 0, 0, 0, 1, 391, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #806 = DROP_F64
3127 { 805, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #805 = DROP_F32_S
3128 { 804, 1, 0, 0, 0, 0, 1, 390, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #804 = DROP_F32
3129 { 803, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #803 = DROP_EXTERNREF_S
3130 { 802, 1, 0, 0, 0, 0, 1, 389, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #802 = DROP_EXTERNREF
3131 { 801, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #801 = DROP_EXNREF_S
3132 { 800, 1, 0, 0, 0, 0, 1, 288, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #800 = DROP_EXNREF
3133 { 799, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #799 = DOT_S
3134 { 798, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #798 = DOT
3135 { 797, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #797 = DIV_U_I64_S
3136 { 796, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #796 = DIV_U_I64
3137 { 795, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #795 = DIV_U_I32_S
3138 { 794, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #794 = DIV_U_I32
3139 { 793, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #793 = DIV_S_I64_S
3140 { 792, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #792 = DIV_S_I64
3141 { 791, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #791 = DIV_S_I32_S
3142 { 790, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #790 = DIV_S_I32
3143 { 789, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #789 = DIV_F64x2_S
3144 { 788, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #788 = DIV_F64x2
3145 { 787, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #787 = DIV_F64_S
3146 { 786, 3, 1, 0, 0, 0, 1, 168, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #786 = DIV_F64
3147 { 785, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #785 = DIV_F32x4_S
3148 { 784, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #784 = DIV_F32x4
3149 { 783, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #783 = DIV_F32_S
3150 { 782, 3, 1, 0, 0, 0, 1, 165, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #782 = DIV_F32
3151 { 781, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #781 = DIV_F16x8_S
3152 { 780, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #780 = DIV_F16x8
3153 { 779, 1, 0, 0, 0, 0, 1, 155, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #779 = DELEGATE_S
3154 { 778, 1, 0, 0, 0, 0, 1, 155, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #778 = DELEGATE
3155 { 777, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #777 = DEBUG_UNREACHABLE_S
3156 { 776, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #776 = DEBUG_UNREACHABLE
3157 { 775, 1, 0, 0, 0, 0, 1, 301, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #775 = DATA_DROP_S
3158 { 774, 1, 0, 0, 0, 0, 1, 301, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #774 = DATA_DROP
3159 { 773, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #773 = CTZ_I64_S
3160 { 772, 2, 1, 0, 0, 0, 1, 291, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #772 = CTZ_I64
3161 { 771, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #771 = CTZ_I32_S
3162 { 770, 2, 1, 0, 0, 0, 1, 289, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #770 = CTZ_I32
3163 { 769, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #769 = COPY_V128_S
3164 { 768, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #768 = COPY_V128
3165 { 767, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #767 = COPY_I64_S
3166 { 766, 2, 1, 0, 0, 0, 1, 291, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #766 = COPY_I64
3167 { 765, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #765 = COPY_I32_S
3168 { 764, 2, 1, 0, 0, 0, 1, 289, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #764 = COPY_I32
3169 { 763, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #763 = COPY_FUNCREF_S
3170 { 762, 2, 1, 0, 0, 0, 1, 387, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #762 = COPY_FUNCREF
3171 { 761, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #761 = COPY_F64_S
3172 { 760, 2, 1, 0, 0, 0, 1, 160, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #760 = COPY_F64
3173 { 759, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #759 = COPY_F32_S
3174 { 758, 2, 1, 0, 0, 0, 1, 158, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #758 = COPY_F32
3175 { 757, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #757 = COPY_EXTERNREF_S
3176 { 756, 2, 1, 0, 0, 0, 1, 385, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #756 = COPY_EXTERNREF
3177 { 755, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #755 = COPY_EXNREF_S
3178 { 754, 2, 1, 0, 0, 0, 1, 383, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #754 = COPY_EXNREF
3179 { 753, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #753 = COPYSIGN_F64_S
3180 { 752, 3, 1, 0, 0, 0, 1, 168, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #752 = COPYSIGN_F64
3181 { 751, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #751 = COPYSIGN_F32_S
3182 { 750, 3, 1, 0, 0, 0, 1, 165, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #750 = COPYSIGN_F32
3183 { 749, 16, 0, 0, 0, 0, 1, 367, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #749 = CONST_V128_I8x16_S
3184 { 748, 17, 1, 0, 0, 0, 1, 350, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #748 = CONST_V128_I8x16
3185 { 747, 2, 0, 0, 0, 0, 1, 348, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #747 = CONST_V128_I64x2_S
3186 { 746, 3, 1, 0, 0, 0, 1, 345, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #746 = CONST_V128_I64x2
3187 { 745, 4, 0, 0, 0, 0, 1, 341, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #745 = CONST_V128_I32x4_S
3188 { 744, 5, 1, 0, 0, 0, 1, 336, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #744 = CONST_V128_I32x4
3189 { 743, 8, 0, 0, 0, 0, 1, 328, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #743 = CONST_V128_I16x8_S
3190 { 742, 9, 1, 0, 0, 0, 1, 319, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #742 = CONST_V128_I16x8
3191 { 741, 2, 0, 0, 0, 0, 1, 317, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #741 = CONST_V128_F64x2_S
3192 { 740, 3, 1, 0, 0, 0, 1, 314, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #740 = CONST_V128_F64x2
3193 { 739, 4, 0, 0, 0, 0, 1, 310, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #739 = CONST_V128_F32x4_S
3194 { 738, 5, 1, 0, 0, 0, 1, 305, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #738 = CONST_V128_F32x4
3195 { 737, 1, 0, 0, 0, 0, 1, 304, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #737 = CONST_I64_S
3196 { 736, 2, 1, 0, 0, 0, 1, 302, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #736 = CONST_I64
3197 { 735, 1, 0, 0, 0, 0, 1, 301, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #735 = CONST_I32_S
3198 { 734, 2, 1, 0, 0, 0, 1, 299, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #734 = CONST_I32
3199 { 733, 1, 0, 0, 0, 0, 1, 298, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #733 = CONST_F64_S
3200 { 732, 2, 1, 0, 0, 0, 1, 296, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #732 = CONST_F64
3201 { 731, 1, 0, 0, 0, 0, 1, 295, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #731 = CONST_F32_S
3202 { 730, 2, 1, 0, 0, 0, 1, 293, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #730 = CONST_F32
3203 { 729, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #729 = CLZ_I64_S
3204 { 728, 2, 1, 0, 0, 0, 1, 291, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #728 = CLZ_I64
3205 { 727, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #727 = CLZ_I32_S
3206 { 726, 2, 1, 0, 0, 0, 1, 289, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #726 = CLZ_I32
3207 { 725, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #725 = CEIL_F64x2_S
3208 { 724, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #724 = CEIL_F64x2
3209 { 723, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #723 = CEIL_F64_S
3210 { 722, 2, 1, 0, 0, 0, 1, 160, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #722 = CEIL_F64
3211 { 721, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #721 = CEIL_F32x4_S
3212 { 720, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #720 = CEIL_F32x4
3213 { 719, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #719 = CEIL_F32_S
3214 { 718, 2, 1, 0, 0, 0, 1, 158, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #718 = CEIL_F32
3215 { 717, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #717 = CEIL_F16x8_S
3216 { 716, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #716 = CEIL_F16x8
3217 { 715, 1, 0, 0, 0, 0, 1, 287, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #715 = CATCH_S
3218 { 714, 1, 0, 0, 0, 0, 1, 287, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #714 = CATCH_REF_S
3219 { 713, 1, 0, 0, 0, 0, 1, 287, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #713 = CATCH_REF
3220 { 712, 1, 0, 0, 0, 0, 1, 287, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #712 = CATCH_LEGACY_S
3221 { 711, 1, 0, 0, 0, 0, 1, 287, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #711 = CATCH_LEGACY
3222 { 710, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #710 = CATCH_ALL_S
3223 { 709, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #709 = CATCH_ALL_REF_S
3224 { 708, 1, 1, 0, 0, 0, 1, 288, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #708 = CATCH_ALL_REF
3225 { 707, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #707 = CATCH_ALL_LEGACY_S
3226 { 706, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #706 = CATCH_ALL_LEGACY
3227 { 705, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #705 = CATCH_ALL
3228 { 704, 1, 0, 0, 0, 0, 1, 287, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #704 = CATCH
3229 { 703, 1, 0, 0, 0, 2, 1, 152, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #703 = CALL_S
3230 { 702, 2, 0, 0, 0, 2, 1, 285, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #702 = CALL_INDIRECT_S
3231 { 701, 2, 0, 0, 0, 2, 1, 285, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #701 = CALL_INDIRECT
3232 { 700, 1, 0, 0, 0, 2, 1, 152, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #700 = CALL
3233 { 699, 1, 0, 0, 0, 0, 1, 155, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #699 = BR_UNLESS_S
3234 { 698, 2, 0, 0, 0, 0, 1, 280, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #698 = BR_UNLESS
3235 { 697, 1, 0, 0, 0, 0, 1, 283, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #697 = BR_TABLE_I64_S
3236 { 696, 1, 0, 0, 0, 0, 1, 284, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #696 = BR_TABLE_I64
3237 { 695, 1, 0, 0, 0, 0, 1, 283, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #695 = BR_TABLE_I32_S
3238 { 694, 1, 0, 0, 0, 0, 1, 282, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #694 = BR_TABLE_I32
3239 { 693, 1, 0, 0, 0, 0, 1, 155, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #693 = BR_S
3240 { 692, 1, 0, 0, 0, 0, 1, 155, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #692 = BR_IF_S
3241 { 691, 2, 0, 0, 0, 0, 1, 280, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #691 = BR_IF
3242 { 690, 1, 0, 0, 0, 0, 1, 155, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #690 = BR
3243 { 689, 1, 0, 0, 0, 1, 1, 279, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #689 = BLOCK_S
3244 { 688, 1, 0, 0, 0, 1, 1, 279, WebAssemblyImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #688 = BLOCK
3245 { 687, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #687 = BITSELECT_S
3246 { 686, 4, 1, 0, 0, 0, 1, 275, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #686 = BITSELECT
3247 { 685, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #685 = BITMASK_I8x16_S
3248 { 684, 2, 1, 0, 0, 0, 1, 177, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #684 = BITMASK_I8x16
3249 { 683, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #683 = BITMASK_I64x2_S
3250 { 682, 2, 1, 0, 0, 0, 1, 177, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #682 = BITMASK_I64x2
3251 { 681, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #681 = BITMASK_I32x4_S
3252 { 680, 2, 1, 0, 0, 0, 1, 177, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #680 = BITMASK_I32x4
3253 { 679, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #679 = BITMASK_I16x8_S
3254 { 678, 2, 1, 0, 0, 0, 1, 177, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #678 = BITMASK_I16x8
3255 { 677, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #677 = AVGR_U_I8x16_S
3256 { 676, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #676 = AVGR_U_I8x16
3257 { 675, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #675 = AVGR_U_I16x8_S
3258 { 674, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #674 = AVGR_U_I16x8
3259 { 673, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #673 = ATOMIC_STORE_I64_A64_S
3260 { 672, 4, 0, 0, 0, 0, 1, 271, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #672 = ATOMIC_STORE_I64_A64
3261 { 671, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #671 = ATOMIC_STORE_I64_A32_S
3262 { 670, 4, 0, 0, 0, 0, 1, 267, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #670 = ATOMIC_STORE_I64_A32
3263 { 669, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #669 = ATOMIC_STORE_I32_A64_S
3264 { 668, 4, 0, 0, 0, 0, 1, 263, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #668 = ATOMIC_STORE_I32_A64
3265 { 667, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #667 = ATOMIC_STORE_I32_A32_S
3266 { 666, 4, 0, 0, 0, 0, 1, 259, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #666 = ATOMIC_STORE_I32_A32
3267 { 665, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #665 = ATOMIC_STORE8_I64_A64_S
3268 { 664, 4, 0, 0, 0, 0, 1, 271, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #664 = ATOMIC_STORE8_I64_A64
3269 { 663, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #663 = ATOMIC_STORE8_I64_A32_S
3270 { 662, 4, 0, 0, 0, 0, 1, 267, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #662 = ATOMIC_STORE8_I64_A32
3271 { 661, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #661 = ATOMIC_STORE8_I32_A64_S
3272 { 660, 4, 0, 0, 0, 0, 1, 263, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #660 = ATOMIC_STORE8_I32_A64
3273 { 659, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #659 = ATOMIC_STORE8_I32_A32_S
3274 { 658, 4, 0, 0, 0, 0, 1, 259, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #658 = ATOMIC_STORE8_I32_A32
3275 { 657, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #657 = ATOMIC_STORE32_I64_A64_S
3276 { 656, 4, 0, 0, 0, 0, 1, 271, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #656 = ATOMIC_STORE32_I64_A64
3277 { 655, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #655 = ATOMIC_STORE32_I64_A32_S
3278 { 654, 4, 0, 0, 0, 0, 1, 267, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #654 = ATOMIC_STORE32_I64_A32
3279 { 653, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #653 = ATOMIC_STORE16_I64_A64_S
3280 { 652, 4, 0, 0, 0, 0, 1, 271, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #652 = ATOMIC_STORE16_I64_A64
3281 { 651, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #651 = ATOMIC_STORE16_I64_A32_S
3282 { 650, 4, 0, 0, 0, 0, 1, 267, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #650 = ATOMIC_STORE16_I64_A32
3283 { 649, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #649 = ATOMIC_STORE16_I32_A64_S
3284 { 648, 4, 0, 0, 0, 0, 1, 263, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #648 = ATOMIC_STORE16_I32_A64
3285 { 647, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #647 = ATOMIC_STORE16_I32_A32_S
3286 { 646, 4, 0, 0, 0, 0, 1, 259, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #646 = ATOMIC_STORE16_I32_A32
3287 { 645, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #645 = ATOMIC_RMW_XOR_I64_A64_S
3288 { 644, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #644 = ATOMIC_RMW_XOR_I64_A64
3289 { 643, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #643 = ATOMIC_RMW_XOR_I64_A32_S
3290 { 642, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #642 = ATOMIC_RMW_XOR_I64_A32
3291 { 641, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #641 = ATOMIC_RMW_XOR_I32_A64_S
3292 { 640, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #640 = ATOMIC_RMW_XOR_I32_A64
3293 { 639, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #639 = ATOMIC_RMW_XOR_I32_A32_S
3294 { 638, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #638 = ATOMIC_RMW_XOR_I32_A32
3295 { 637, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #637 = ATOMIC_RMW_XCHG_I64_A64_S
3296 { 636, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #636 = ATOMIC_RMW_XCHG_I64_A64
3297 { 635, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #635 = ATOMIC_RMW_XCHG_I64_A32_S
3298 { 634, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #634 = ATOMIC_RMW_XCHG_I64_A32
3299 { 633, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #633 = ATOMIC_RMW_XCHG_I32_A64_S
3300 { 632, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #632 = ATOMIC_RMW_XCHG_I32_A64
3301 { 631, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #631 = ATOMIC_RMW_XCHG_I32_A32_S
3302 { 630, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #630 = ATOMIC_RMW_XCHG_I32_A32
3303 { 629, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #629 = ATOMIC_RMW_SUB_I64_A64_S
3304 { 628, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #628 = ATOMIC_RMW_SUB_I64_A64
3305 { 627, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #627 = ATOMIC_RMW_SUB_I64_A32_S
3306 { 626, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #626 = ATOMIC_RMW_SUB_I64_A32
3307 { 625, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #625 = ATOMIC_RMW_SUB_I32_A64_S
3308 { 624, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #624 = ATOMIC_RMW_SUB_I32_A64
3309 { 623, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #623 = ATOMIC_RMW_SUB_I32_A32_S
3310 { 622, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #622 = ATOMIC_RMW_SUB_I32_A32
3311 { 621, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #621 = ATOMIC_RMW_OR_I64_A64_S
3312 { 620, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #620 = ATOMIC_RMW_OR_I64_A64
3313 { 619, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #619 = ATOMIC_RMW_OR_I64_A32_S
3314 { 618, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #618 = ATOMIC_RMW_OR_I64_A32
3315 { 617, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #617 = ATOMIC_RMW_OR_I32_A64_S
3316 { 616, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #616 = ATOMIC_RMW_OR_I32_A64
3317 { 615, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #615 = ATOMIC_RMW_OR_I32_A32_S
3318 { 614, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #614 = ATOMIC_RMW_OR_I32_A32
3319 { 613, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #613 = ATOMIC_RMW_CMPXCHG_I64_A64_S
3320 { 612, 6, 1, 0, 0, 0, 1, 253, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #612 = ATOMIC_RMW_CMPXCHG_I64_A64
3321 { 611, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #611 = ATOMIC_RMW_CMPXCHG_I64_A32_S
3322 { 610, 6, 1, 0, 0, 0, 1, 247, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #610 = ATOMIC_RMW_CMPXCHG_I64_A32
3323 { 609, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #609 = ATOMIC_RMW_CMPXCHG_I32_A64_S
3324 { 608, 6, 1, 0, 0, 0, 1, 241, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #608 = ATOMIC_RMW_CMPXCHG_I32_A64
3325 { 607, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #607 = ATOMIC_RMW_CMPXCHG_I32_A32_S
3326 { 606, 6, 1, 0, 0, 0, 1, 235, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #606 = ATOMIC_RMW_CMPXCHG_I32_A32
3327 { 605, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #605 = ATOMIC_RMW_AND_I64_A64_S
3328 { 604, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #604 = ATOMIC_RMW_AND_I64_A64
3329 { 603, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #603 = ATOMIC_RMW_AND_I64_A32_S
3330 { 602, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #602 = ATOMIC_RMW_AND_I64_A32
3331 { 601, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #601 = ATOMIC_RMW_AND_I32_A64_S
3332 { 600, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #600 = ATOMIC_RMW_AND_I32_A64
3333 { 599, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #599 = ATOMIC_RMW_AND_I32_A32_S
3334 { 598, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #598 = ATOMIC_RMW_AND_I32_A32
3335 { 597, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #597 = ATOMIC_RMW_ADD_I64_A64_S
3336 { 596, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #596 = ATOMIC_RMW_ADD_I64_A64
3337 { 595, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #595 = ATOMIC_RMW_ADD_I64_A32_S
3338 { 594, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #594 = ATOMIC_RMW_ADD_I64_A32
3339 { 593, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #593 = ATOMIC_RMW_ADD_I32_A64_S
3340 { 592, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #592 = ATOMIC_RMW_ADD_I32_A64
3341 { 591, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #591 = ATOMIC_RMW_ADD_I32_A32_S
3342 { 590, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #590 = ATOMIC_RMW_ADD_I32_A32
3343 { 589, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #589 = ATOMIC_RMW8_U_XOR_I64_A64_S
3344 { 588, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #588 = ATOMIC_RMW8_U_XOR_I64_A64
3345 { 587, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #587 = ATOMIC_RMW8_U_XOR_I64_A32_S
3346 { 586, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #586 = ATOMIC_RMW8_U_XOR_I64_A32
3347 { 585, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #585 = ATOMIC_RMW8_U_XOR_I32_A64_S
3348 { 584, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #584 = ATOMIC_RMW8_U_XOR_I32_A64
3349 { 583, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #583 = ATOMIC_RMW8_U_XOR_I32_A32_S
3350 { 582, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #582 = ATOMIC_RMW8_U_XOR_I32_A32
3351 { 581, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #581 = ATOMIC_RMW8_U_XCHG_I64_A64_S
3352 { 580, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #580 = ATOMIC_RMW8_U_XCHG_I64_A64
3353 { 579, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #579 = ATOMIC_RMW8_U_XCHG_I64_A32_S
3354 { 578, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #578 = ATOMIC_RMW8_U_XCHG_I64_A32
3355 { 577, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #577 = ATOMIC_RMW8_U_XCHG_I32_A64_S
3356 { 576, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #576 = ATOMIC_RMW8_U_XCHG_I32_A64
3357 { 575, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #575 = ATOMIC_RMW8_U_XCHG_I32_A32_S
3358 { 574, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #574 = ATOMIC_RMW8_U_XCHG_I32_A32
3359 { 573, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #573 = ATOMIC_RMW8_U_SUB_I64_A64_S
3360 { 572, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #572 = ATOMIC_RMW8_U_SUB_I64_A64
3361 { 571, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #571 = ATOMIC_RMW8_U_SUB_I64_A32_S
3362 { 570, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #570 = ATOMIC_RMW8_U_SUB_I64_A32
3363 { 569, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #569 = ATOMIC_RMW8_U_SUB_I32_A64_S
3364 { 568, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #568 = ATOMIC_RMW8_U_SUB_I32_A64
3365 { 567, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #567 = ATOMIC_RMW8_U_SUB_I32_A32_S
3366 { 566, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #566 = ATOMIC_RMW8_U_SUB_I32_A32
3367 { 565, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #565 = ATOMIC_RMW8_U_OR_I64_A64_S
3368 { 564, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #564 = ATOMIC_RMW8_U_OR_I64_A64
3369 { 563, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #563 = ATOMIC_RMW8_U_OR_I64_A32_S
3370 { 562, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #562 = ATOMIC_RMW8_U_OR_I64_A32
3371 { 561, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #561 = ATOMIC_RMW8_U_OR_I32_A64_S
3372 { 560, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #560 = ATOMIC_RMW8_U_OR_I32_A64
3373 { 559, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #559 = ATOMIC_RMW8_U_OR_I32_A32_S
3374 { 558, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #558 = ATOMIC_RMW8_U_OR_I32_A32
3375 { 557, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #557 = ATOMIC_RMW8_U_CMPXCHG_I64_A64_S
3376 { 556, 6, 1, 0, 0, 0, 1, 253, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #556 = ATOMIC_RMW8_U_CMPXCHG_I64_A64
3377 { 555, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #555 = ATOMIC_RMW8_U_CMPXCHG_I64_A32_S
3378 { 554, 6, 1, 0, 0, 0, 1, 247, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #554 = ATOMIC_RMW8_U_CMPXCHG_I64_A32
3379 { 553, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #553 = ATOMIC_RMW8_U_CMPXCHG_I32_A64_S
3380 { 552, 6, 1, 0, 0, 0, 1, 241, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #552 = ATOMIC_RMW8_U_CMPXCHG_I32_A64
3381 { 551, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #551 = ATOMIC_RMW8_U_CMPXCHG_I32_A32_S
3382 { 550, 6, 1, 0, 0, 0, 1, 235, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #550 = ATOMIC_RMW8_U_CMPXCHG_I32_A32
3383 { 549, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #549 = ATOMIC_RMW8_U_AND_I64_A64_S
3384 { 548, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #548 = ATOMIC_RMW8_U_AND_I64_A64
3385 { 547, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #547 = ATOMIC_RMW8_U_AND_I64_A32_S
3386 { 546, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #546 = ATOMIC_RMW8_U_AND_I64_A32
3387 { 545, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #545 = ATOMIC_RMW8_U_AND_I32_A64_S
3388 { 544, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #544 = ATOMIC_RMW8_U_AND_I32_A64
3389 { 543, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #543 = ATOMIC_RMW8_U_AND_I32_A32_S
3390 { 542, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #542 = ATOMIC_RMW8_U_AND_I32_A32
3391 { 541, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #541 = ATOMIC_RMW8_U_ADD_I64_A64_S
3392 { 540, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #540 = ATOMIC_RMW8_U_ADD_I64_A64
3393 { 539, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #539 = ATOMIC_RMW8_U_ADD_I64_A32_S
3394 { 538, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #538 = ATOMIC_RMW8_U_ADD_I64_A32
3395 { 537, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #537 = ATOMIC_RMW8_U_ADD_I32_A64_S
3396 { 536, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #536 = ATOMIC_RMW8_U_ADD_I32_A64
3397 { 535, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #535 = ATOMIC_RMW8_U_ADD_I32_A32_S
3398 { 534, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #534 = ATOMIC_RMW8_U_ADD_I32_A32
3399 { 533, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #533 = ATOMIC_RMW32_U_XOR_I64_A64_S
3400 { 532, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #532 = ATOMIC_RMW32_U_XOR_I64_A64
3401 { 531, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #531 = ATOMIC_RMW32_U_XOR_I64_A32_S
3402 { 530, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #530 = ATOMIC_RMW32_U_XOR_I64_A32
3403 { 529, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #529 = ATOMIC_RMW32_U_XCHG_I64_A64_S
3404 { 528, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #528 = ATOMIC_RMW32_U_XCHG_I64_A64
3405 { 527, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #527 = ATOMIC_RMW32_U_XCHG_I64_A32_S
3406 { 526, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #526 = ATOMIC_RMW32_U_XCHG_I64_A32
3407 { 525, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #525 = ATOMIC_RMW32_U_SUB_I64_A64_S
3408 { 524, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #524 = ATOMIC_RMW32_U_SUB_I64_A64
3409 { 523, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #523 = ATOMIC_RMW32_U_SUB_I64_A32_S
3410 { 522, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #522 = ATOMIC_RMW32_U_SUB_I64_A32
3411 { 521, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #521 = ATOMIC_RMW32_U_OR_I64_A64_S
3412 { 520, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #520 = ATOMIC_RMW32_U_OR_I64_A64
3413 { 519, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #519 = ATOMIC_RMW32_U_OR_I64_A32_S
3414 { 518, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #518 = ATOMIC_RMW32_U_OR_I64_A32
3415 { 517, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #517 = ATOMIC_RMW32_U_CMPXCHG_I64_A64_S
3416 { 516, 6, 1, 0, 0, 0, 1, 253, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #516 = ATOMIC_RMW32_U_CMPXCHG_I64_A64
3417 { 515, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #515 = ATOMIC_RMW32_U_CMPXCHG_I64_A32_S
3418 { 514, 6, 1, 0, 0, 0, 1, 247, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #514 = ATOMIC_RMW32_U_CMPXCHG_I64_A32
3419 { 513, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #513 = ATOMIC_RMW32_U_AND_I64_A64_S
3420 { 512, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #512 = ATOMIC_RMW32_U_AND_I64_A64
3421 { 511, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #511 = ATOMIC_RMW32_U_AND_I64_A32_S
3422 { 510, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #510 = ATOMIC_RMW32_U_AND_I64_A32
3423 { 509, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #509 = ATOMIC_RMW32_U_ADD_I64_A64_S
3424 { 508, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #508 = ATOMIC_RMW32_U_ADD_I64_A64
3425 { 507, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #507 = ATOMIC_RMW32_U_ADD_I64_A32_S
3426 { 506, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #506 = ATOMIC_RMW32_U_ADD_I64_A32
3427 { 505, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #505 = ATOMIC_RMW16_U_XOR_I64_A64_S
3428 { 504, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #504 = ATOMIC_RMW16_U_XOR_I64_A64
3429 { 503, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #503 = ATOMIC_RMW16_U_XOR_I64_A32_S
3430 { 502, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #502 = ATOMIC_RMW16_U_XOR_I64_A32
3431 { 501, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #501 = ATOMIC_RMW16_U_XOR_I32_A64_S
3432 { 500, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #500 = ATOMIC_RMW16_U_XOR_I32_A64
3433 { 499, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #499 = ATOMIC_RMW16_U_XOR_I32_A32_S
3434 { 498, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #498 = ATOMIC_RMW16_U_XOR_I32_A32
3435 { 497, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #497 = ATOMIC_RMW16_U_XCHG_I64_A64_S
3436 { 496, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #496 = ATOMIC_RMW16_U_XCHG_I64_A64
3437 { 495, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #495 = ATOMIC_RMW16_U_XCHG_I64_A32_S
3438 { 494, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #494 = ATOMIC_RMW16_U_XCHG_I64_A32
3439 { 493, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #493 = ATOMIC_RMW16_U_XCHG_I32_A64_S
3440 { 492, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #492 = ATOMIC_RMW16_U_XCHG_I32_A64
3441 { 491, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #491 = ATOMIC_RMW16_U_XCHG_I32_A32_S
3442 { 490, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #490 = ATOMIC_RMW16_U_XCHG_I32_A32
3443 { 489, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #489 = ATOMIC_RMW16_U_SUB_I64_A64_S
3444 { 488, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #488 = ATOMIC_RMW16_U_SUB_I64_A64
3445 { 487, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #487 = ATOMIC_RMW16_U_SUB_I64_A32_S
3446 { 486, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #486 = ATOMIC_RMW16_U_SUB_I64_A32
3447 { 485, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #485 = ATOMIC_RMW16_U_SUB_I32_A64_S
3448 { 484, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #484 = ATOMIC_RMW16_U_SUB_I32_A64
3449 { 483, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #483 = ATOMIC_RMW16_U_SUB_I32_A32_S
3450 { 482, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #482 = ATOMIC_RMW16_U_SUB_I32_A32
3451 { 481, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #481 = ATOMIC_RMW16_U_OR_I64_A64_S
3452 { 480, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #480 = ATOMIC_RMW16_U_OR_I64_A64
3453 { 479, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #479 = ATOMIC_RMW16_U_OR_I64_A32_S
3454 { 478, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #478 = ATOMIC_RMW16_U_OR_I64_A32
3455 { 477, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #477 = ATOMIC_RMW16_U_OR_I32_A64_S
3456 { 476, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #476 = ATOMIC_RMW16_U_OR_I32_A64
3457 { 475, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #475 = ATOMIC_RMW16_U_OR_I32_A32_S
3458 { 474, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #474 = ATOMIC_RMW16_U_OR_I32_A32
3459 { 473, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #473 = ATOMIC_RMW16_U_CMPXCHG_I64_A64_S
3460 { 472, 6, 1, 0, 0, 0, 1, 253, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #472 = ATOMIC_RMW16_U_CMPXCHG_I64_A64
3461 { 471, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #471 = ATOMIC_RMW16_U_CMPXCHG_I64_A32_S
3462 { 470, 6, 1, 0, 0, 0, 1, 247, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #470 = ATOMIC_RMW16_U_CMPXCHG_I64_A32
3463 { 469, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #469 = ATOMIC_RMW16_U_CMPXCHG_I32_A64_S
3464 { 468, 6, 1, 0, 0, 0, 1, 241, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #468 = ATOMIC_RMW16_U_CMPXCHG_I32_A64
3465 { 467, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #467 = ATOMIC_RMW16_U_CMPXCHG_I32_A32_S
3466 { 466, 6, 1, 0, 0, 0, 1, 235, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #466 = ATOMIC_RMW16_U_CMPXCHG_I32_A32
3467 { 465, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #465 = ATOMIC_RMW16_U_AND_I64_A64_S
3468 { 464, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #464 = ATOMIC_RMW16_U_AND_I64_A64
3469 { 463, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #463 = ATOMIC_RMW16_U_AND_I64_A32_S
3470 { 462, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #462 = ATOMIC_RMW16_U_AND_I64_A32
3471 { 461, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #461 = ATOMIC_RMW16_U_AND_I32_A64_S
3472 { 460, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #460 = ATOMIC_RMW16_U_AND_I32_A64
3473 { 459, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #459 = ATOMIC_RMW16_U_AND_I32_A32_S
3474 { 458, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #458 = ATOMIC_RMW16_U_AND_I32_A32
3475 { 457, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #457 = ATOMIC_RMW16_U_ADD_I64_A64_S
3476 { 456, 5, 1, 0, 0, 0, 1, 230, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #456 = ATOMIC_RMW16_U_ADD_I64_A64
3477 { 455, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #455 = ATOMIC_RMW16_U_ADD_I64_A32_S
3478 { 454, 5, 1, 0, 0, 0, 1, 225, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #454 = ATOMIC_RMW16_U_ADD_I64_A32
3479 { 453, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = ATOMIC_RMW16_U_ADD_I32_A64_S
3480 { 452, 5, 1, 0, 0, 0, 1, 220, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = ATOMIC_RMW16_U_ADD_I32_A64
3481 { 451, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #451 = ATOMIC_RMW16_U_ADD_I32_A32_S
3482 { 450, 5, 1, 0, 0, 0, 1, 215, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #450 = ATOMIC_RMW16_U_ADD_I32_A32
3483 { 449, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = ATOMIC_LOAD_I64_A64_S
3484 { 448, 4, 1, 0, 0, 0, 1, 211, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = ATOMIC_LOAD_I64_A64
3485 { 447, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #447 = ATOMIC_LOAD_I64_A32_S
3486 { 446, 4, 1, 0, 0, 0, 1, 207, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #446 = ATOMIC_LOAD_I64_A32
3487 { 445, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = ATOMIC_LOAD_I32_A64_S
3488 { 444, 4, 1, 0, 0, 0, 1, 201, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = ATOMIC_LOAD_I32_A64
3489 { 443, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #443 = ATOMIC_LOAD_I32_A32_S
3490 { 442, 4, 1, 0, 0, 0, 1, 195, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #442 = ATOMIC_LOAD_I32_A32
3491 { 441, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = ATOMIC_LOAD8_U_I64_A64_S
3492 { 440, 4, 1, 0, 0, 0, 1, 211, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = ATOMIC_LOAD8_U_I64_A64
3493 { 439, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #439 = ATOMIC_LOAD8_U_I64_A32_S
3494 { 438, 4, 1, 0, 0, 0, 1, 207, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #438 = ATOMIC_LOAD8_U_I64_A32
3495 { 437, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #437 = ATOMIC_LOAD8_U_I32_A64_S
3496 { 436, 4, 1, 0, 0, 0, 1, 201, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #436 = ATOMIC_LOAD8_U_I32_A64
3497 { 435, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #435 = ATOMIC_LOAD8_U_I32_A32_S
3498 { 434, 4, 1, 0, 0, 0, 1, 195, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #434 = ATOMIC_LOAD8_U_I32_A32
3499 { 433, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #433 = ATOMIC_LOAD32_U_I64_A64_S
3500 { 432, 4, 1, 0, 0, 0, 1, 211, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #432 = ATOMIC_LOAD32_U_I64_A64
3501 { 431, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #431 = ATOMIC_LOAD32_U_I64_A32_S
3502 { 430, 4, 1, 0, 0, 0, 1, 207, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #430 = ATOMIC_LOAD32_U_I64_A32
3503 { 429, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #429 = ATOMIC_LOAD16_U_I64_A64_S
3504 { 428, 4, 1, 0, 0, 0, 1, 211, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #428 = ATOMIC_LOAD16_U_I64_A64
3505 { 427, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #427 = ATOMIC_LOAD16_U_I64_A32_S
3506 { 426, 4, 1, 0, 0, 0, 1, 207, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #426 = ATOMIC_LOAD16_U_I64_A32
3507 { 425, 2, 0, 0, 0, 0, 1, 205, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #425 = ATOMIC_LOAD16_U_I32_A64_S
3508 { 424, 4, 1, 0, 0, 0, 1, 201, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #424 = ATOMIC_LOAD16_U_I32_A64
3509 { 423, 2, 0, 0, 0, 0, 1, 199, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #423 = ATOMIC_LOAD16_U_I32_A32_S
3510 { 422, 4, 1, 0, 0, 0, 1, 195, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #422 = ATOMIC_LOAD16_U_I32_A32
3511 { 421, 1, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #421 = ATOMIC_FENCE_S
3512 { 420, 1, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #420 = ATOMIC_FENCE
3513 { 419, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #419 = ARGUMENT_v8i16_S
3514 { 418, 2, 1, 0, 0, 1, 0, 193, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #418 = ARGUMENT_v8i16
3515 { 417, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #417 = ARGUMENT_v8f16_S
3516 { 416, 2, 1, 0, 0, 1, 0, 193, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #416 = ARGUMENT_v8f16
3517 { 415, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #415 = ARGUMENT_v4i32_S
3518 { 414, 2, 1, 0, 0, 1, 0, 193, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #414 = ARGUMENT_v4i32
3519 { 413, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #413 = ARGUMENT_v4f32_S
3520 { 412, 2, 1, 0, 0, 1, 0, 193, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #412 = ARGUMENT_v4f32
3521 { 411, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #411 = ARGUMENT_v2i64_S
3522 { 410, 2, 1, 0, 0, 1, 0, 193, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #410 = ARGUMENT_v2i64
3523 { 409, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #409 = ARGUMENT_v2f64_S
3524 { 408, 2, 1, 0, 0, 1, 0, 193, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #408 = ARGUMENT_v2f64
3525 { 407, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #407 = ARGUMENT_v16i8_S
3526 { 406, 2, 1, 0, 0, 1, 0, 193, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #406 = ARGUMENT_v16i8
3527 { 405, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #405 = ARGUMENT_i64_S
3528 { 404, 2, 1, 0, 0, 1, 0, 191, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #404 = ARGUMENT_i64
3529 { 403, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #403 = ARGUMENT_i32_S
3530 { 402, 2, 1, 0, 0, 1, 0, 189, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #402 = ARGUMENT_i32
3531 { 401, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #401 = ARGUMENT_funcref_S
3532 { 400, 2, 1, 0, 0, 1, 0, 187, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #400 = ARGUMENT_funcref
3533 { 399, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #399 = ARGUMENT_f64_S
3534 { 398, 2, 1, 0, 0, 1, 0, 185, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #398 = ARGUMENT_f64
3535 { 397, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #397 = ARGUMENT_f32_S
3536 { 396, 2, 1, 0, 0, 1, 0, 183, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #396 = ARGUMENT_f32
3537 { 395, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #395 = ARGUMENT_externref_S
3538 { 394, 2, 1, 0, 0, 1, 0, 181, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #394 = ARGUMENT_externref
3539 { 393, 1, 0, 0, 0, 1, 0, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = ARGUMENT_exnref_S
3540 { 392, 2, 1, 0, 0, 1, 0, 179, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = ARGUMENT_exnref
3541 { 391, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = ANYTRUE_S
3542 { 390, 2, 1, 0, 0, 0, 1, 177, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = ANYTRUE
3543 { 389, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = AND_S
3544 { 388, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = AND_I64_S
3545 { 387, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = AND_I64
3546 { 386, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = AND_I32_S
3547 { 385, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = AND_I32
3548 { 384, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = ANDNOT_S
3549 { 383, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = ANDNOT
3550 { 382, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = AND
3551 { 381, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = ALLTRUE_I8x16_S
3552 { 380, 2, 1, 0, 0, 0, 1, 177, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = ALLTRUE_I8x16
3553 { 379, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = ALLTRUE_I64x2_S
3554 { 378, 2, 1, 0, 0, 0, 1, 177, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = ALLTRUE_I64x2
3555 { 377, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = ALLTRUE_I32x4_S
3556 { 376, 2, 1, 0, 0, 0, 1, 177, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = ALLTRUE_I32x4
3557 { 375, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = ALLTRUE_I16x8_S
3558 { 374, 2, 1, 0, 0, 0, 1, 177, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = ALLTRUE_I16x8
3559 { 373, 2, 0, 0, 0, 2, 2, 21, WebAssemblyImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = ADJCALLSTACKUP_S
3560 { 372, 2, 0, 0, 0, 2, 2, 21, WebAssemblyImpOpBase + 4, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = ADJCALLSTACKUP
3561 { 371, 2, 0, 0, 0, 2, 2, 21, WebAssemblyImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = ADJCALLSTACKDOWN_S
3562 { 370, 2, 0, 0, 0, 2, 2, 21, WebAssemblyImpOpBase + 4, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = ADJCALLSTACKDOWN
3563 { 369, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = ADD_SAT_U_I8x16_S
3564 { 368, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = ADD_SAT_U_I8x16
3565 { 367, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = ADD_SAT_U_I16x8_S
3566 { 366, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = ADD_SAT_U_I16x8
3567 { 365, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = ADD_SAT_S_I8x16_S
3568 { 364, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = ADD_SAT_S_I8x16
3569 { 363, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = ADD_SAT_S_I16x8_S
3570 { 362, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = ADD_SAT_S_I16x8
3571 { 361, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = ADD_I8x16_S
3572 { 360, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = ADD_I8x16
3573 { 359, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = ADD_I64x2_S
3574 { 358, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = ADD_I64x2
3575 { 357, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = ADD_I64_S
3576 { 356, 3, 1, 0, 0, 0, 1, 174, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = ADD_I64
3577 { 355, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = ADD_I32x4_S
3578 { 354, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = ADD_I32x4
3579 { 353, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = ADD_I32_S
3580 { 352, 3, 1, 0, 0, 0, 1, 171, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = ADD_I32
3581 { 351, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = ADD_I16x8_S
3582 { 350, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = ADD_I16x8
3583 { 349, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = ADD_F64x2_S
3584 { 348, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = ADD_F64x2
3585 { 347, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = ADD_F64_S
3586 { 346, 3, 1, 0, 0, 0, 1, 168, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = ADD_F64
3587 { 345, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = ADD_F32x4_S
3588 { 344, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = ADD_F32x4
3589 { 343, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = ADD_F32_S
3590 { 342, 3, 1, 0, 0, 0, 1, 165, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = ADD_F32
3591 { 341, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = ADD_F16x8_S
3592 { 340, 3, 1, 0, 0, 0, 1, 162, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = ADD_F16x8
3593 { 339, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = ABS_I8x16_S
3594 { 338, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = ABS_I8x16
3595 { 337, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = ABS_I64x2_S
3596 { 336, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = ABS_I64x2
3597 { 335, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = ABS_I32x4_S
3598 { 334, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = ABS_I32x4
3599 { 333, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = ABS_I16x8_S
3600 { 332, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = ABS_I16x8
3601 { 331, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = ABS_F64x2_S
3602 { 330, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = ABS_F64x2
3603 { 329, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = ABS_F64_S
3604 { 328, 2, 1, 0, 0, 0, 1, 160, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = ABS_F64
3605 { 327, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = ABS_F32x4_S
3606 { 326, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = ABS_F32x4
3607 { 325, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = ABS_F32_S
3608 { 324, 2, 1, 0, 0, 0, 1, 158, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = ABS_F32
3609 { 323, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = ABS_F16x8_S
3610 { 322, 2, 1, 0, 0, 0, 1, 156, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = ABS_F16x8
3611 { 321, 0, 0, 0, 0, 2, 1, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #321 = RET_CALL_RESULTS_S
3612 { 320, 0, 0, 0, 0, 2, 1, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #320 = RET_CALL_RESULTS
3613 { 319, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = COMPILER_FENCE_S
3614 { 318, 0, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = COMPILER_FENCE
3615 { 317, 1, 0, 0, 0, 0, 1, 155, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = CLEANUPRET_S
3616 { 316, 1, 0, 0, 0, 0, 1, 155, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = CLEANUPRET
3617 { 315, 2, 0, 0, 0, 0, 1, 153, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = CATCHRET_S
3618 { 314, 2, 0, 0, 0, 0, 1, 153, WebAssemblyImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = CATCHRET
3619 { 313, 0, 0, 0, 0, 2, 1, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #313 = CALL_RESULTS_S
3620 { 312, 0, 0, 0, 0, 2, 1, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #312 = CALL_RESULTS
3621 { 311, 1, 0, 0, 0, 2, 1, 152, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #311 = CALL_PARAMS_S
3622 { 310, 1, 0, 0, 0, 2, 1, 152, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = CALL_PARAMS
3623 { 309, 4, 1, 0, 0, 0, 0, 148, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = G_UBFX
3624 { 308, 4, 1, 0, 0, 0, 0, 148, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = G_SBFX
3625 { 307, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #307 = G_VECREDUCE_UMIN
3626 { 306, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #306 = G_VECREDUCE_UMAX
3627 { 305, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #305 = G_VECREDUCE_SMIN
3628 { 304, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #304 = G_VECREDUCE_SMAX
3629 { 303, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #303 = G_VECREDUCE_XOR
3630 { 302, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = G_VECREDUCE_OR
3631 { 301, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = G_VECREDUCE_AND
3632 { 300, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = G_VECREDUCE_MUL
3633 { 299, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #299 = G_VECREDUCE_ADD
3634 { 298, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #298 = G_VECREDUCE_FMINIMUM
3635 { 297, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #297 = G_VECREDUCE_FMAXIMUM
3636 { 296, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = G_VECREDUCE_FMIN
3637 { 295, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = G_VECREDUCE_FMAX
3638 { 294, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_VECREDUCE_FMUL
3639 { 293, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_VECREDUCE_FADD
3640 { 292, 3, 1, 0, 0, 0, 0, 131, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_SEQ_FMUL
3641 { 291, 3, 1, 0, 0, 0, 0, 131, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_SEQ_FADD
3642 { 290, 1, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_UBSANTRAP
3643 { 289, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_DEBUGTRAP
3644 { 288, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_TRAP
3645 { 287, 3, 0, 0, 0, 0, 0, 58, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_BZERO
3646 { 286, 4, 0, 0, 0, 0, 0, 144, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_MEMSET
3647 { 285, 4, 0, 0, 0, 0, 0, 144, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_MEMMOVE
3648 { 284, 3, 0, 0, 0, 0, 0, 131, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_MEMCPY_INLINE
3649 { 283, 4, 0, 0, 0, 0, 0, 144, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_MEMCPY
3650 { 282, 2, 0, 0, 0, 0, 0, 142, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #282 = G_WRITE_REGISTER
3651 { 281, 2, 1, 0, 0, 0, 0, 51, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #281 = G_READ_REGISTER
3652 { 280, 3, 1, 0, 0, 0, 0, 101, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_STRICT_FLDEXP
3653 { 279, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_STRICT_FSQRT
3654 { 278, 4, 1, 0, 0, 0, 0, 46, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_STRICT_FMA
3655 { 277, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_STRICT_FREM
3656 { 276, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_STRICT_FDIV
3657 { 275, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_STRICT_FMUL
3658 { 274, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #274 = G_STRICT_FSUB
3659 { 273, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #273 = G_STRICT_FADD
3660 { 272, 1, 0, 0, 0, 0, 0, 50, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #272 = G_STACKRESTORE
3661 { 271, 1, 1, 0, 0, 0, 0, 50, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_STACKSAVE
3662 { 270, 3, 1, 0, 0, 0, 0, 69, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_DYN_STACKALLOC
3663 { 269, 2, 1, 0, 0, 0, 0, 51, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_JUMP_TABLE
3664 { 268, 2, 1, 0, 0, 0, 0, 51, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #268 = G_BLOCK_ADDR
3665 { 267, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #267 = G_ADDRSPACE_CAST
3666 { 266, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #266 = G_FNEARBYINT
3667 { 265, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_FRINT
3668 { 264, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_FFLOOR
3669 { 263, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_FSQRT
3670 { 262, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_FTANH
3671 { 261, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_FSINH
3672 { 260, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_FCOSH
3673 { 259, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_FATAN2
3674 { 258, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_FATAN
3675 { 257, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_FASIN
3676 { 256, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_FACOS
3677 { 255, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_FTAN
3678 { 254, 3, 2, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_FSINCOS
3679 { 253, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_FSIN
3680 { 252, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_FCOS
3681 { 251, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FCEIL
3682 { 250, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_BITREVERSE
3683 { 249, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_BSWAP
3684 { 248, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_CTPOP
3685 { 247, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_CTLZ_ZERO_UNDEF
3686 { 246, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_CTLZ
3687 { 245, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_CTTZ_ZERO_UNDEF
3688 { 244, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_CTTZ
3689 { 243, 4, 1, 0, 0, 0, 0, 138, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_VECTOR_COMPRESS
3690 { 242, 2, 1, 0, 0, 0, 0, 51, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_STEP_VECTOR
3691 { 241, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_SPLAT_VECTOR
3692 { 240, 4, 1, 0, 0, 0, 0, 134, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_SHUFFLE_VECTOR
3693 { 239, 3, 1, 0, 0, 0, 0, 131, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_EXTRACT_VECTOR_ELT
3694 { 238, 4, 1, 0, 0, 0, 0, 127, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_INSERT_VECTOR_ELT
3695 { 237, 3, 1, 0, 0, 0, 0, 58, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_EXTRACT_SUBVECTOR
3696 { 236, 4, 1, 0, 0, 0, 0, 63, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_INSERT_SUBVECTOR
3697 { 235, 2, 1, 0, 0, 0, 0, 51, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_VSCALE
3698 { 234, 3, 0, 0, 0, 0, 0, 124, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_BRJT
3699 { 233, 1, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_BR
3700 { 232, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_LLROUND
3701 { 231, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_LROUND
3702 { 230, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_ABS
3703 { 229, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_UMAX
3704 { 228, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_UMIN
3705 { 227, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_SMAX
3706 { 226, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_SMIN
3707 { 225, 3, 1, 0, 0, 0, 0, 101, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_PTRMASK
3708 { 224, 3, 1, 0, 0, 0, 0, 101, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_PTR_ADD
3709 { 223, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_RESET_FPMODE
3710 { 222, 1, 0, 0, 0, 0, 0, 50, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_SET_FPMODE
3711 { 221, 1, 1, 0, 0, 0, 0, 50, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_GET_FPMODE
3712 { 220, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_RESET_FPENV
3713 { 219, 1, 0, 0, 0, 0, 0, 50, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_SET_FPENV
3714 { 218, 1, 1, 0, 0, 0, 0, 50, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_GET_FPENV
3715 { 217, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_FMAXIMUMNUM
3716 { 216, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_FMINIMUMNUM
3717 { 215, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_FMAXIMUM
3718 { 214, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_FMINIMUM
3719 { 213, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_FMAXNUM_IEEE
3720 { 212, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_FMINNUM_IEEE
3721 { 211, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_FMAXNUM
3722 { 210, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_FMINNUM
3723 { 209, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_FCANONICALIZE
3724 { 208, 3, 1, 0, 0, 0, 0, 98, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_IS_FPCLASS
3725 { 207, 3, 1, 0, 0, 0, 0, 101, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_FCOPYSIGN
3726 { 206, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_FABS
3727 { 205, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FPTOUI_SAT
3728 { 204, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_FPTOSI_SAT
3729 { 203, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_UITOFP
3730 { 202, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_SITOFP
3731 { 201, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FPTOUI
3732 { 200, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FPTOSI
3733 { 199, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_FPTRUNC
3734 { 198, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_FPEXT
3735 { 197, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FNEG
3736 { 196, 3, 2, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_FFREXP
3737 { 195, 3, 1, 0, 0, 0, 0, 101, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_FLDEXP
3738 { 194, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_FLOG10
3739 { 193, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FLOG2
3740 { 192, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FLOG
3741 { 191, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FEXP10
3742 { 190, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FEXP2
3743 { 189, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FEXP
3744 { 188, 3, 1, 0, 0, 0, 0, 101, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FPOWI
3745 { 187, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FPOW
3746 { 186, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FREM
3747 { 185, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FDIV
3748 { 184, 4, 1, 0, 0, 0, 0, 46, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FMAD
3749 { 183, 4, 1, 0, 0, 0, 0, 46, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FMA
3750 { 182, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FMUL
3751 { 181, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FSUB
3752 { 180, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FADD
3753 { 179, 4, 1, 0, 0, 0, 0, 120, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #179 = G_UDIVFIXSAT
3754 { 178, 4, 1, 0, 0, 0, 0, 120, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #178 = G_SDIVFIXSAT
3755 { 177, 4, 1, 0, 0, 0, 0, 120, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #177 = G_UDIVFIX
3756 { 176, 4, 1, 0, 0, 0, 0, 120, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #176 = G_SDIVFIX
3757 { 175, 4, 1, 0, 0, 0, 0, 120, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #175 = G_UMULFIXSAT
3758 { 174, 4, 1, 0, 0, 0, 0, 120, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #174 = G_SMULFIXSAT
3759 { 173, 4, 1, 0, 0, 0, 0, 120, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #173 = G_UMULFIX
3760 { 172, 4, 1, 0, 0, 0, 0, 120, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #172 = G_SMULFIX
3761 { 171, 3, 1, 0, 0, 0, 0, 101, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #171 = G_SSHLSAT
3762 { 170, 3, 1, 0, 0, 0, 0, 101, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #170 = G_USHLSAT
3763 { 169, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #169 = G_SSUBSAT
3764 { 168, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #168 = G_USUBSAT
3765 { 167, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #167 = G_SADDSAT
3766 { 166, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #166 = G_UADDSAT
3767 { 165, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #165 = G_SMULH
3768 { 164, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #164 = G_UMULH
3769 { 163, 4, 2, 0, 0, 0, 0, 87, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #163 = G_SMULO
3770 { 162, 4, 2, 0, 0, 0, 0, 87, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #162 = G_UMULO
3771 { 161, 5, 2, 0, 0, 0, 0, 115, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #161 = G_SSUBE
3772 { 160, 4, 2, 0, 0, 0, 0, 87, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #160 = G_SSUBO
3773 { 159, 5, 2, 0, 0, 0, 0, 115, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #159 = G_SADDE
3774 { 158, 4, 2, 0, 0, 0, 0, 87, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #158 = G_SADDO
3775 { 157, 5, 2, 0, 0, 0, 0, 115, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #157 = G_USUBE
3776 { 156, 4, 2, 0, 0, 0, 0, 87, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #156 = G_USUBO
3777 { 155, 5, 2, 0, 0, 0, 0, 115, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #155 = G_UADDE
3778 { 154, 4, 2, 0, 0, 0, 0, 87, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #154 = G_UADDO
3779 { 153, 4, 1, 0, 0, 0, 0, 87, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #153 = G_SELECT
3780 { 152, 3, 1, 0, 0, 0, 0, 112, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #152 = G_UCMP
3781 { 151, 3, 1, 0, 0, 0, 0, 112, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #151 = G_SCMP
3782 { 150, 4, 1, 0, 0, 0, 0, 108, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #150 = G_FCMP
3783 { 149, 4, 1, 0, 0, 0, 0, 108, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #149 = G_ICMP
3784 { 148, 3, 1, 0, 0, 0, 0, 101, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #148 = G_ROTL
3785 { 147, 3, 1, 0, 0, 0, 0, 101, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #147 = G_ROTR
3786 { 146, 4, 1, 0, 0, 0, 0, 104, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #146 = G_FSHR
3787 { 145, 4, 1, 0, 0, 0, 0, 104, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #145 = G_FSHL
3788 { 144, 3, 1, 0, 0, 0, 0, 101, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #144 = G_ASHR
3789 { 143, 3, 1, 0, 0, 0, 0, 101, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #143 = G_LSHR
3790 { 142, 3, 1, 0, 0, 0, 0, 101, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #142 = G_SHL
3791 { 141, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #141 = G_ZEXT
3792 { 140, 3, 1, 0, 0, 0, 0, 40, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #140 = G_SEXT_INREG
3793 { 139, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #139 = G_SEXT
3794 { 138, 3, 1, 0, 0, 0, 0, 98, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #138 = G_VAARG
3795 { 137, 1, 0, 0, 0, 0, 0, 50, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #137 = G_VASTART
3796 { 136, 2, 1, 0, 0, 0, 0, 51, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #136 = G_FCONSTANT
3797 { 135, 2, 1, 0, 0, 0, 0, 51, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #135 = G_CONSTANT
3798 { 134, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #134 = G_TRUNC
3799 { 133, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #133 = G_ANYEXT
3800 { 132, 1, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3801 { 131, 1, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #131 = G_INTRINSIC_CONVERGENT
3802 { 130, 1, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS
3803 { 129, 1, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #129 = G_INTRINSIC
3804 { 128, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #128 = G_INVOKE_REGION_START
3805 { 127, 1, 0, 0, 0, 0, 0, 50, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #127 = G_BRINDIRECT
3806 { 126, 2, 0, 0, 0, 0, 0, 51, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #126 = G_BRCOND
3807 { 125, 4, 0, 0, 0, 0, 0, 94, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #125 = G_PREFETCH
3808 { 124, 2, 0, 0, 0, 0, 0, 21, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #124 = G_FENCE
3809 { 123, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #123 = G_ATOMICRMW_USUB_SAT
3810 { 122, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #122 = G_ATOMICRMW_USUB_COND
3811 { 121, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP
3812 { 120, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #120 = G_ATOMICRMW_UINC_WRAP
3813 { 119, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #119 = G_ATOMICRMW_FMINIMUM
3814 { 118, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #118 = G_ATOMICRMW_FMAXIMUM
3815 { 117, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #117 = G_ATOMICRMW_FMIN
3816 { 116, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #116 = G_ATOMICRMW_FMAX
3817 { 115, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #115 = G_ATOMICRMW_FSUB
3818 { 114, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FADD
3819 { 113, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #113 = G_ATOMICRMW_UMIN
3820 { 112, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #112 = G_ATOMICRMW_UMAX
3821 { 111, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #111 = G_ATOMICRMW_MIN
3822 { 110, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #110 = G_ATOMICRMW_MAX
3823 { 109, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #109 = G_ATOMICRMW_XOR
3824 { 108, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #108 = G_ATOMICRMW_OR
3825 { 107, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #107 = G_ATOMICRMW_NAND
3826 { 106, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #106 = G_ATOMICRMW_AND
3827 { 105, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #105 = G_ATOMICRMW_SUB
3828 { 104, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #104 = G_ATOMICRMW_ADD
3829 { 103, 3, 1, 0, 0, 0, 0, 91, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #103 = G_ATOMICRMW_XCHG
3830 { 102, 4, 1, 0, 0, 0, 0, 87, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #102 = G_ATOMIC_CMPXCHG
3831 { 101, 5, 2, 0, 0, 0, 0, 82, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
3832 { 100, 5, 1, 0, 0, 0, 0, 77, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #100 = G_INDEXED_STORE
3833 { 99, 2, 0, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #99 = G_STORE
3834 { 98, 5, 2, 0, 0, 0, 0, 72, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #98 = G_INDEXED_ZEXTLOAD
3835 { 97, 5, 2, 0, 0, 0, 0, 72, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #97 = G_INDEXED_SEXTLOAD
3836 { 96, 5, 2, 0, 0, 0, 0, 72, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #96 = G_INDEXED_LOAD
3837 { 95, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #95 = G_ZEXTLOAD
3838 { 94, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #94 = G_SEXTLOAD
3839 { 93, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #93 = G_LOAD
3840 { 92, 1, 1, 0, 0, 0, 0, 50, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #92 = G_READSTEADYCOUNTER
3841 { 91, 1, 1, 0, 0, 0, 0, 50, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #91 = G_READCYCLECOUNTER
3842 { 90, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #90 = G_INTRINSIC_ROUNDEVEN
3843 { 89, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #89 = G_INTRINSIC_LLRINT
3844 { 88, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #88 = G_INTRINSIC_LRINT
3845 { 87, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUND
3846 { 86, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #86 = G_INTRINSIC_TRUNC
3847 { 85, 3, 1, 0, 0, 0, 0, 69, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
3848 { 84, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #84 = G_CONSTANT_FOLD_BARRIER
3849 { 83, 2, 1, 0, 0, 0, 0, 67, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #83 = G_FREEZE
3850 { 82, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #82 = G_BITCAST
3851 { 81, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #81 = G_INTTOPTR
3852 { 80, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #80 = G_PTRTOINT
3853 { 79, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #79 = G_CONCAT_VECTORS
3854 { 78, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #78 = G_BUILD_VECTOR_TRUNC
3855 { 77, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #77 = G_BUILD_VECTOR
3856 { 76, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #76 = G_MERGE_VALUES
3857 { 75, 4, 1, 0, 0, 0, 0, 63, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #75 = G_INSERT
3858 { 74, 2, 1, 0, 0, 0, 0, 61, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #74 = G_UNMERGE_VALUES
3859 { 73, 3, 1, 0, 0, 0, 0, 58, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #73 = G_EXTRACT
3860 { 72, 2, 1, 0, 0, 0, 0, 51, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #72 = G_CONSTANT_POOL
3861 { 71, 5, 1, 0, 0, 0, 0, 53, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
3862 { 70, 2, 1, 0, 0, 0, 0, 51, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #70 = G_GLOBAL_VALUE
3863 { 69, 2, 1, 0, 0, 0, 0, 51, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #69 = G_FRAME_INDEX
3864 { 68, 1, 1, 0, 0, 0, 0, 50, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #68 = G_PHI
3865 { 67, 1, 1, 0, 0, 0, 0, 50, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #67 = G_IMPLICIT_DEF
3866 { 66, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #66 = G_ABDU
3867 { 65, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #65 = G_ABDS
3868 { 64, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #64 = G_XOR
3869 { 63, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #63 = G_OR
3870 { 62, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #62 = G_AND
3871 { 61, 4, 2, 0, 0, 0, 0, 46, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #61 = G_UDIVREM
3872 { 60, 4, 2, 0, 0, 0, 0, 46, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #60 = G_SDIVREM
3873 { 59, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #59 = G_UREM
3874 { 58, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #58 = G_SREM
3875 { 57, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #57 = G_UDIV
3876 { 56, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #56 = G_SDIV
3877 { 55, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #55 = G_MUL
3878 { 54, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #54 = G_SUB
3879 { 53, 3, 1, 0, 0, 0, 0, 43, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #53 = G_ADD
3880 { 52, 3, 1, 0, 0, 0, 0, 40, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #52 = G_ASSERT_ALIGN
3881 { 51, 3, 1, 0, 0, 0, 0, 40, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #51 = G_ASSERT_ZEXT
3882 { 50, 3, 1, 0, 0, 0, 0, 40, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #50 = G_ASSERT_SEXT
3883 { 49, 1, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #49 = CONVERGENCECTRL_GLUE
3884 { 48, 2, 1, 0, 0, 0, 0, 13, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_LOOP
3885 { 47, 1, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_ANCHOR
3886 { 46, 1, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ENTRY
3887 { 45, 1, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #45 = JUMP_TABLE_DEBUG_INFO
3888 { 44, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #44 = MEMBARRIER
3889 { 43, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #43 = FAKE_USE
3890 { 42, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #42 = ICALL_BRANCH_FUNNEL
3891 { 41, 3, 0, 0, 0, 0, 0, 37, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
3892 { 40, 2, 0, 0, 0, 0, 0, 35, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #40 = PATCHABLE_EVENT_CALL
3893 { 39, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #39 = PATCHABLE_TAIL_CALL
3894 { 38, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #38 = PATCHABLE_FUNCTION_EXIT
3895 { 37, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #37 = PATCHABLE_RET
3896 { 36, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #36 = PATCHABLE_FUNCTION_ENTER
3897 { 35, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #35 = PATCHABLE_OP
3898 { 34, 1, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #34 = FAULTING_OP
3899 { 33, 2, 0, 0, 0, 0, 0, 33, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #33 = LOCAL_ESCAPE
3900 { 32, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #32 = STATEPOINT
3901 { 31, 3, 1, 0, 0, 0, 0, 30, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #31 = PREALLOCATED_ARG
3902 { 30, 1, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #30 = PREALLOCATED_SETUP
3903 { 29, 1, 1, 0, 0, 0, 0, 29, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #29 = LOAD_STACK_GUARD
3904 { 28, 6, 1, 0, 0, 0, 0, 23, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #28 = PATCHPOINT
3905 { 27, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #27 = FENTRY_CALL
3906 { 26, 2, 0, 0, 0, 0, 0, 21, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #26 = STACKMAP
3907 { 25, 2, 1, 0, 0, 0, 0, 19, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #25 = ARITH_FENCE
3908 { 24, 4, 0, 0, 0, 0, 0, 15, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #24 = PSEUDO_PROBE
3909 { 23, 1, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #23 = LIFETIME_END
3910 { 22, 1, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #22 = LIFETIME_START
3911 { 21, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #21 = BUNDLE
3912 { 20, 2, 1, 0, 0, 0, 0, 13, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #20 = COPY
3913 { 19, 2, 1, 0, 0, 0, 0, 13, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #19 = REG_SEQUENCE
3914 { 18, 1, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #18 = DBG_LABEL
3915 { 17, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #17 = DBG_PHI
3916 { 16, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #16 = DBG_INSTR_REF
3917 { 15, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #15 = DBG_VALUE_LIST
3918 { 14, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #14 = DBG_VALUE
3919 { 13, 3, 1, 0, 0, 0, 0, 2, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #13 = COPY_TO_REGCLASS
3920 { 12, 4, 1, 0, 0, 0, 0, 9, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #12 = SUBREG_TO_REG
3921 { 11, 1, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #11 = INIT_UNDEF
3922 { 10, 1, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
3923 { 9, 4, 1, 0, 0, 0, 0, 5, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #9 = INSERT_SUBREG
3924 { 8, 3, 1, 0, 0, 0, 0, 2, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
3925 { 7, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #7 = KILL
3926 { 6, 1, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
3927 { 5, 1, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #5 = GC_LABEL
3928 { 4, 1, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #4 = EH_LABEL
3929 { 3, 1, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
3930 { 2, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #2 = INLINEASM_BR
3931 { 1, 0, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1 = INLINEASM
3932 { 0, 1, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #0 = PHI
3933 }, {
3934 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3935 /* 1 */
3936 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3937 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3938 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3939 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3940 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3941 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3942 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
3943 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3944 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3945 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
3946 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3947 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3948 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3949 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3950 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3951 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3952 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3953 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3954 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3955 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3956 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3957 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3958 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3959 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3960 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3961 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3962 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3963 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3964 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3965 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3966 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3967 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3968 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3969 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3970 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3971 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3972 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3973 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3974 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3975 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
3976 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
3977 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3978 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3979 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3980 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3981 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3982 /* 152 */ { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 },
3983 /* 153 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 },
3984 /* 155 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 },
3985 /* 156 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3986 /* 158 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3987 /* 160 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3988 /* 162 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3989 /* 165 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3990 /* 168 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3991 /* 171 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3992 /* 174 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3993 /* 177 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3994 /* 179 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3995 /* 181 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3996 /* 183 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3997 /* 185 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3998 /* 187 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3999 /* 189 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4000 /* 191 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4001 /* 193 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4002 /* 195 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4003 /* 199 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 },
4004 /* 201 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4005 /* 205 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 },
4006 /* 207 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4007 /* 211 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4008 /* 215 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4009 /* 220 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4010 /* 225 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4011 /* 230 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4012 /* 235 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4013 /* 241 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4014 /* 247 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4015 /* 253 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4016 /* 259 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4017 /* 263 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4018 /* 267 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4019 /* 271 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4020 /* 275 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4021 /* 279 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 },
4022 /* 280 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4023 /* 282 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4024 /* 283 */ { -1, 0, WebAssembly::OPERAND_BRLIST, 0 },
4025 /* 284 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4026 /* 285 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4027 /* 287 */ { -1, 0, WebAssembly::OPERAND_TAG, 0 },
4028 /* 288 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4029 /* 289 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4030 /* 291 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4031 /* 293 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4032 /* 295 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4033 /* 296 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4034 /* 298 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4035 /* 299 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
4036 /* 301 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
4037 /* 302 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I64IMM, 0 },
4038 /* 304 */ { -1, 0, WebAssembly::OPERAND_I64IMM, 0 },
4039 /* 305 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4040 /* 310 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
4041 /* 314 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4042 /* 317 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
4043 /* 319 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 },
4044 /* 328 */ { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 },
4045 /* 336 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 },
4046 /* 341 */ { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 },
4047 /* 345 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 },
4048 /* 348 */ { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 },
4049 /* 350 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4050 /* 367 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4051 /* 383 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4052 /* 385 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4053 /* 387 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4054 /* 389 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4055 /* 390 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4056 /* 391 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4057 /* 392 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4058 /* 393 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4059 /* 394 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4060 /* 396 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4061 /* 399 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4062 /* 402 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4063 /* 405 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4064 /* 408 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4065 /* 409 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4066 /* 412 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4067 /* 415 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4068 /* 418 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4069 /* 420 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4070 /* 422 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4071 /* 424 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4072 /* 426 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4073 /* 428 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4074 /* 430 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4075 /* 432 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4076 /* 434 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4077 /* 436 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4078 /* 438 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4079 /* 440 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4080 /* 441 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4081 /* 443 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4082 /* 445 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4083 /* 447 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4084 /* 449 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4085 /* 451 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4086 /* 453 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4087 /* 455 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4088 /* 457 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4089 /* 459 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4090 /* 461 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4091 /* 463 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4092 /* 465 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4093 /* 467 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4094 /* 469 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4095 /* 471 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4096 /* 477 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4097 /* 479 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4098 /* 483 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4099 /* 485 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4100 /* 489 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4101 /* 493 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4102 /* 497 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4103 /* 501 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4104 /* 505 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4105 /* 509 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4106 /* 515 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4107 /* 518 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4108 /* 524 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4109 /* 527 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4110 /* 529 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4111 /* 530 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4112 /* 532 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4113 /* 534 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4114 /* 536 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4115 /* 538 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4116 /* 540 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4117 /* 542 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4118 /* 544 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4119 /* 546 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4120 /* 548 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4121 /* 550 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4122 /* 552 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4123 /* 554 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4124 /* 556 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4125 /* 558 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4126 /* 560 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4127 /* 563 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4128 /* 566 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4129 /* 569 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4130 /* 572 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4131 /* 575 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4132 /* 578 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4133 /* 581 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4134 /* 584 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4135 /* 589 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
4136 /* 591 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4137 /* 596 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4138 /* 602 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4139 /* 608 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4140 /* 614 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4141 /* 620 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4142 /* 624 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4143 /* 628 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4144 /* 633 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4145 /* 635 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4146 /* 637 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4147 /* 639 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4148 /* 643 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4149 /* 647 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4150 /* 651 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4151 /* 655 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4152 /* 659 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4153 /* 663 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4154 /* 667 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4155 /* 671 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4156 /* 675 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4157 /* 679 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4158 /* 683 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4159 /* 687 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4160 /* 690 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4161 /* 709 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4162 /* 711 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4163 /* 713 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4164 /* 715 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4165 /* 717 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4166 /* 721 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4167 /* 725 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4168 /* 729 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4169 /* 733 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4170 /* 738 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4171 /* 743 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4172 /* 747 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4173 /* 751 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4174 /* 756 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4175 /* 758 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4176 /* 762 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4177 /* 763 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4178 /* 767 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4179 /* 771 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4180 /* 774 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4181 /* 777 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4182 /* 780 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4183 /* 784 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4184 /* 788 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4185 /* 792 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4186 /* 795 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4187 /* 798 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4188 /* 801 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4189 /* 803 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4190 /* 806 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4191 /* 809 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4192 /* 812 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { -1, 0, WebAssembly::OPERAND_CATCH_LIST, 0 },
4193 /* 814 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4194 /* 817 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4195 }, {
4196 /* 0 */
4197 /* 0 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::ARGUMENTS,
4198 /* 3 */ WebAssembly::ARGUMENTS,
4199 /* 4 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::SP32, WebAssembly::SP64,
4200 /* 8 */ WebAssembly::VALUE_STACK, WebAssembly::VALUE_STACK,
4201 }
4202};
4203
4204
4205#ifdef __GNUC__
4206#pragma GCC diagnostic push
4207#pragma GCC diagnostic ignored "-Woverlength-strings"
4208#endif
4209extern const char WebAssemblyInstrNameData[] = {
4210 /* 0 */ "G_FLOG10\000"
4211 /* 9 */ "G_FEXP10\000"
4212 /* 18 */ "LOAD_F16_F32_A32\000"
4213 /* 35 */ "STORE_F16_F32_A32\000"
4214 /* 53 */ "LOAD_F32_A32\000"
4215 /* 66 */ "STORE_F32_A32\000"
4216 /* 80 */ "ATOMIC_STORE16_I32_A32\000"
4217 /* 103 */ "ATOMIC_STORE8_I32_A32\000"
4218 /* 125 */ "ATOMIC_RMW16_U_SUB_I32_A32\000"
4219 /* 152 */ "ATOMIC_RMW8_U_SUB_I32_A32\000"
4220 /* 178 */ "ATOMIC_RMW_SUB_I32_A32\000"
4221 /* 201 */ "ATOMIC_LOAD_I32_A32\000"
4222 /* 221 */ "ATOMIC_RMW16_U_ADD_I32_A32\000"
4223 /* 248 */ "ATOMIC_RMW8_U_ADD_I32_A32\000"
4224 /* 274 */ "ATOMIC_RMW_ADD_I32_A32\000"
4225 /* 297 */ "ATOMIC_RMW16_U_AND_I32_A32\000"
4226 /* 324 */ "ATOMIC_RMW8_U_AND_I32_A32\000"
4227 /* 350 */ "ATOMIC_RMW_AND_I32_A32\000"
4228 /* 373 */ "ATOMIC_STORE_I32_A32\000"
4229 /* 394 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32\000"
4230 /* 425 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32\000"
4231 /* 455 */ "ATOMIC_RMW_CMPXCHG_I32_A32\000"
4232 /* 482 */ "ATOMIC_RMW16_U_XCHG_I32_A32\000"
4233 /* 510 */ "ATOMIC_RMW8_U_XCHG_I32_A32\000"
4234 /* 537 */ "ATOMIC_RMW_XCHG_I32_A32\000"
4235 /* 561 */ "ATOMIC_RMW16_U_XOR_I32_A32\000"
4236 /* 588 */ "ATOMIC_RMW8_U_XOR_I32_A32\000"
4237 /* 614 */ "ATOMIC_RMW_XOR_I32_A32\000"
4238 /* 637 */ "ATOMIC_RMW16_U_OR_I32_A32\000"
4239 /* 663 */ "ATOMIC_RMW8_U_OR_I32_A32\000"
4240 /* 688 */ "ATOMIC_RMW_OR_I32_A32\000"
4241 /* 710 */ "LOAD16_S_I32_A32\000"
4242 /* 727 */ "LOAD8_S_I32_A32\000"
4243 /* 743 */ "ATOMIC_LOAD16_U_I32_A32\000"
4244 /* 767 */ "ATOMIC_LOAD8_U_I32_A32\000"
4245 /* 790 */ "MEMORY_ATOMIC_WAIT32_A32\000"
4246 /* 815 */ "LOAD_LANE_32_A32\000"
4247 /* 832 */ "LOAD_ZERO_32_A32\000"
4248 /* 849 */ "STORE_LANE_I64x2_A32\000"
4249 /* 870 */ "LOAD_EXTEND_S_I64x2_A32\000"
4250 /* 894 */ "LOAD_EXTEND_U_I64x2_A32\000"
4251 /* 918 */ "LOAD_F64_A32\000"
4252 /* 931 */ "STORE_F64_A32\000"
4253 /* 945 */ "ATOMIC_STORE32_I64_A32\000"
4254 /* 968 */ "ATOMIC_STORE16_I64_A32\000"
4255 /* 991 */ "ATOMIC_STORE8_I64_A32\000"
4256 /* 1013 */ "ATOMIC_RMW32_U_SUB_I64_A32\000"
4257 /* 1040 */ "ATOMIC_RMW16_U_SUB_I64_A32\000"
4258 /* 1067 */ "ATOMIC_RMW8_U_SUB_I64_A32\000"
4259 /* 1093 */ "ATOMIC_RMW_SUB_I64_A32\000"
4260 /* 1116 */ "ATOMIC_LOAD_I64_A32\000"
4261 /* 1136 */ "ATOMIC_RMW32_U_ADD_I64_A32\000"
4262 /* 1163 */ "ATOMIC_RMW16_U_ADD_I64_A32\000"
4263 /* 1190 */ "ATOMIC_RMW8_U_ADD_I64_A32\000"
4264 /* 1216 */ "ATOMIC_RMW_ADD_I64_A32\000"
4265 /* 1239 */ "ATOMIC_RMW32_U_AND_I64_A32\000"
4266 /* 1266 */ "ATOMIC_RMW16_U_AND_I64_A32\000"
4267 /* 1293 */ "ATOMIC_RMW8_U_AND_I64_A32\000"
4268 /* 1319 */ "ATOMIC_RMW_AND_I64_A32\000"
4269 /* 1342 */ "ATOMIC_STORE_I64_A32\000"
4270 /* 1363 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32\000"
4271 /* 1394 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32\000"
4272 /* 1425 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32\000"
4273 /* 1455 */ "ATOMIC_RMW_CMPXCHG_I64_A32\000"
4274 /* 1482 */ "ATOMIC_RMW32_U_XCHG_I64_A32\000"
4275 /* 1510 */ "ATOMIC_RMW16_U_XCHG_I64_A32\000"
4276 /* 1538 */ "ATOMIC_RMW8_U_XCHG_I64_A32\000"
4277 /* 1565 */ "ATOMIC_RMW_XCHG_I64_A32\000"
4278 /* 1589 */ "ATOMIC_RMW32_U_XOR_I64_A32\000"
4279 /* 1616 */ "ATOMIC_RMW16_U_XOR_I64_A32\000"
4280 /* 1643 */ "ATOMIC_RMW8_U_XOR_I64_A32\000"
4281 /* 1669 */ "ATOMIC_RMW_XOR_I64_A32\000"
4282 /* 1692 */ "ATOMIC_RMW32_U_OR_I64_A32\000"
4283 /* 1718 */ "ATOMIC_RMW16_U_OR_I64_A32\000"
4284 /* 1744 */ "ATOMIC_RMW8_U_OR_I64_A32\000"
4285 /* 1769 */ "ATOMIC_RMW_OR_I64_A32\000"
4286 /* 1791 */ "LOAD32_S_I64_A32\000"
4287 /* 1808 */ "LOAD16_S_I64_A32\000"
4288 /* 1825 */ "LOAD8_S_I64_A32\000"
4289 /* 1841 */ "ATOMIC_LOAD32_U_I64_A32\000"
4290 /* 1865 */ "ATOMIC_LOAD16_U_I64_A32\000"
4291 /* 1889 */ "ATOMIC_LOAD8_U_I64_A32\000"
4292 /* 1912 */ "MEMORY_ATOMIC_WAIT64_A32\000"
4293 /* 1937 */ "LOAD_LANE_64_A32\000"
4294 /* 1954 */ "LOAD_ZERO_64_A32\000"
4295 /* 1971 */ "STORE_LANE_I32x4_A32\000"
4296 /* 1992 */ "LOAD_EXTEND_S_I32x4_A32\000"
4297 /* 2016 */ "LOAD_EXTEND_U_I32x4_A32\000"
4298 /* 2040 */ "LOAD_LANE_16_A32\000"
4299 /* 2057 */ "STORE_LANE_I8x16_A32\000"
4300 /* 2078 */ "LOAD_V128_A32\000"
4301 /* 2092 */ "STORE_V128_A32\000"
4302 /* 2107 */ "LOAD_LANE_8_A32\000"
4303 /* 2123 */ "STORE_LANE_I16x8_A32\000"
4304 /* 2144 */ "LOAD_EXTEND_S_I16x8_A32\000"
4305 /* 2168 */ "LOAD_EXTEND_U_I16x8_A32\000"
4306 /* 2192 */ "anonymous_8818MEMORY_SIZE_A32\000"
4307 /* 2222 */ "MEMORY_FILL_A32\000"
4308 /* 2238 */ "LOAD32_SPLAT_A32\000"
4309 /* 2255 */ "LOAD64_SPLAT_A32\000"
4310 /* 2272 */ "LOAD16_SPLAT_A32\000"
4311 /* 2289 */ "LOAD8_SPLAT_A32\000"
4312 /* 2305 */ "MEMSET_A32\000"
4313 /* 2316 */ "MEMORY_INIT_A32\000"
4314 /* 2332 */ "anonymous_8818MEMORY_GROW_A32\000"
4315 /* 2362 */ "MEMORY_ATOMIC_NOTIFY_A32\000"
4316 /* 2387 */ "MEMCPY_A32\000"
4317 /* 2398 */ "MEMORY_COPY_A32\000"
4318 /* 2414 */ "FP_TO_SINT_I32_F32\000"
4319 /* 2433 */ "FP_TO_UINT_I32_F32\000"
4320 /* 2452 */ "FP_TO_SINT_I64_F32\000"
4321 /* 2471 */ "FP_TO_UINT_I64_F32\000"
4322 /* 2490 */ "SUB_F32\000"
4323 /* 2498 */ "TRUNC_F32\000"
4324 /* 2508 */ "ADD_F32\000"
4325 /* 2516 */ "LOCAL_TEE_F32\000"
4326 /* 2530 */ "GE_F32\000"
4327 /* 2537 */ "LE_F32\000"
4328 /* 2544 */ "NE_F32\000"
4329 /* 2551 */ "F64_PROMOTE_F32\000"
4330 /* 2567 */ "NEG_F32\000"
4331 /* 2575 */ "CEIL_F32\000"
4332 /* 2584 */ "MUL_F32\000"
4333 /* 2592 */ "COPYSIGN_F32\000"
4334 /* 2605 */ "MIN_F32\000"
4335 /* 2613 */ "DROP_F32\000"
4336 /* 2622 */ "EQ_F32\000"
4337 /* 2629 */ "FLOOR_F32\000"
4338 /* 2639 */ "ABS_F32\000"
4339 /* 2647 */ "I32_TRUNC_S_F32\000"
4340 /* 2663 */ "I64_TRUNC_S_F32\000"
4341 /* 2679 */ "I32_TRUNC_S_SAT_F32\000"
4342 /* 2699 */ "I64_TRUNC_S_SAT_F32\000"
4343 /* 2719 */ "I32_TRUNC_U_SAT_F32\000"
4344 /* 2739 */ "I64_TRUNC_U_SAT_F32\000"
4345 /* 2759 */ "SELECT_F32\000"
4346 /* 2770 */ "GLOBAL_GET_F32\000"
4347 /* 2785 */ "LOCAL_GET_F32\000"
4348 /* 2799 */ "I32_REINTERPRET_F32\000"
4349 /* 2819 */ "GLOBAL_SET_F32\000"
4350 /* 2834 */ "LOCAL_SET_F32\000"
4351 /* 2848 */ "GT_F32\000"
4352 /* 2855 */ "LT_F32\000"
4353 /* 2862 */ "SQRT_F32\000"
4354 /* 2871 */ "NEAREST_F32\000"
4355 /* 2883 */ "CONST_F32\000"
4356 /* 2893 */ "I32_TRUNC_U_F32\000"
4357 /* 2909 */ "I64_TRUNC_U_F32\000"
4358 /* 2925 */ "DIV_F32\000"
4359 /* 2933 */ "MAX_F32\000"
4360 /* 2941 */ "COPY_F32\000"
4361 /* 2950 */ "SUB_I32\000"
4362 /* 2958 */ "ADD_I32\000"
4363 /* 2966 */ "AND_I32\000"
4364 /* 2974 */ "LOCAL_TEE_I32\000"
4365 /* 2988 */ "BR_TABLE_I32\000"
4366 /* 3001 */ "NE_I32\000"
4367 /* 3008 */ "SHL_I32\000"
4368 /* 3016 */ "ROTL_I32\000"
4369 /* 3025 */ "MUL_I32\000"
4370 /* 3033 */ "DROP_I32\000"
4371 /* 3042 */ "EQ_I32\000"
4372 /* 3049 */ "XOR_I32\000"
4373 /* 3057 */ "ROTR_I32\000"
4374 /* 3066 */ "I32_EXTEND16_S_I32\000"
4375 /* 3085 */ "I32_EXTEND8_S_I32\000"
4376 /* 3103 */ "I64_EXTEND_S_I32\000"
4377 /* 3120 */ "GE_S_I32\000"
4378 /* 3129 */ "LE_S_I32\000"
4379 /* 3138 */ "REM_S_I32\000"
4380 /* 3148 */ "SHR_S_I32\000"
4381 /* 3158 */ "GT_S_I32\000"
4382 /* 3167 */ "LT_S_I32\000"
4383 /* 3176 */ "F32_CONVERT_S_I32\000"
4384 /* 3194 */ "F64_CONVERT_S_I32\000"
4385 /* 3212 */ "DIV_S_I32\000"
4386 /* 3222 */ "SELECT_I32\000"
4387 /* 3233 */ "GLOBAL_GET_I32\000"
4388 /* 3248 */ "LOCAL_GET_I32\000"
4389 /* 3262 */ "F32_REINTERPRET_I32\000"
4390 /* 3282 */ "GLOBAL_SET_I32\000"
4391 /* 3297 */ "LOCAL_SET_I32\000"
4392 /* 3311 */ "POPCNT_I32\000"
4393 /* 3322 */ "CONST_I32\000"
4394 /* 3332 */ "I64_EXTEND_U_I32\000"
4395 /* 3349 */ "GE_U_I32\000"
4396 /* 3358 */ "LE_U_I32\000"
4397 /* 3367 */ "REM_U_I32\000"
4398 /* 3377 */ "SHR_U_I32\000"
4399 /* 3387 */ "GT_U_I32\000"
4400 /* 3396 */ "LT_U_I32\000"
4401 /* 3405 */ "F32_CONVERT_U_I32\000"
4402 /* 3423 */ "F64_CONVERT_U_I32\000"
4403 /* 3441 */ "DIV_U_I32\000"
4404 /* 3451 */ "COPY_I32\000"
4405 /* 3460 */ "CLZ_I32\000"
4406 /* 3468 */ "EQZ_I32\000"
4407 /* 3476 */ "CTZ_I32\000"
4408 /* 3484 */ "ARGUMENT_v4f32\000"
4409 /* 3499 */ "ARGUMENT_f32\000"
4410 /* 3512 */ "ARGUMENT_v4i32\000"
4411 /* 3527 */ "ARGUMENT_i32\000"
4412 /* 3540 */ "G_FLOG2\000"
4413 /* 3548 */ "G_FATAN2\000"
4414 /* 3557 */ "G_FEXP2\000"
4415 /* 3565 */ "CONST_V128_F64x2\000"
4416 /* 3582 */ "SUB_F64x2\000"
4417 /* 3592 */ "TRUNC_F64x2\000"
4418 /* 3604 */ "NMADD_F64x2\000"
4419 /* 3616 */ "GE_F64x2\000"
4420 /* 3625 */ "LE_F64x2\000"
4421 /* 3634 */ "REPLACE_LANE_F64x2\000"
4422 /* 3653 */ "EXTRACT_LANE_F64x2\000"
4423 /* 3672 */ "NEG_F64x2\000"
4424 /* 3682 */ "CEIL_F64x2\000"
4425 /* 3693 */ "MUL_F64x2\000"
4426 /* 3703 */ "SIMD_RELAXED_FMIN_F64x2\000"
4427 /* 3727 */ "PMIN_F64x2\000"
4428 /* 3738 */ "EQ_F64x2\000"
4429 /* 3747 */ "FLOOR_F64x2\000"
4430 /* 3759 */ "ABS_F64x2\000"
4431 /* 3769 */ "SPLAT_F64x2\000"
4432 /* 3781 */ "GT_F64x2\000"
4433 /* 3790 */ "LT_F64x2\000"
4434 /* 3799 */ "SQRT_F64x2\000"
4435 /* 3810 */ "NEAREST_F64x2\000"
4436 /* 3824 */ "DIV_F64x2\000"
4437 /* 3834 */ "SIMD_RELAXED_FMAX_F64x2\000"
4438 /* 3858 */ "PMAX_F64x2\000"
4439 /* 3869 */ "convert_low_s_F64x2\000"
4440 /* 3889 */ "convert_low_u_F64x2\000"
4441 /* 3909 */ "promote_low_F64x2\000"
4442 /* 3927 */ "CONST_V128_I64x2\000"
4443 /* 3944 */ "SUB_I64x2\000"
4444 /* 3954 */ "ADD_I64x2\000"
4445 /* 3964 */ "REPLACE_LANE_I64x2\000"
4446 /* 3983 */ "EXTRACT_LANE_I64x2\000"
4447 /* 4002 */ "ALLTRUE_I64x2\000"
4448 /* 4016 */ "NEG_I64x2\000"
4449 /* 4026 */ "BITMASK_I64x2\000"
4450 /* 4040 */ "SHL_I64x2\000"
4451 /* 4050 */ "MUL_I64x2\000"
4452 /* 4060 */ "EQ_I64x2\000"
4453 /* 4069 */ "ABS_I64x2\000"
4454 /* 4079 */ "GE_S_I64x2\000"
4455 /* 4090 */ "LE_S_I64x2\000"
4456 /* 4101 */ "EXTMUL_HIGH_S_I64x2\000"
4457 /* 4121 */ "SHR_S_I64x2\000"
4458 /* 4133 */ "GT_S_I64x2\000"
4459 /* 4144 */ "LT_S_I64x2\000"
4460 /* 4155 */ "EXTMUL_LOW_S_I64x2\000"
4461 /* 4174 */ "SPLAT_I64x2\000"
4462 /* 4186 */ "LANESELECT_I64x2\000"
4463 /* 4203 */ "EXTMUL_HIGH_U_I64x2\000"
4464 /* 4223 */ "SHR_U_I64x2\000"
4465 /* 4235 */ "EXTMUL_LOW_U_I64x2\000"
4466 /* 4254 */ "extend_high_s_I64x2\000"
4467 /* 4274 */ "extend_low_s_I64x2\000"
4468 /* 4293 */ "extend_high_u_I64x2\000"
4469 /* 4313 */ "extend_low_u_I64x2\000"
4470 /* 4332 */ "LOAD_F16_F32_A64\000"
4471 /* 4349 */ "STORE_F16_F32_A64\000"
4472 /* 4367 */ "LOAD_F32_A64\000"
4473 /* 4380 */ "STORE_F32_A64\000"
4474 /* 4394 */ "ATOMIC_STORE16_I32_A64\000"
4475 /* 4417 */ "ATOMIC_STORE8_I32_A64\000"
4476 /* 4439 */ "ATOMIC_RMW16_U_SUB_I32_A64\000"
4477 /* 4466 */ "ATOMIC_RMW8_U_SUB_I32_A64\000"
4478 /* 4492 */ "ATOMIC_RMW_SUB_I32_A64\000"
4479 /* 4515 */ "ATOMIC_LOAD_I32_A64\000"
4480 /* 4535 */ "ATOMIC_RMW16_U_ADD_I32_A64\000"
4481 /* 4562 */ "ATOMIC_RMW8_U_ADD_I32_A64\000"
4482 /* 4588 */ "ATOMIC_RMW_ADD_I32_A64\000"
4483 /* 4611 */ "ATOMIC_RMW16_U_AND_I32_A64\000"
4484 /* 4638 */ "ATOMIC_RMW8_U_AND_I32_A64\000"
4485 /* 4664 */ "ATOMIC_RMW_AND_I32_A64\000"
4486 /* 4687 */ "ATOMIC_STORE_I32_A64\000"
4487 /* 4708 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64\000"
4488 /* 4739 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64\000"
4489 /* 4769 */ "ATOMIC_RMW_CMPXCHG_I32_A64\000"
4490 /* 4796 */ "ATOMIC_RMW16_U_XCHG_I32_A64\000"
4491 /* 4824 */ "ATOMIC_RMW8_U_XCHG_I32_A64\000"
4492 /* 4851 */ "ATOMIC_RMW_XCHG_I32_A64\000"
4493 /* 4875 */ "ATOMIC_RMW16_U_XOR_I32_A64\000"
4494 /* 4902 */ "ATOMIC_RMW8_U_XOR_I32_A64\000"
4495 /* 4928 */ "ATOMIC_RMW_XOR_I32_A64\000"
4496 /* 4951 */ "ATOMIC_RMW16_U_OR_I32_A64\000"
4497 /* 4977 */ "ATOMIC_RMW8_U_OR_I32_A64\000"
4498 /* 5002 */ "ATOMIC_RMW_OR_I32_A64\000"
4499 /* 5024 */ "LOAD16_S_I32_A64\000"
4500 /* 5041 */ "LOAD8_S_I32_A64\000"
4501 /* 5057 */ "ATOMIC_LOAD16_U_I32_A64\000"
4502 /* 5081 */ "ATOMIC_LOAD8_U_I32_A64\000"
4503 /* 5104 */ "MEMORY_ATOMIC_WAIT32_A64\000"
4504 /* 5129 */ "LOAD_LANE_32_A64\000"
4505 /* 5146 */ "LOAD_ZERO_32_A64\000"
4506 /* 5163 */ "STORE_LANE_I64x2_A64\000"
4507 /* 5184 */ "LOAD_EXTEND_S_I64x2_A64\000"
4508 /* 5208 */ "LOAD_EXTEND_U_I64x2_A64\000"
4509 /* 5232 */ "LOAD_F64_A64\000"
4510 /* 5245 */ "STORE_F64_A64\000"
4511 /* 5259 */ "ATOMIC_STORE32_I64_A64\000"
4512 /* 5282 */ "ATOMIC_STORE16_I64_A64\000"
4513 /* 5305 */ "ATOMIC_STORE8_I64_A64\000"
4514 /* 5327 */ "ATOMIC_RMW32_U_SUB_I64_A64\000"
4515 /* 5354 */ "ATOMIC_RMW16_U_SUB_I64_A64\000"
4516 /* 5381 */ "ATOMIC_RMW8_U_SUB_I64_A64\000"
4517 /* 5407 */ "ATOMIC_RMW_SUB_I64_A64\000"
4518 /* 5430 */ "ATOMIC_LOAD_I64_A64\000"
4519 /* 5450 */ "ATOMIC_RMW32_U_ADD_I64_A64\000"
4520 /* 5477 */ "ATOMIC_RMW16_U_ADD_I64_A64\000"
4521 /* 5504 */ "ATOMIC_RMW8_U_ADD_I64_A64\000"
4522 /* 5530 */ "ATOMIC_RMW_ADD_I64_A64\000"
4523 /* 5553 */ "ATOMIC_RMW32_U_AND_I64_A64\000"
4524 /* 5580 */ "ATOMIC_RMW16_U_AND_I64_A64\000"
4525 /* 5607 */ "ATOMIC_RMW8_U_AND_I64_A64\000"
4526 /* 5633 */ "ATOMIC_RMW_AND_I64_A64\000"
4527 /* 5656 */ "ATOMIC_STORE_I64_A64\000"
4528 /* 5677 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64\000"
4529 /* 5708 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64\000"
4530 /* 5739 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64\000"
4531 /* 5769 */ "ATOMIC_RMW_CMPXCHG_I64_A64\000"
4532 /* 5796 */ "ATOMIC_RMW32_U_XCHG_I64_A64\000"
4533 /* 5824 */ "ATOMIC_RMW16_U_XCHG_I64_A64\000"
4534 /* 5852 */ "ATOMIC_RMW8_U_XCHG_I64_A64\000"
4535 /* 5879 */ "ATOMIC_RMW_XCHG_I64_A64\000"
4536 /* 5903 */ "ATOMIC_RMW32_U_XOR_I64_A64\000"
4537 /* 5930 */ "ATOMIC_RMW16_U_XOR_I64_A64\000"
4538 /* 5957 */ "ATOMIC_RMW8_U_XOR_I64_A64\000"
4539 /* 5983 */ "ATOMIC_RMW_XOR_I64_A64\000"
4540 /* 6006 */ "ATOMIC_RMW32_U_OR_I64_A64\000"
4541 /* 6032 */ "ATOMIC_RMW16_U_OR_I64_A64\000"
4542 /* 6058 */ "ATOMIC_RMW8_U_OR_I64_A64\000"
4543 /* 6083 */ "ATOMIC_RMW_OR_I64_A64\000"
4544 /* 6105 */ "LOAD32_S_I64_A64\000"
4545 /* 6122 */ "LOAD16_S_I64_A64\000"
4546 /* 6139 */ "LOAD8_S_I64_A64\000"
4547 /* 6155 */ "ATOMIC_LOAD32_U_I64_A64\000"
4548 /* 6179 */ "ATOMIC_LOAD16_U_I64_A64\000"
4549 /* 6203 */ "ATOMIC_LOAD8_U_I64_A64\000"
4550 /* 6226 */ "MEMORY_ATOMIC_WAIT64_A64\000"
4551 /* 6251 */ "LOAD_LANE_64_A64\000"
4552 /* 6268 */ "LOAD_ZERO_64_A64\000"
4553 /* 6285 */ "STORE_LANE_I32x4_A64\000"
4554 /* 6306 */ "LOAD_EXTEND_S_I32x4_A64\000"
4555 /* 6330 */ "LOAD_EXTEND_U_I32x4_A64\000"
4556 /* 6354 */ "LOAD_LANE_16_A64\000"
4557 /* 6371 */ "STORE_LANE_I8x16_A64\000"
4558 /* 6392 */ "LOAD_V128_A64\000"
4559 /* 6406 */ "STORE_V128_A64\000"
4560 /* 6421 */ "LOAD_LANE_8_A64\000"
4561 /* 6437 */ "STORE_LANE_I16x8_A64\000"
4562 /* 6458 */ "LOAD_EXTEND_S_I16x8_A64\000"
4563 /* 6482 */ "LOAD_EXTEND_U_I16x8_A64\000"
4564 /* 6506 */ "anonymous_8819MEMORY_SIZE_A64\000"
4565 /* 6536 */ "MEMORY_FILL_A64\000"
4566 /* 6552 */ "LOAD32_SPLAT_A64\000"
4567 /* 6569 */ "LOAD64_SPLAT_A64\000"
4568 /* 6586 */ "LOAD16_SPLAT_A64\000"
4569 /* 6603 */ "LOAD8_SPLAT_A64\000"
4570 /* 6619 */ "MEMSET_A64\000"
4571 /* 6630 */ "MEMORY_INIT_A64\000"
4572 /* 6646 */ "anonymous_8819MEMORY_GROW_A64\000"
4573 /* 6676 */ "MEMORY_ATOMIC_NOTIFY_A64\000"
4574 /* 6701 */ "MEMCPY_A64\000"
4575 /* 6712 */ "MEMORY_COPY_A64\000"
4576 /* 6728 */ "FP_TO_SINT_I32_F64\000"
4577 /* 6747 */ "FP_TO_UINT_I32_F64\000"
4578 /* 6766 */ "FP_TO_SINT_I64_F64\000"
4579 /* 6785 */ "FP_TO_UINT_I64_F64\000"
4580 /* 6804 */ "SUB_F64\000"
4581 /* 6812 */ "TRUNC_F64\000"
4582 /* 6822 */ "ADD_F64\000"
4583 /* 6830 */ "LOCAL_TEE_F64\000"
4584 /* 6844 */ "GE_F64\000"
4585 /* 6851 */ "LE_F64\000"
4586 /* 6858 */ "NE_F64\000"
4587 /* 6865 */ "F32_DEMOTE_F64\000"
4588 /* 6880 */ "NEG_F64\000"
4589 /* 6888 */ "CEIL_F64\000"
4590 /* 6897 */ "MUL_F64\000"
4591 /* 6905 */ "COPYSIGN_F64\000"
4592 /* 6918 */ "MIN_F64\000"
4593 /* 6926 */ "DROP_F64\000"
4594 /* 6935 */ "EQ_F64\000"
4595 /* 6942 */ "FLOOR_F64\000"
4596 /* 6952 */ "ABS_F64\000"
4597 /* 6960 */ "I32_TRUNC_S_F64\000"
4598 /* 6976 */ "I64_TRUNC_S_F64\000"
4599 /* 6992 */ "I32_TRUNC_S_SAT_F64\000"
4600 /* 7012 */ "I64_TRUNC_S_SAT_F64\000"
4601 /* 7032 */ "I32_TRUNC_U_SAT_F64\000"
4602 /* 7052 */ "I64_TRUNC_U_SAT_F64\000"
4603 /* 7072 */ "SELECT_F64\000"
4604 /* 7083 */ "GLOBAL_GET_F64\000"
4605 /* 7098 */ "LOCAL_GET_F64\000"
4606 /* 7112 */ "I64_REINTERPRET_F64\000"
4607 /* 7132 */ "GLOBAL_SET_F64\000"
4608 /* 7147 */ "LOCAL_SET_F64\000"
4609 /* 7161 */ "GT_F64\000"
4610 /* 7168 */ "LT_F64\000"
4611 /* 7175 */ "SQRT_F64\000"
4612 /* 7184 */ "NEAREST_F64\000"
4613 /* 7196 */ "CONST_F64\000"
4614 /* 7206 */ "I32_TRUNC_U_F64\000"
4615 /* 7222 */ "I64_TRUNC_U_F64\000"
4616 /* 7238 */ "DIV_F64\000"
4617 /* 7246 */ "MAX_F64\000"
4618 /* 7254 */ "COPY_F64\000"
4619 /* 7263 */ "SUB_I64\000"
4620 /* 7271 */ "ADD_I64\000"
4621 /* 7279 */ "AND_I64\000"
4622 /* 7287 */ "LOCAL_TEE_I64\000"
4623 /* 7301 */ "BR_TABLE_I64\000"
4624 /* 7314 */ "NE_I64\000"
4625 /* 7321 */ "SHL_I64\000"
4626 /* 7329 */ "ROTL_I64\000"
4627 /* 7338 */ "MUL_I64\000"
4628 /* 7346 */ "I32_WRAP_I64\000"
4629 /* 7359 */ "DROP_I64\000"
4630 /* 7368 */ "EQ_I64\000"
4631 /* 7375 */ "XOR_I64\000"
4632 /* 7383 */ "ROTR_I64\000"
4633 /* 7392 */ "I64_EXTEND32_S_I64\000"
4634 /* 7411 */ "I64_EXTEND16_S_I64\000"
4635 /* 7430 */ "I64_EXTEND8_S_I64\000"
4636 /* 7448 */ "GE_S_I64\000"
4637 /* 7457 */ "LE_S_I64\000"
4638 /* 7466 */ "REM_S_I64\000"
4639 /* 7476 */ "SHR_S_I64\000"
4640 /* 7486 */ "GT_S_I64\000"
4641 /* 7495 */ "LT_S_I64\000"
4642 /* 7504 */ "F32_CONVERT_S_I64\000"
4643 /* 7522 */ "F64_CONVERT_S_I64\000"
4644 /* 7540 */ "DIV_S_I64\000"
4645 /* 7550 */ "SELECT_I64\000"
4646 /* 7561 */ "GLOBAL_GET_I64\000"
4647 /* 7576 */ "LOCAL_GET_I64\000"
4648 /* 7590 */ "F64_REINTERPRET_I64\000"
4649 /* 7610 */ "GLOBAL_SET_I64\000"
4650 /* 7625 */ "LOCAL_SET_I64\000"
4651 /* 7639 */ "POPCNT_I64\000"
4652 /* 7650 */ "CONST_I64\000"
4653 /* 7660 */ "GE_U_I64\000"
4654 /* 7669 */ "LE_U_I64\000"
4655 /* 7678 */ "REM_U_I64\000"
4656 /* 7688 */ "SHR_U_I64\000"
4657 /* 7698 */ "GT_U_I64\000"
4658 /* 7707 */ "LT_U_I64\000"
4659 /* 7716 */ "F32_CONVERT_U_I64\000"
4660 /* 7734 */ "F64_CONVERT_U_I64\000"
4661 /* 7752 */ "DIV_U_I64\000"
4662 /* 7762 */ "COPY_I64\000"
4663 /* 7771 */ "CLZ_I64\000"
4664 /* 7779 */ "EQZ_I64\000"
4665 /* 7787 */ "CTZ_I64\000"
4666 /* 7795 */ "ARGUMENT_v2f64\000"
4667 /* 7810 */ "ARGUMENT_f64\000"
4668 /* 7823 */ "ARGUMENT_v2i64\000"
4669 /* 7838 */ "ARGUMENT_i64\000"
4670 /* 7851 */ "CONST_V128_F32x4\000"
4671 /* 7868 */ "SUB_F32x4\000"
4672 /* 7878 */ "TRUNC_F32x4\000"
4673 /* 7890 */ "NMADD_F32x4\000"
4674 /* 7902 */ "GE_F32x4\000"
4675 /* 7911 */ "LE_F32x4\000"
4676 /* 7920 */ "REPLACE_LANE_F32x4\000"
4677 /* 7939 */ "EXTRACT_LANE_F32x4\000"
4678 /* 7958 */ "NEG_F32x4\000"
4679 /* 7968 */ "CEIL_F32x4\000"
4680 /* 7979 */ "MUL_F32x4\000"
4681 /* 7989 */ "SIMD_RELAXED_FMIN_F32x4\000"
4682 /* 8013 */ "PMIN_F32x4\000"
4683 /* 8024 */ "EQ_F32x4\000"
4684 /* 8033 */ "FLOOR_F32x4\000"
4685 /* 8045 */ "ABS_F32x4\000"
4686 /* 8055 */ "SPLAT_F32x4\000"
4687 /* 8067 */ "GT_F32x4\000"
4688 /* 8076 */ "LT_F32x4\000"
4689 /* 8085 */ "SQRT_F32x4\000"
4690 /* 8096 */ "NEAREST_F32x4\000"
4691 /* 8110 */ "DIV_F32x4\000"
4692 /* 8120 */ "SIMD_RELAXED_FMAX_F32x4\000"
4693 /* 8144 */ "PMAX_F32x4\000"
4694 /* 8155 */ "demote_zero_F32x4\000"
4695 /* 8173 */ "sint_to_fp_F32x4\000"
4696 /* 8190 */ "uint_to_fp_F32x4\000"
4697 /* 8207 */ "CONST_V128_I32x4\000"
4698 /* 8224 */ "SUB_I32x4\000"
4699 /* 8234 */ "ADD_I32x4\000"
4700 /* 8244 */ "REPLACE_LANE_I32x4\000"
4701 /* 8263 */ "EXTRACT_LANE_I32x4\000"
4702 /* 8282 */ "ALLTRUE_I32x4\000"
4703 /* 8296 */ "NEG_I32x4\000"
4704 /* 8306 */ "BITMASK_I32x4\000"
4705 /* 8320 */ "SHL_I32x4\000"
4706 /* 8330 */ "MUL_I32x4\000"
4707 /* 8340 */ "EQ_I32x4\000"
4708 /* 8349 */ "ABS_I32x4\000"
4709 /* 8359 */ "GE_S_I32x4\000"
4710 /* 8370 */ "LE_S_I32x4\000"
4711 /* 8381 */ "EXTMUL_HIGH_S_I32x4\000"
4712 /* 8401 */ "MIN_S_I32x4\000"
4713 /* 8413 */ "SHR_S_I32x4\000"
4714 /* 8425 */ "GT_S_I32x4\000"
4715 /* 8436 */ "LT_S_I32x4\000"
4716 /* 8447 */ "EXTMUL_LOW_S_I32x4\000"
4717 /* 8466 */ "MAX_S_I32x4\000"
4718 /* 8478 */ "SPLAT_I32x4\000"
4719 /* 8490 */ "LANESELECT_I32x4\000"
4720 /* 8507 */ "GE_U_I32x4\000"
4721 /* 8518 */ "LE_U_I32x4\000"
4722 /* 8529 */ "EXTMUL_HIGH_U_I32x4\000"
4723 /* 8549 */ "MIN_U_I32x4\000"
4724 /* 8561 */ "SHR_U_I32x4\000"
4725 /* 8573 */ "GT_U_I32x4\000"
4726 /* 8584 */ "LT_U_I32x4\000"
4727 /* 8595 */ "EXTMUL_LOW_U_I32x4\000"
4728 /* 8614 */ "MAX_U_I32x4\000"
4729 /* 8626 */ "int_wasm_relaxed_trunc_signed_I32x4\000"
4730 /* 8662 */ "int_wasm_extadd_pairwise_signed_I32x4\000"
4731 /* 8700 */ "int_wasm_relaxed_trunc_unsigned_I32x4\000"
4732 /* 8738 */ "int_wasm_extadd_pairwise_unsigned_I32x4\000"
4733 /* 8778 */ "int_wasm_relaxed_trunc_signed_zero_I32x4\000"
4734 /* 8819 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4\000"
4735 /* 8862 */ "extend_high_s_I32x4\000"
4736 /* 8882 */ "trunc_sat_zero_s_I32x4\000"
4737 /* 8905 */ "extend_low_s_I32x4\000"
4738 /* 8924 */ "fp_to_sint_I32x4\000"
4739 /* 8941 */ "fp_to_uint_I32x4\000"
4740 /* 8958 */ "extend_high_u_I32x4\000"
4741 /* 8978 */ "trunc_sat_zero_u_I32x4\000"
4742 /* 9001 */ "extend_low_u_I32x4\000"
4743 /* 9020 */ "ARGUMENT_v8f16\000"
4744 /* 9035 */ "ARGUMENT_v8i16\000"
4745 /* 9050 */ "CONST_V128_I8x16\000"
4746 /* 9067 */ "SUB_I8x16\000"
4747 /* 9077 */ "ADD_I8x16\000"
4748 /* 9087 */ "REPLACE_LANE_I8x16\000"
4749 /* 9106 */ "ALLTRUE_I8x16\000"
4750 /* 9120 */ "NEG_I8x16\000"
4751 /* 9130 */ "BITMASK_I8x16\000"
4752 /* 9144 */ "SHL_I8x16\000"
4753 /* 9154 */ "EQ_I8x16\000"
4754 /* 9163 */ "ABS_I8x16\000"
4755 /* 9173 */ "GE_S_I8x16\000"
4756 /* 9184 */ "LE_S_I8x16\000"
4757 /* 9195 */ "MIN_S_I8x16\000"
4758 /* 9207 */ "SHR_S_I8x16\000"
4759 /* 9219 */ "SUB_SAT_S_I8x16\000"
4760 /* 9235 */ "ADD_SAT_S_I8x16\000"
4761 /* 9251 */ "GT_S_I8x16\000"
4762 /* 9262 */ "LT_S_I8x16\000"
4763 /* 9273 */ "NARROW_S_I8x16\000"
4764 /* 9288 */ "MAX_S_I8x16\000"
4765 /* 9300 */ "SPLAT_I8x16\000"
4766 /* 9312 */ "LANESELECT_I8x16\000"
4767 /* 9329 */ "POPCNT_I8x16\000"
4768 /* 9342 */ "GE_U_I8x16\000"
4769 /* 9353 */ "LE_U_I8x16\000"
4770 /* 9364 */ "MIN_U_I8x16\000"
4771 /* 9376 */ "AVGR_U_I8x16\000"
4772 /* 9389 */ "SHR_U_I8x16\000"
4773 /* 9401 */ "SUB_SAT_U_I8x16\000"
4774 /* 9417 */ "ADD_SAT_U_I8x16\000"
4775 /* 9433 */ "GT_U_I8x16\000"
4776 /* 9444 */ "LT_U_I8x16\000"
4777 /* 9455 */ "NARROW_U_I8x16\000"
4778 /* 9470 */ "MAX_U_I8x16\000"
4779 /* 9482 */ "I64_SUB128\000"
4780 /* 9493 */ "I64_ADD128\000"
4781 /* 9504 */ "LOCAL_TEE_V128\000"
4782 /* 9519 */ "DROP_V128\000"
4783 /* 9529 */ "SELECT_V128\000"
4784 /* 9541 */ "GLOBAL_GET_V128\000"
4785 /* 9557 */ "LOCAL_GET_V128\000"
4786 /* 9572 */ "GLOBAL_SET_V128\000"
4787 /* 9588 */ "LOCAL_SET_V128\000"
4788 /* 9603 */ "COPY_V128\000"
4789 /* 9613 */ "ARGUMENT_v16i8\000"
4790 /* 9628 */ "SUB_F16x8\000"
4791 /* 9638 */ "TRUNC_F16x8\000"
4792 /* 9650 */ "NMADD_F16x8\000"
4793 /* 9662 */ "GE_F16x8\000"
4794 /* 9671 */ "LE_F16x8\000"
4795 /* 9680 */ "REPLACE_LANE_F16x8\000"
4796 /* 9699 */ "EXTRACT_LANE_F16x8\000"
4797 /* 9718 */ "NEG_F16x8\000"
4798 /* 9728 */ "CEIL_F16x8\000"
4799 /* 9739 */ "MUL_F16x8\000"
4800 /* 9749 */ "PMIN_F16x8\000"
4801 /* 9760 */ "EQ_F16x8\000"
4802 /* 9769 */ "FLOOR_F16x8\000"
4803 /* 9781 */ "ABS_F16x8\000"
4804 /* 9791 */ "SPLAT_F16x8\000"
4805 /* 9803 */ "GT_F16x8\000"
4806 /* 9812 */ "LT_F16x8\000"
4807 /* 9821 */ "SQRT_F16x8\000"
4808 /* 9832 */ "NEAREST_F16x8\000"
4809 /* 9846 */ "DIV_F16x8\000"
4810 /* 9856 */ "PMAX_F16x8\000"
4811 /* 9867 */ "sint_to_fp_F16x8\000"
4812 /* 9884 */ "uint_to_fp_F16x8\000"
4813 /* 9901 */ "CONST_V128_I16x8\000"
4814 /* 9918 */ "SUB_I16x8\000"
4815 /* 9928 */ "ADD_I16x8\000"
4816 /* 9938 */ "REPLACE_LANE_I16x8\000"
4817 /* 9957 */ "ALLTRUE_I16x8\000"
4818 /* 9971 */ "NEG_I16x8\000"
4819 /* 9981 */ "BITMASK_I16x8\000"
4820 /* 9995 */ "SHL_I16x8\000"
4821 /* 10005 */ "MUL_I16x8\000"
4822 /* 10015 */ "EQ_I16x8\000"
4823 /* 10024 */ "ABS_I16x8\000"
4824 /* 10034 */ "GE_S_I16x8\000"
4825 /* 10045 */ "LE_S_I16x8\000"
4826 /* 10056 */ "EXTMUL_HIGH_S_I16x8\000"
4827 /* 10076 */ "MIN_S_I16x8\000"
4828 /* 10088 */ "SHR_S_I16x8\000"
4829 /* 10100 */ "RELAXED_Q15MULR_S_I16x8\000"
4830 /* 10124 */ "SUB_SAT_S_I16x8\000"
4831 /* 10140 */ "ADD_SAT_S_I16x8\000"
4832 /* 10156 */ "Q15MULR_SAT_S_I16x8\000"
4833 /* 10176 */ "GT_S_I16x8\000"
4834 /* 10187 */ "LT_S_I16x8\000"
4835 /* 10198 */ "EXTMUL_LOW_S_I16x8\000"
4836 /* 10217 */ "NARROW_S_I16x8\000"
4837 /* 10232 */ "MAX_S_I16x8\000"
4838 /* 10244 */ "SPLAT_I16x8\000"
4839 /* 10256 */ "LANESELECT_I16x8\000"
4840 /* 10273 */ "GE_U_I16x8\000"
4841 /* 10284 */ "LE_U_I16x8\000"
4842 /* 10295 */ "EXTMUL_HIGH_U_I16x8\000"
4843 /* 10315 */ "MIN_U_I16x8\000"
4844 /* 10327 */ "AVGR_U_I16x8\000"
4845 /* 10340 */ "SHR_U_I16x8\000"
4846 /* 10352 */ "SUB_SAT_U_I16x8\000"
4847 /* 10368 */ "ADD_SAT_U_I16x8\000"
4848 /* 10384 */ "GT_U_I16x8\000"
4849 /* 10395 */ "LT_U_I16x8\000"
4850 /* 10406 */ "EXTMUL_LOW_U_I16x8\000"
4851 /* 10425 */ "NARROW_U_I16x8\000"
4852 /* 10440 */ "MAX_U_I16x8\000"
4853 /* 10452 */ "int_wasm_extadd_pairwise_signed_I16x8\000"
4854 /* 10490 */ "int_wasm_extadd_pairwise_unsigned_I16x8\000"
4855 /* 10530 */ "extend_high_s_I16x8\000"
4856 /* 10550 */ "extend_low_s_I16x8\000"
4857 /* 10569 */ "fp_to_sint_I16x8\000"
4858 /* 10586 */ "fp_to_uint_I16x8\000"
4859 /* 10603 */ "extend_high_u_I16x8\000"
4860 /* 10623 */ "extend_low_u_I16x8\000"
4861 /* 10642 */ "G_FMA\000"
4862 /* 10648 */ "G_STRICT_FMA\000"
4863 /* 10661 */ "G_FSUB\000"
4864 /* 10668 */ "G_STRICT_FSUB\000"
4865 /* 10682 */ "G_ATOMICRMW_FSUB\000"
4866 /* 10699 */ "G_SUB\000"
4867 /* 10705 */ "G_ATOMICRMW_SUB\000"
4868 /* 10721 */ "G_INTRINSIC\000"
4869 /* 10733 */ "G_FPTRUNC\000"
4870 /* 10743 */ "G_INTRINSIC_TRUNC\000"
4871 /* 10761 */ "G_TRUNC\000"
4872 /* 10769 */ "G_BUILD_VECTOR_TRUNC\000"
4873 /* 10790 */ "G_DYN_STACKALLOC\000"
4874 /* 10807 */ "G_FMAD\000"
4875 /* 10814 */ "G_INDEXED_SEXTLOAD\000"
4876 /* 10833 */ "G_SEXTLOAD\000"
4877 /* 10844 */ "G_INDEXED_ZEXTLOAD\000"
4878 /* 10863 */ "G_ZEXTLOAD\000"
4879 /* 10874 */ "G_INDEXED_LOAD\000"
4880 /* 10889 */ "G_LOAD\000"
4881 /* 10896 */ "G_VECREDUCE_FADD\000"
4882 /* 10913 */ "G_FADD\000"
4883 /* 10920 */ "G_VECREDUCE_SEQ_FADD\000"
4884 /* 10941 */ "G_STRICT_FADD\000"
4885 /* 10955 */ "G_ATOMICRMW_FADD\000"
4886 /* 10972 */ "G_VECREDUCE_ADD\000"
4887 /* 10988 */ "G_ADD\000"
4888 /* 10994 */ "G_PTR_ADD\000"
4889 /* 11004 */ "RELAXED_DOT_ADD\000"
4890 /* 11020 */ "G_ATOMICRMW_ADD\000"
4891 /* 11036 */ "G_ATOMICRMW_NAND\000"
4892 /* 11053 */ "G_VECREDUCE_AND\000"
4893 /* 11069 */ "G_AND\000"
4894 /* 11075 */ "G_ATOMICRMW_AND\000"
4895 /* 11091 */ "LIFETIME_END\000"
4896 /* 11104 */ "G_BRCOND\000"
4897 /* 11113 */ "G_ATOMICRMW_USUB_COND\000"
4898 /* 11135 */ "G_LLROUND\000"
4899 /* 11145 */ "G_LROUND\000"
4900 /* 11154 */ "G_INTRINSIC_ROUND\000"
4901 /* 11172 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
4902 /* 11198 */ "LOAD_STACK_GUARD\000"
4903 /* 11215 */ "PSEUDO_PROBE\000"
4904 /* 11228 */ "G_SSUBE\000"
4905 /* 11236 */ "G_USUBE\000"
4906 /* 11244 */ "ATOMIC_FENCE\000"
4907 /* 11257 */ "G_FENCE\000"
4908 /* 11265 */ "ARITH_FENCE\000"
4909 /* 11277 */ "COMPILER_FENCE\000"
4910 /* 11292 */ "REG_SEQUENCE\000"
4911 /* 11305 */ "G_SADDE\000"
4912 /* 11313 */ "G_UADDE\000"
4913 /* 11321 */ "G_GET_FPMODE\000"
4914 /* 11334 */ "G_RESET_FPMODE\000"
4915 /* 11349 */ "G_SET_FPMODE\000"
4916 /* 11362 */ "G_FMINNUM_IEEE\000"
4917 /* 11377 */ "G_FMAXNUM_IEEE\000"
4918 /* 11392 */ "G_VSCALE\000"
4919 /* 11401 */ "DEBUG_UNREACHABLE\000"
4920 /* 11419 */ "G_JUMP_TABLE\000"
4921 /* 11432 */ "END_TRY_TABLE\000"
4922 /* 11446 */ "BUNDLE\000"
4923 /* 11453 */ "SHUFFLE\000"
4924 /* 11461 */ "RELAXED_SWIZZLE\000"
4925 /* 11477 */ "G_MEMCPY_INLINE\000"
4926 /* 11493 */ "LOCAL_ESCAPE\000"
4927 /* 11506 */ "G_STACKRESTORE\000"
4928 /* 11521 */ "G_INDEXED_STORE\000"
4929 /* 11537 */ "G_STORE\000"
4930 /* 11545 */ "ELSE\000"
4931 /* 11550 */ "G_BITREVERSE\000"
4932 /* 11563 */ "FAKE_USE\000"
4933 /* 11572 */ "DELEGATE\000"
4934 /* 11581 */ "DBG_VALUE\000"
4935 /* 11591 */ "G_GLOBAL_VALUE\000"
4936 /* 11606 */ "G_PTRAUTH_GLOBAL_VALUE\000"
4937 /* 11629 */ "CONVERGENCECTRL_GLUE\000"
4938 /* 11650 */ "ANYTRUE\000"
4939 /* 11658 */ "G_STACKSAVE\000"
4940 /* 11670 */ "G_MEMMOVE\000"
4941 /* 11680 */ "G_FREEZE\000"
4942 /* 11689 */ "G_FCANONICALIZE\000"
4943 /* 11705 */ "TABLE_SIZE\000"
4944 /* 11716 */ "G_CTLZ_ZERO_UNDEF\000"
4945 /* 11734 */ "G_CTTZ_ZERO_UNDEF\000"
4946 /* 11752 */ "INIT_UNDEF\000"
4947 /* 11763 */ "G_IMPLICIT_DEF\000"
4948 /* 11778 */ "LOCAL_TEE_FUNCREF\000"
4949 /* 11796 */ "TABLE_FILL_FUNCREF\000"
4950 /* 11815 */ "REF_NULL_FUNCREF\000"
4951 /* 11832 */ "REF_IS_NULL_FUNCREF\000"
4952 /* 11852 */ "DROP_FUNCREF\000"
4953 /* 11865 */ "SELECT_FUNCREF\000"
4954 /* 11880 */ "TABLE_GET_FUNCREF\000"
4955 /* 11898 */ "GLOBAL_GET_FUNCREF\000"
4956 /* 11917 */ "LOCAL_GET_FUNCREF\000"
4957 /* 11935 */ "TABLE_SET_FUNCREF\000"
4958 /* 11953 */ "GLOBAL_SET_FUNCREF\000"
4959 /* 11972 */ "LOCAL_SET_FUNCREF\000"
4960 /* 11990 */ "TABLE_GROW_FUNCREF\000"
4961 /* 12009 */ "COPY_FUNCREF\000"
4962 /* 12022 */ "LOCAL_TEE_EXTERNREF\000"
4963 /* 12042 */ "TABLE_FILL_EXTERNREF\000"
4964 /* 12063 */ "REF_NULL_EXTERNREF\000"
4965 /* 12082 */ "REF_IS_NULL_EXTERNREF\000"
4966 /* 12104 */ "DROP_EXTERNREF\000"
4967 /* 12119 */ "SELECT_EXTERNREF\000"
4968 /* 12136 */ "TABLE_GET_EXTERNREF\000"
4969 /* 12156 */ "GLOBAL_GET_EXTERNREF\000"
4970 /* 12177 */ "LOCAL_GET_EXTERNREF\000"
4971 /* 12197 */ "TABLE_SET_EXTERNREF\000"
4972 /* 12217 */ "GLOBAL_SET_EXTERNREF\000"
4973 /* 12238 */ "LOCAL_SET_EXTERNREF\000"
4974 /* 12258 */ "TABLE_GROW_EXTERNREF\000"
4975 /* 12279 */ "COPY_EXTERNREF\000"
4976 /* 12294 */ "LOCAL_TEE_EXNREF\000"
4977 /* 12311 */ "TABLE_FILL_EXNREF\000"
4978 /* 12329 */ "REF_NULL_EXNREF\000"
4979 /* 12345 */ "REF_IS_NULL_EXNREF\000"
4980 /* 12364 */ "DROP_EXNREF\000"
4981 /* 12376 */ "SELECT_EXNREF\000"
4982 /* 12390 */ "TABLE_GET_EXNREF\000"
4983 /* 12407 */ "GLOBAL_GET_EXNREF\000"
4984 /* 12425 */ "LOCAL_GET_EXNREF\000"
4985 /* 12442 */ "TABLE_SET_EXNREF\000"
4986 /* 12459 */ "GLOBAL_SET_EXNREF\000"
4987 /* 12477 */ "LOCAL_SET_EXNREF\000"
4988 /* 12494 */ "TABLE_GROW_EXNREF\000"
4989 /* 12512 */ "COPY_EXNREF\000"
4990 /* 12524 */ "CATCH_REF\000"
4991 /* 12534 */ "CATCH_ALL_REF\000"
4992 /* 12548 */ "DBG_INSTR_REF\000"
4993 /* 12562 */ "THROW_REF\000"
4994 /* 12572 */ "END_IF\000"
4995 /* 12579 */ "BR_IF\000"
4996 /* 12585 */ "G_FNEG\000"
4997 /* 12592 */ "EXTRACT_SUBREG\000"
4998 /* 12607 */ "INSERT_SUBREG\000"
4999 /* 12621 */ "G_SEXT_INREG\000"
5000 /* 12634 */ "SUBREG_TO_REG\000"
5001 /* 12648 */ "G_ATOMIC_CMPXCHG\000"
5002 /* 12665 */ "G_ATOMICRMW_XCHG\000"
5003 /* 12682 */ "G_FLOG\000"
5004 /* 12689 */ "G_VAARG\000"
5005 /* 12697 */ "PREALLOCATED_ARG\000"
5006 /* 12714 */ "CATCH\000"
5007 /* 12720 */ "G_PREFETCH\000"
5008 /* 12731 */ "G_SMULH\000"
5009 /* 12739 */ "G_UMULH\000"
5010 /* 12747 */ "G_FTANH\000"
5011 /* 12755 */ "G_FSINH\000"
5012 /* 12763 */ "G_FCOSH\000"
5013 /* 12771 */ "DBG_PHI\000"
5014 /* 12779 */ "G_FPTOSI\000"
5015 /* 12788 */ "G_FPTOUI\000"
5016 /* 12797 */ "G_FPOWI\000"
5017 /* 12805 */ "END_BLOCK\000"
5018 /* 12815 */ "G_PTRMASK\000"
5019 /* 12825 */ "GC_LABEL\000"
5020 /* 12834 */ "DBG_LABEL\000"
5021 /* 12844 */ "EH_LABEL\000"
5022 /* 12853 */ "ANNOTATION_LABEL\000"
5023 /* 12870 */ "ICALL_BRANCH_FUNNEL\000"
5024 /* 12890 */ "G_FSHL\000"
5025 /* 12897 */ "G_SHL\000"
5026 /* 12903 */ "G_FCEIL\000"
5027 /* 12911 */ "PATCHABLE_TAIL_CALL\000"
5028 /* 12931 */ "RET_CALL\000"
5029 /* 12940 */ "PATCHABLE_TYPED_EVENT_CALL\000"
5030 /* 12967 */ "PATCHABLE_EVENT_CALL\000"
5031 /* 12988 */ "FENTRY_CALL\000"
5032 /* 13000 */ "CATCH_ALL\000"
5033 /* 13010 */ "KILL\000"
5034 /* 13015 */ "G_CONSTANT_POOL\000"
5035 /* 13031 */ "G_ROTL\000"
5036 /* 13038 */ "G_VECREDUCE_FMUL\000"
5037 /* 13055 */ "G_FMUL\000"
5038 /* 13062 */ "G_VECREDUCE_SEQ_FMUL\000"
5039 /* 13083 */ "G_STRICT_FMUL\000"
5040 /* 13097 */ "G_VECREDUCE_MUL\000"
5041 /* 13113 */ "G_MUL\000"
5042 /* 13119 */ "G_FREM\000"
5043 /* 13126 */ "G_STRICT_FREM\000"
5044 /* 13140 */ "G_SREM\000"
5045 /* 13147 */ "G_UREM\000"
5046 /* 13154 */ "G_SDIVREM\000"
5047 /* 13164 */ "G_UDIVREM\000"
5048 /* 13174 */ "INLINEASM\000"
5049 /* 13184 */ "G_VECREDUCE_FMINIMUM\000"
5050 /* 13205 */ "G_FMINIMUM\000"
5051 /* 13216 */ "G_ATOMICRMW_FMINIMUM\000"
5052 /* 13237 */ "G_VECREDUCE_FMAXIMUM\000"
5053 /* 13258 */ "G_FMAXIMUM\000"
5054 /* 13269 */ "G_ATOMICRMW_FMAXIMUM\000"
5055 /* 13290 */ "G_FMINIMUMNUM\000"
5056 /* 13304 */ "G_FMAXIMUMNUM\000"
5057 /* 13318 */ "G_FMINNUM\000"
5058 /* 13328 */ "G_FMAXNUM\000"
5059 /* 13338 */ "G_FATAN\000"
5060 /* 13346 */ "G_FTAN\000"
5061 /* 13353 */ "G_INTRINSIC_ROUNDEVEN\000"
5062 /* 13375 */ "G_ASSERT_ALIGN\000"
5063 /* 13390 */ "G_FCOPYSIGN\000"
5064 /* 13402 */ "G_VECREDUCE_FMIN\000"
5065 /* 13419 */ "G_ATOMICRMW_FMIN\000"
5066 /* 13436 */ "G_VECREDUCE_SMIN\000"
5067 /* 13453 */ "G_SMIN\000"
5068 /* 13460 */ "G_VECREDUCE_UMIN\000"
5069 /* 13477 */ "G_UMIN\000"
5070 /* 13484 */ "G_ATOMICRMW_UMIN\000"
5071 /* 13501 */ "G_ATOMICRMW_MIN\000"
5072 /* 13517 */ "G_FASIN\000"
5073 /* 13525 */ "G_FSIN\000"
5074 /* 13532 */ "END_FUNCTION\000"
5075 /* 13545 */ "CFI_INSTRUCTION\000"
5076 /* 13561 */ "FALLTHROUGH_RETURN\000"
5077 /* 13580 */ "ADJCALLSTACKDOWN\000"
5078 /* 13597 */ "G_SSUBO\000"
5079 /* 13605 */ "G_USUBO\000"
5080 /* 13613 */ "G_SADDO\000"
5081 /* 13621 */ "G_UADDO\000"
5082 /* 13629 */ "JUMP_TABLE_DEBUG_INFO\000"
5083 /* 13651 */ "G_SMULO\000"
5084 /* 13659 */ "G_UMULO\000"
5085 /* 13667 */ "G_BZERO\000"
5086 /* 13675 */ "STACKMAP\000"
5087 /* 13684 */ "G_DEBUGTRAP\000"
5088 /* 13696 */ "G_UBSANTRAP\000"
5089 /* 13708 */ "G_TRAP\000"
5090 /* 13715 */ "G_ATOMICRMW_UDEC_WRAP\000"
5091 /* 13737 */ "G_ATOMICRMW_UINC_WRAP\000"
5092 /* 13759 */ "G_BSWAP\000"
5093 /* 13767 */ "G_SITOFP\000"
5094 /* 13776 */ "G_UITOFP\000"
5095 /* 13785 */ "G_FCMP\000"
5096 /* 13792 */ "G_ICMP\000"
5097 /* 13799 */ "G_SCMP\000"
5098 /* 13806 */ "G_UCMP\000"
5099 /* 13813 */ "NOP\000"
5100 /* 13817 */ "END_LOOP\000"
5101 /* 13826 */ "CONVERGENCECTRL_LOOP\000"
5102 /* 13847 */ "G_CTPOP\000"
5103 /* 13855 */ "DATA_DROP\000"
5104 /* 13865 */ "PATCHABLE_OP\000"
5105 /* 13878 */ "FAULTING_OP\000"
5106 /* 13890 */ "ADJCALLSTACKUP\000"
5107 /* 13905 */ "PREALLOCATED_SETUP\000"
5108 /* 13924 */ "G_FLDEXP\000"
5109 /* 13933 */ "G_STRICT_FLDEXP\000"
5110 /* 13949 */ "G_FEXP\000"
5111 /* 13956 */ "G_FFREXP\000"
5112 /* 13965 */ "G_BR\000"
5113 /* 13970 */ "INLINEASM_BR\000"
5114 /* 13983 */ "G_BLOCK_ADDR\000"
5115 /* 13996 */ "MEMBARRIER\000"
5116 /* 14007 */ "G_CONSTANT_FOLD_BARRIER\000"
5117 /* 14031 */ "PATCHABLE_FUNCTION_ENTER\000"
5118 /* 14056 */ "G_READCYCLECOUNTER\000"
5119 /* 14075 */ "G_READSTEADYCOUNTER\000"
5120 /* 14095 */ "G_READ_REGISTER\000"
5121 /* 14111 */ "G_WRITE_REGISTER\000"
5122 /* 14128 */ "G_ASHR\000"
5123 /* 14135 */ "G_FSHR\000"
5124 /* 14142 */ "G_LSHR\000"
5125 /* 14149 */ "CONVERGENCECTRL_ANCHOR\000"
5126 /* 14172 */ "G_FFLOOR\000"
5127 /* 14181 */ "G_EXTRACT_SUBVECTOR\000"
5128 /* 14201 */ "G_INSERT_SUBVECTOR\000"
5129 /* 14220 */ "G_BUILD_VECTOR\000"
5130 /* 14235 */ "G_SHUFFLE_VECTOR\000"
5131 /* 14252 */ "G_STEP_VECTOR\000"
5132 /* 14266 */ "G_SPLAT_VECTOR\000"
5133 /* 14281 */ "G_VECREDUCE_XOR\000"
5134 /* 14297 */ "G_XOR\000"
5135 /* 14303 */ "G_ATOMICRMW_XOR\000"
5136 /* 14319 */ "G_VECREDUCE_OR\000"
5137 /* 14334 */ "G_OR\000"
5138 /* 14339 */ "G_ATOMICRMW_OR\000"
5139 /* 14354 */ "G_ROTR\000"
5140 /* 14361 */ "G_INTTOPTR\000"
5141 /* 14372 */ "G_FABS\000"
5142 /* 14379 */ "G_ABS\000"
5143 /* 14385 */ "G_ABDS\000"
5144 /* 14392 */ "G_UNMERGE_VALUES\000"
5145 /* 14409 */ "G_MERGE_VALUES\000"
5146 /* 14424 */ "CALL_PARAMS\000"
5147 /* 14436 */ "G_FACOS\000"
5148 /* 14444 */ "G_FCOS\000"
5149 /* 14451 */ "G_FSINCOS\000"
5150 /* 14461 */ "G_CONCAT_VECTORS\000"
5151 /* 14478 */ "COPY_TO_REGCLASS\000"
5152 /* 14495 */ "G_IS_FPCLASS\000"
5153 /* 14508 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
5154 /* 14538 */ "BR_UNLESS\000"
5155 /* 14548 */ "G_VECTOR_COMPRESS\000"
5156 /* 14566 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
5157 /* 14593 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
5158 /* 14631 */ "RET_CALL_RESULTS\000"
5159 /* 14648 */ "LOAD_F16_F32_A32_S\000"
5160 /* 14667 */ "STORE_F16_F32_A32_S\000"
5161 /* 14687 */ "LOAD_F32_A32_S\000"
5162 /* 14702 */ "STORE_F32_A32_S\000"
5163 /* 14718 */ "ATOMIC_STORE16_I32_A32_S\000"
5164 /* 14743 */ "ATOMIC_STORE8_I32_A32_S\000"
5165 /* 14767 */ "ATOMIC_RMW16_U_SUB_I32_A32_S\000"
5166 /* 14796 */ "ATOMIC_RMW8_U_SUB_I32_A32_S\000"
5167 /* 14824 */ "ATOMIC_RMW_SUB_I32_A32_S\000"
5168 /* 14849 */ "ATOMIC_LOAD_I32_A32_S\000"
5169 /* 14871 */ "ATOMIC_RMW16_U_ADD_I32_A32_S\000"
5170 /* 14900 */ "ATOMIC_RMW8_U_ADD_I32_A32_S\000"
5171 /* 14928 */ "ATOMIC_RMW_ADD_I32_A32_S\000"
5172 /* 14953 */ "ATOMIC_RMW16_U_AND_I32_A32_S\000"
5173 /* 14982 */ "ATOMIC_RMW8_U_AND_I32_A32_S\000"
5174 /* 15010 */ "ATOMIC_RMW_AND_I32_A32_S\000"
5175 /* 15035 */ "ATOMIC_STORE_I32_A32_S\000"
5176 /* 15058 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32_S\000"
5177 /* 15091 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32_S\000"
5178 /* 15123 */ "ATOMIC_RMW_CMPXCHG_I32_A32_S\000"
5179 /* 15152 */ "ATOMIC_RMW16_U_XCHG_I32_A32_S\000"
5180 /* 15182 */ "ATOMIC_RMW8_U_XCHG_I32_A32_S\000"
5181 /* 15211 */ "ATOMIC_RMW_XCHG_I32_A32_S\000"
5182 /* 15237 */ "ATOMIC_RMW16_U_XOR_I32_A32_S\000"
5183 /* 15266 */ "ATOMIC_RMW8_U_XOR_I32_A32_S\000"
5184 /* 15294 */ "ATOMIC_RMW_XOR_I32_A32_S\000"
5185 /* 15319 */ "ATOMIC_RMW16_U_OR_I32_A32_S\000"
5186 /* 15347 */ "ATOMIC_RMW8_U_OR_I32_A32_S\000"
5187 /* 15374 */ "ATOMIC_RMW_OR_I32_A32_S\000"
5188 /* 15398 */ "LOAD16_S_I32_A32_S\000"
5189 /* 15417 */ "LOAD8_S_I32_A32_S\000"
5190 /* 15435 */ "ATOMIC_LOAD16_U_I32_A32_S\000"
5191 /* 15461 */ "ATOMIC_LOAD8_U_I32_A32_S\000"
5192 /* 15486 */ "MEMORY_ATOMIC_WAIT32_A32_S\000"
5193 /* 15513 */ "LOAD_LANE_32_A32_S\000"
5194 /* 15532 */ "LOAD_ZERO_32_A32_S\000"
5195 /* 15551 */ "STORE_LANE_I64x2_A32_S\000"
5196 /* 15574 */ "LOAD_EXTEND_S_I64x2_A32_S\000"
5197 /* 15600 */ "LOAD_EXTEND_U_I64x2_A32_S\000"
5198 /* 15626 */ "LOAD_F64_A32_S\000"
5199 /* 15641 */ "STORE_F64_A32_S\000"
5200 /* 15657 */ "ATOMIC_STORE32_I64_A32_S\000"
5201 /* 15682 */ "ATOMIC_STORE16_I64_A32_S\000"
5202 /* 15707 */ "ATOMIC_STORE8_I64_A32_S\000"
5203 /* 15731 */ "ATOMIC_RMW32_U_SUB_I64_A32_S\000"
5204 /* 15760 */ "ATOMIC_RMW16_U_SUB_I64_A32_S\000"
5205 /* 15789 */ "ATOMIC_RMW8_U_SUB_I64_A32_S\000"
5206 /* 15817 */ "ATOMIC_RMW_SUB_I64_A32_S\000"
5207 /* 15842 */ "ATOMIC_LOAD_I64_A32_S\000"
5208 /* 15864 */ "ATOMIC_RMW32_U_ADD_I64_A32_S\000"
5209 /* 15893 */ "ATOMIC_RMW16_U_ADD_I64_A32_S\000"
5210 /* 15922 */ "ATOMIC_RMW8_U_ADD_I64_A32_S\000"
5211 /* 15950 */ "ATOMIC_RMW_ADD_I64_A32_S\000"
5212 /* 15975 */ "ATOMIC_RMW32_U_AND_I64_A32_S\000"
5213 /* 16004 */ "ATOMIC_RMW16_U_AND_I64_A32_S\000"
5214 /* 16033 */ "ATOMIC_RMW8_U_AND_I64_A32_S\000"
5215 /* 16061 */ "ATOMIC_RMW_AND_I64_A32_S\000"
5216 /* 16086 */ "ATOMIC_STORE_I64_A32_S\000"
5217 /* 16109 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32_S\000"
5218 /* 16142 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32_S\000"
5219 /* 16175 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32_S\000"
5220 /* 16207 */ "ATOMIC_RMW_CMPXCHG_I64_A32_S\000"
5221 /* 16236 */ "ATOMIC_RMW32_U_XCHG_I64_A32_S\000"
5222 /* 16266 */ "ATOMIC_RMW16_U_XCHG_I64_A32_S\000"
5223 /* 16296 */ "ATOMIC_RMW8_U_XCHG_I64_A32_S\000"
5224 /* 16325 */ "ATOMIC_RMW_XCHG_I64_A32_S\000"
5225 /* 16351 */ "ATOMIC_RMW32_U_XOR_I64_A32_S\000"
5226 /* 16380 */ "ATOMIC_RMW16_U_XOR_I64_A32_S\000"
5227 /* 16409 */ "ATOMIC_RMW8_U_XOR_I64_A32_S\000"
5228 /* 16437 */ "ATOMIC_RMW_XOR_I64_A32_S\000"
5229 /* 16462 */ "ATOMIC_RMW32_U_OR_I64_A32_S\000"
5230 /* 16490 */ "ATOMIC_RMW16_U_OR_I64_A32_S\000"
5231 /* 16518 */ "ATOMIC_RMW8_U_OR_I64_A32_S\000"
5232 /* 16545 */ "ATOMIC_RMW_OR_I64_A32_S\000"
5233 /* 16569 */ "LOAD32_S_I64_A32_S\000"
5234 /* 16588 */ "LOAD16_S_I64_A32_S\000"
5235 /* 16607 */ "LOAD8_S_I64_A32_S\000"
5236 /* 16625 */ "ATOMIC_LOAD32_U_I64_A32_S\000"
5237 /* 16651 */ "ATOMIC_LOAD16_U_I64_A32_S\000"
5238 /* 16677 */ "ATOMIC_LOAD8_U_I64_A32_S\000"
5239 /* 16702 */ "MEMORY_ATOMIC_WAIT64_A32_S\000"
5240 /* 16729 */ "LOAD_LANE_64_A32_S\000"
5241 /* 16748 */ "LOAD_ZERO_64_A32_S\000"
5242 /* 16767 */ "STORE_LANE_I32x4_A32_S\000"
5243 /* 16790 */ "LOAD_EXTEND_S_I32x4_A32_S\000"
5244 /* 16816 */ "LOAD_EXTEND_U_I32x4_A32_S\000"
5245 /* 16842 */ "LOAD_LANE_16_A32_S\000"
5246 /* 16861 */ "STORE_LANE_I8x16_A32_S\000"
5247 /* 16884 */ "LOAD_V128_A32_S\000"
5248 /* 16900 */ "STORE_V128_A32_S\000"
5249 /* 16917 */ "LOAD_LANE_8_A32_S\000"
5250 /* 16935 */ "STORE_LANE_I16x8_A32_S\000"
5251 /* 16958 */ "LOAD_EXTEND_S_I16x8_A32_S\000"
5252 /* 16984 */ "LOAD_EXTEND_U_I16x8_A32_S\000"
5253 /* 17010 */ "anonymous_8818MEMORY_SIZE_A32_S\000"
5254 /* 17042 */ "MEMORY_FILL_A32_S\000"
5255 /* 17060 */ "LOAD32_SPLAT_A32_S\000"
5256 /* 17079 */ "LOAD64_SPLAT_A32_S\000"
5257 /* 17098 */ "LOAD16_SPLAT_A32_S\000"
5258 /* 17117 */ "LOAD8_SPLAT_A32_S\000"
5259 /* 17135 */ "MEMSET_A32_S\000"
5260 /* 17148 */ "MEMORY_INIT_A32_S\000"
5261 /* 17166 */ "anonymous_8818MEMORY_GROW_A32_S\000"
5262 /* 17198 */ "MEMORY_ATOMIC_NOTIFY_A32_S\000"
5263 /* 17225 */ "MEMCPY_A32_S\000"
5264 /* 17238 */ "MEMORY_COPY_A32_S\000"
5265 /* 17256 */ "FP_TO_SINT_I32_F32_S\000"
5266 /* 17277 */ "FP_TO_UINT_I32_F32_S\000"
5267 /* 17298 */ "FP_TO_SINT_I64_F32_S\000"
5268 /* 17319 */ "FP_TO_UINT_I64_F32_S\000"
5269 /* 17340 */ "SUB_F32_S\000"
5270 /* 17350 */ "TRUNC_F32_S\000"
5271 /* 17362 */ "ADD_F32_S\000"
5272 /* 17372 */ "LOCAL_TEE_F32_S\000"
5273 /* 17388 */ "GE_F32_S\000"
5274 /* 17397 */ "LE_F32_S\000"
5275 /* 17406 */ "NE_F32_S\000"
5276 /* 17415 */ "F64_PROMOTE_F32_S\000"
5277 /* 17433 */ "NEG_F32_S\000"
5278 /* 17443 */ "CEIL_F32_S\000"
5279 /* 17454 */ "MUL_F32_S\000"
5280 /* 17464 */ "COPYSIGN_F32_S\000"
5281 /* 17479 */ "MIN_F32_S\000"
5282 /* 17489 */ "DROP_F32_S\000"
5283 /* 17500 */ "EQ_F32_S\000"
5284 /* 17509 */ "FLOOR_F32_S\000"
5285 /* 17521 */ "ABS_F32_S\000"
5286 /* 17531 */ "I32_TRUNC_S_F32_S\000"
5287 /* 17549 */ "I64_TRUNC_S_F32_S\000"
5288 /* 17567 */ "I32_TRUNC_S_SAT_F32_S\000"
5289 /* 17589 */ "I64_TRUNC_S_SAT_F32_S\000"
5290 /* 17611 */ "I32_TRUNC_U_SAT_F32_S\000"
5291 /* 17633 */ "I64_TRUNC_U_SAT_F32_S\000"
5292 /* 17655 */ "SELECT_F32_S\000"
5293 /* 17668 */ "GLOBAL_GET_F32_S\000"
5294 /* 17685 */ "LOCAL_GET_F32_S\000"
5295 /* 17701 */ "I32_REINTERPRET_F32_S\000"
5296 /* 17723 */ "GLOBAL_SET_F32_S\000"
5297 /* 17740 */ "LOCAL_SET_F32_S\000"
5298 /* 17756 */ "GT_F32_S\000"
5299 /* 17765 */ "LT_F32_S\000"
5300 /* 17774 */ "SQRT_F32_S\000"
5301 /* 17785 */ "NEAREST_F32_S\000"
5302 /* 17799 */ "CONST_F32_S\000"
5303 /* 17811 */ "I32_TRUNC_U_F32_S\000"
5304 /* 17829 */ "I64_TRUNC_U_F32_S\000"
5305 /* 17847 */ "DIV_F32_S\000"
5306 /* 17857 */ "MAX_F32_S\000"
5307 /* 17867 */ "COPY_F32_S\000"
5308 /* 17878 */ "SUB_I32_S\000"
5309 /* 17888 */ "ADD_I32_S\000"
5310 /* 17898 */ "AND_I32_S\000"
5311 /* 17908 */ "LOCAL_TEE_I32_S\000"
5312 /* 17924 */ "BR_TABLE_I32_S\000"
5313 /* 17939 */ "NE_I32_S\000"
5314 /* 17948 */ "SHL_I32_S\000"
5315 /* 17958 */ "ROTL_I32_S\000"
5316 /* 17969 */ "MUL_I32_S\000"
5317 /* 17979 */ "DROP_I32_S\000"
5318 /* 17990 */ "EQ_I32_S\000"
5319 /* 17999 */ "XOR_I32_S\000"
5320 /* 18009 */ "ROTR_I32_S\000"
5321 /* 18020 */ "I32_EXTEND16_S_I32_S\000"
5322 /* 18041 */ "I32_EXTEND8_S_I32_S\000"
5323 /* 18061 */ "I64_EXTEND_S_I32_S\000"
5324 /* 18080 */ "GE_S_I32_S\000"
5325 /* 18091 */ "LE_S_I32_S\000"
5326 /* 18102 */ "REM_S_I32_S\000"
5327 /* 18114 */ "SHR_S_I32_S\000"
5328 /* 18126 */ "GT_S_I32_S\000"
5329 /* 18137 */ "LT_S_I32_S\000"
5330 /* 18148 */ "F32_CONVERT_S_I32_S\000"
5331 /* 18168 */ "F64_CONVERT_S_I32_S\000"
5332 /* 18188 */ "DIV_S_I32_S\000"
5333 /* 18200 */ "SELECT_I32_S\000"
5334 /* 18213 */ "GLOBAL_GET_I32_S\000"
5335 /* 18230 */ "LOCAL_GET_I32_S\000"
5336 /* 18246 */ "F32_REINTERPRET_I32_S\000"
5337 /* 18268 */ "GLOBAL_SET_I32_S\000"
5338 /* 18285 */ "LOCAL_SET_I32_S\000"
5339 /* 18301 */ "POPCNT_I32_S\000"
5340 /* 18314 */ "CONST_I32_S\000"
5341 /* 18326 */ "I64_EXTEND_U_I32_S\000"
5342 /* 18345 */ "GE_U_I32_S\000"
5343 /* 18356 */ "LE_U_I32_S\000"
5344 /* 18367 */ "REM_U_I32_S\000"
5345 /* 18379 */ "SHR_U_I32_S\000"
5346 /* 18391 */ "GT_U_I32_S\000"
5347 /* 18402 */ "LT_U_I32_S\000"
5348 /* 18413 */ "F32_CONVERT_U_I32_S\000"
5349 /* 18433 */ "F64_CONVERT_U_I32_S\000"
5350 /* 18453 */ "DIV_U_I32_S\000"
5351 /* 18465 */ "COPY_I32_S\000"
5352 /* 18476 */ "CLZ_I32_S\000"
5353 /* 18486 */ "EQZ_I32_S\000"
5354 /* 18496 */ "CTZ_I32_S\000"
5355 /* 18506 */ "ARGUMENT_v4f32_S\000"
5356 /* 18523 */ "ARGUMENT_f32_S\000"
5357 /* 18538 */ "ARGUMENT_v4i32_S\000"
5358 /* 18555 */ "ARGUMENT_i32_S\000"
5359 /* 18570 */ "CONST_V128_F64x2_S\000"
5360 /* 18589 */ "SUB_F64x2_S\000"
5361 /* 18601 */ "TRUNC_F64x2_S\000"
5362 /* 18615 */ "NMADD_F64x2_S\000"
5363 /* 18629 */ "GE_F64x2_S\000"
5364 /* 18640 */ "LE_F64x2_S\000"
5365 /* 18651 */ "REPLACE_LANE_F64x2_S\000"
5366 /* 18672 */ "EXTRACT_LANE_F64x2_S\000"
5367 /* 18693 */ "NEG_F64x2_S\000"
5368 /* 18705 */ "CEIL_F64x2_S\000"
5369 /* 18718 */ "MUL_F64x2_S\000"
5370 /* 18730 */ "SIMD_RELAXED_FMIN_F64x2_S\000"
5371 /* 18756 */ "PMIN_F64x2_S\000"
5372 /* 18769 */ "EQ_F64x2_S\000"
5373 /* 18780 */ "FLOOR_F64x2_S\000"
5374 /* 18794 */ "ABS_F64x2_S\000"
5375 /* 18806 */ "SPLAT_F64x2_S\000"
5376 /* 18820 */ "GT_F64x2_S\000"
5377 /* 18831 */ "LT_F64x2_S\000"
5378 /* 18842 */ "SQRT_F64x2_S\000"
5379 /* 18855 */ "NEAREST_F64x2_S\000"
5380 /* 18871 */ "DIV_F64x2_S\000"
5381 /* 18883 */ "SIMD_RELAXED_FMAX_F64x2_S\000"
5382 /* 18909 */ "PMAX_F64x2_S\000"
5383 /* 18922 */ "convert_low_s_F64x2_S\000"
5384 /* 18944 */ "convert_low_u_F64x2_S\000"
5385 /* 18966 */ "promote_low_F64x2_S\000"
5386 /* 18986 */ "CONST_V128_I64x2_S\000"
5387 /* 19005 */ "SUB_I64x2_S\000"
5388 /* 19017 */ "ADD_I64x2_S\000"
5389 /* 19029 */ "REPLACE_LANE_I64x2_S\000"
5390 /* 19050 */ "EXTRACT_LANE_I64x2_S\000"
5391 /* 19071 */ "ALLTRUE_I64x2_S\000"
5392 /* 19087 */ "NEG_I64x2_S\000"
5393 /* 19099 */ "BITMASK_I64x2_S\000"
5394 /* 19115 */ "SHL_I64x2_S\000"
5395 /* 19127 */ "MUL_I64x2_S\000"
5396 /* 19139 */ "EQ_I64x2_S\000"
5397 /* 19150 */ "ABS_I64x2_S\000"
5398 /* 19162 */ "GE_S_I64x2_S\000"
5399 /* 19175 */ "LE_S_I64x2_S\000"
5400 /* 19188 */ "EXTMUL_HIGH_S_I64x2_S\000"
5401 /* 19210 */ "SHR_S_I64x2_S\000"
5402 /* 19224 */ "GT_S_I64x2_S\000"
5403 /* 19237 */ "LT_S_I64x2_S\000"
5404 /* 19250 */ "EXTMUL_LOW_S_I64x2_S\000"
5405 /* 19271 */ "SPLAT_I64x2_S\000"
5406 /* 19285 */ "LANESELECT_I64x2_S\000"
5407 /* 19304 */ "EXTMUL_HIGH_U_I64x2_S\000"
5408 /* 19326 */ "SHR_U_I64x2_S\000"
5409 /* 19340 */ "EXTMUL_LOW_U_I64x2_S\000"
5410 /* 19361 */ "extend_high_s_I64x2_S\000"
5411 /* 19383 */ "extend_low_s_I64x2_S\000"
5412 /* 19404 */ "extend_high_u_I64x2_S\000"
5413 /* 19426 */ "extend_low_u_I64x2_S\000"
5414 /* 19447 */ "LOAD_F16_F32_A64_S\000"
5415 /* 19466 */ "STORE_F16_F32_A64_S\000"
5416 /* 19486 */ "LOAD_F32_A64_S\000"
5417 /* 19501 */ "STORE_F32_A64_S\000"
5418 /* 19517 */ "ATOMIC_STORE16_I32_A64_S\000"
5419 /* 19542 */ "ATOMIC_STORE8_I32_A64_S\000"
5420 /* 19566 */ "ATOMIC_RMW16_U_SUB_I32_A64_S\000"
5421 /* 19595 */ "ATOMIC_RMW8_U_SUB_I32_A64_S\000"
5422 /* 19623 */ "ATOMIC_RMW_SUB_I32_A64_S\000"
5423 /* 19648 */ "ATOMIC_LOAD_I32_A64_S\000"
5424 /* 19670 */ "ATOMIC_RMW16_U_ADD_I32_A64_S\000"
5425 /* 19699 */ "ATOMIC_RMW8_U_ADD_I32_A64_S\000"
5426 /* 19727 */ "ATOMIC_RMW_ADD_I32_A64_S\000"
5427 /* 19752 */ "ATOMIC_RMW16_U_AND_I32_A64_S\000"
5428 /* 19781 */ "ATOMIC_RMW8_U_AND_I32_A64_S\000"
5429 /* 19809 */ "ATOMIC_RMW_AND_I32_A64_S\000"
5430 /* 19834 */ "ATOMIC_STORE_I32_A64_S\000"
5431 /* 19857 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64_S\000"
5432 /* 19890 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64_S\000"
5433 /* 19922 */ "ATOMIC_RMW_CMPXCHG_I32_A64_S\000"
5434 /* 19951 */ "ATOMIC_RMW16_U_XCHG_I32_A64_S\000"
5435 /* 19981 */ "ATOMIC_RMW8_U_XCHG_I32_A64_S\000"
5436 /* 20010 */ "ATOMIC_RMW_XCHG_I32_A64_S\000"
5437 /* 20036 */ "ATOMIC_RMW16_U_XOR_I32_A64_S\000"
5438 /* 20065 */ "ATOMIC_RMW8_U_XOR_I32_A64_S\000"
5439 /* 20093 */ "ATOMIC_RMW_XOR_I32_A64_S\000"
5440 /* 20118 */ "ATOMIC_RMW16_U_OR_I32_A64_S\000"
5441 /* 20146 */ "ATOMIC_RMW8_U_OR_I32_A64_S\000"
5442 /* 20173 */ "ATOMIC_RMW_OR_I32_A64_S\000"
5443 /* 20197 */ "LOAD16_S_I32_A64_S\000"
5444 /* 20216 */ "LOAD8_S_I32_A64_S\000"
5445 /* 20234 */ "ATOMIC_LOAD16_U_I32_A64_S\000"
5446 /* 20260 */ "ATOMIC_LOAD8_U_I32_A64_S\000"
5447 /* 20285 */ "MEMORY_ATOMIC_WAIT32_A64_S\000"
5448 /* 20312 */ "LOAD_LANE_32_A64_S\000"
5449 /* 20331 */ "LOAD_ZERO_32_A64_S\000"
5450 /* 20350 */ "STORE_LANE_I64x2_A64_S\000"
5451 /* 20373 */ "LOAD_EXTEND_S_I64x2_A64_S\000"
5452 /* 20399 */ "LOAD_EXTEND_U_I64x2_A64_S\000"
5453 /* 20425 */ "LOAD_F64_A64_S\000"
5454 /* 20440 */ "STORE_F64_A64_S\000"
5455 /* 20456 */ "ATOMIC_STORE32_I64_A64_S\000"
5456 /* 20481 */ "ATOMIC_STORE16_I64_A64_S\000"
5457 /* 20506 */ "ATOMIC_STORE8_I64_A64_S\000"
5458 /* 20530 */ "ATOMIC_RMW32_U_SUB_I64_A64_S\000"
5459 /* 20559 */ "ATOMIC_RMW16_U_SUB_I64_A64_S\000"
5460 /* 20588 */ "ATOMIC_RMW8_U_SUB_I64_A64_S\000"
5461 /* 20616 */ "ATOMIC_RMW_SUB_I64_A64_S\000"
5462 /* 20641 */ "ATOMIC_LOAD_I64_A64_S\000"
5463 /* 20663 */ "ATOMIC_RMW32_U_ADD_I64_A64_S\000"
5464 /* 20692 */ "ATOMIC_RMW16_U_ADD_I64_A64_S\000"
5465 /* 20721 */ "ATOMIC_RMW8_U_ADD_I64_A64_S\000"
5466 /* 20749 */ "ATOMIC_RMW_ADD_I64_A64_S\000"
5467 /* 20774 */ "ATOMIC_RMW32_U_AND_I64_A64_S\000"
5468 /* 20803 */ "ATOMIC_RMW16_U_AND_I64_A64_S\000"
5469 /* 20832 */ "ATOMIC_RMW8_U_AND_I64_A64_S\000"
5470 /* 20860 */ "ATOMIC_RMW_AND_I64_A64_S\000"
5471 /* 20885 */ "ATOMIC_STORE_I64_A64_S\000"
5472 /* 20908 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64_S\000"
5473 /* 20941 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64_S\000"
5474 /* 20974 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64_S\000"
5475 /* 21006 */ "ATOMIC_RMW_CMPXCHG_I64_A64_S\000"
5476 /* 21035 */ "ATOMIC_RMW32_U_XCHG_I64_A64_S\000"
5477 /* 21065 */ "ATOMIC_RMW16_U_XCHG_I64_A64_S\000"
5478 /* 21095 */ "ATOMIC_RMW8_U_XCHG_I64_A64_S\000"
5479 /* 21124 */ "ATOMIC_RMW_XCHG_I64_A64_S\000"
5480 /* 21150 */ "ATOMIC_RMW32_U_XOR_I64_A64_S\000"
5481 /* 21179 */ "ATOMIC_RMW16_U_XOR_I64_A64_S\000"
5482 /* 21208 */ "ATOMIC_RMW8_U_XOR_I64_A64_S\000"
5483 /* 21236 */ "ATOMIC_RMW_XOR_I64_A64_S\000"
5484 /* 21261 */ "ATOMIC_RMW32_U_OR_I64_A64_S\000"
5485 /* 21289 */ "ATOMIC_RMW16_U_OR_I64_A64_S\000"
5486 /* 21317 */ "ATOMIC_RMW8_U_OR_I64_A64_S\000"
5487 /* 21344 */ "ATOMIC_RMW_OR_I64_A64_S\000"
5488 /* 21368 */ "LOAD32_S_I64_A64_S\000"
5489 /* 21387 */ "LOAD16_S_I64_A64_S\000"
5490 /* 21406 */ "LOAD8_S_I64_A64_S\000"
5491 /* 21424 */ "ATOMIC_LOAD32_U_I64_A64_S\000"
5492 /* 21450 */ "ATOMIC_LOAD16_U_I64_A64_S\000"
5493 /* 21476 */ "ATOMIC_LOAD8_U_I64_A64_S\000"
5494 /* 21501 */ "MEMORY_ATOMIC_WAIT64_A64_S\000"
5495 /* 21528 */ "LOAD_LANE_64_A64_S\000"
5496 /* 21547 */ "LOAD_ZERO_64_A64_S\000"
5497 /* 21566 */ "STORE_LANE_I32x4_A64_S\000"
5498 /* 21589 */ "LOAD_EXTEND_S_I32x4_A64_S\000"
5499 /* 21615 */ "LOAD_EXTEND_U_I32x4_A64_S\000"
5500 /* 21641 */ "LOAD_LANE_16_A64_S\000"
5501 /* 21660 */ "STORE_LANE_I8x16_A64_S\000"
5502 /* 21683 */ "LOAD_V128_A64_S\000"
5503 /* 21699 */ "STORE_V128_A64_S\000"
5504 /* 21716 */ "LOAD_LANE_8_A64_S\000"
5505 /* 21734 */ "STORE_LANE_I16x8_A64_S\000"
5506 /* 21757 */ "LOAD_EXTEND_S_I16x8_A64_S\000"
5507 /* 21783 */ "LOAD_EXTEND_U_I16x8_A64_S\000"
5508 /* 21809 */ "anonymous_8819MEMORY_SIZE_A64_S\000"
5509 /* 21841 */ "MEMORY_FILL_A64_S\000"
5510 /* 21859 */ "LOAD32_SPLAT_A64_S\000"
5511 /* 21878 */ "LOAD64_SPLAT_A64_S\000"
5512 /* 21897 */ "LOAD16_SPLAT_A64_S\000"
5513 /* 21916 */ "LOAD8_SPLAT_A64_S\000"
5514 /* 21934 */ "MEMSET_A64_S\000"
5515 /* 21947 */ "MEMORY_INIT_A64_S\000"
5516 /* 21965 */ "anonymous_8819MEMORY_GROW_A64_S\000"
5517 /* 21997 */ "MEMORY_ATOMIC_NOTIFY_A64_S\000"
5518 /* 22024 */ "MEMCPY_A64_S\000"
5519 /* 22037 */ "MEMORY_COPY_A64_S\000"
5520 /* 22055 */ "FP_TO_SINT_I32_F64_S\000"
5521 /* 22076 */ "FP_TO_UINT_I32_F64_S\000"
5522 /* 22097 */ "FP_TO_SINT_I64_F64_S\000"
5523 /* 22118 */ "FP_TO_UINT_I64_F64_S\000"
5524 /* 22139 */ "SUB_F64_S\000"
5525 /* 22149 */ "TRUNC_F64_S\000"
5526 /* 22161 */ "ADD_F64_S\000"
5527 /* 22171 */ "LOCAL_TEE_F64_S\000"
5528 /* 22187 */ "GE_F64_S\000"
5529 /* 22196 */ "LE_F64_S\000"
5530 /* 22205 */ "NE_F64_S\000"
5531 /* 22214 */ "F32_DEMOTE_F64_S\000"
5532 /* 22231 */ "NEG_F64_S\000"
5533 /* 22241 */ "CEIL_F64_S\000"
5534 /* 22252 */ "MUL_F64_S\000"
5535 /* 22262 */ "COPYSIGN_F64_S\000"
5536 /* 22277 */ "MIN_F64_S\000"
5537 /* 22287 */ "DROP_F64_S\000"
5538 /* 22298 */ "EQ_F64_S\000"
5539 /* 22307 */ "FLOOR_F64_S\000"
5540 /* 22319 */ "ABS_F64_S\000"
5541 /* 22329 */ "I32_TRUNC_S_F64_S\000"
5542 /* 22347 */ "I64_TRUNC_S_F64_S\000"
5543 /* 22365 */ "I32_TRUNC_S_SAT_F64_S\000"
5544 /* 22387 */ "I64_TRUNC_S_SAT_F64_S\000"
5545 /* 22409 */ "I32_TRUNC_U_SAT_F64_S\000"
5546 /* 22431 */ "I64_TRUNC_U_SAT_F64_S\000"
5547 /* 22453 */ "SELECT_F64_S\000"
5548 /* 22466 */ "GLOBAL_GET_F64_S\000"
5549 /* 22483 */ "LOCAL_GET_F64_S\000"
5550 /* 22499 */ "I64_REINTERPRET_F64_S\000"
5551 /* 22521 */ "GLOBAL_SET_F64_S\000"
5552 /* 22538 */ "LOCAL_SET_F64_S\000"
5553 /* 22554 */ "GT_F64_S\000"
5554 /* 22563 */ "LT_F64_S\000"
5555 /* 22572 */ "SQRT_F64_S\000"
5556 /* 22583 */ "NEAREST_F64_S\000"
5557 /* 22597 */ "CONST_F64_S\000"
5558 /* 22609 */ "I32_TRUNC_U_F64_S\000"
5559 /* 22627 */ "I64_TRUNC_U_F64_S\000"
5560 /* 22645 */ "DIV_F64_S\000"
5561 /* 22655 */ "MAX_F64_S\000"
5562 /* 22665 */ "COPY_F64_S\000"
5563 /* 22676 */ "SUB_I64_S\000"
5564 /* 22686 */ "ADD_I64_S\000"
5565 /* 22696 */ "AND_I64_S\000"
5566 /* 22706 */ "LOCAL_TEE_I64_S\000"
5567 /* 22722 */ "BR_TABLE_I64_S\000"
5568 /* 22737 */ "NE_I64_S\000"
5569 /* 22746 */ "SHL_I64_S\000"
5570 /* 22756 */ "ROTL_I64_S\000"
5571 /* 22767 */ "MUL_I64_S\000"
5572 /* 22777 */ "I32_WRAP_I64_S\000"
5573 /* 22792 */ "DROP_I64_S\000"
5574 /* 22803 */ "EQ_I64_S\000"
5575 /* 22812 */ "XOR_I64_S\000"
5576 /* 22822 */ "ROTR_I64_S\000"
5577 /* 22833 */ "I64_EXTEND32_S_I64_S\000"
5578 /* 22854 */ "I64_EXTEND16_S_I64_S\000"
5579 /* 22875 */ "I64_EXTEND8_S_I64_S\000"
5580 /* 22895 */ "GE_S_I64_S\000"
5581 /* 22906 */ "LE_S_I64_S\000"
5582 /* 22917 */ "REM_S_I64_S\000"
5583 /* 22929 */ "SHR_S_I64_S\000"
5584 /* 22941 */ "GT_S_I64_S\000"
5585 /* 22952 */ "LT_S_I64_S\000"
5586 /* 22963 */ "F32_CONVERT_S_I64_S\000"
5587 /* 22983 */ "F64_CONVERT_S_I64_S\000"
5588 /* 23003 */ "DIV_S_I64_S\000"
5589 /* 23015 */ "SELECT_I64_S\000"
5590 /* 23028 */ "GLOBAL_GET_I64_S\000"
5591 /* 23045 */ "LOCAL_GET_I64_S\000"
5592 /* 23061 */ "F64_REINTERPRET_I64_S\000"
5593 /* 23083 */ "GLOBAL_SET_I64_S\000"
5594 /* 23100 */ "LOCAL_SET_I64_S\000"
5595 /* 23116 */ "POPCNT_I64_S\000"
5596 /* 23129 */ "CONST_I64_S\000"
5597 /* 23141 */ "GE_U_I64_S\000"
5598 /* 23152 */ "LE_U_I64_S\000"
5599 /* 23163 */ "REM_U_I64_S\000"
5600 /* 23175 */ "SHR_U_I64_S\000"
5601 /* 23187 */ "GT_U_I64_S\000"
5602 /* 23198 */ "LT_U_I64_S\000"
5603 /* 23209 */ "F32_CONVERT_U_I64_S\000"
5604 /* 23229 */ "F64_CONVERT_U_I64_S\000"
5605 /* 23249 */ "DIV_U_I64_S\000"
5606 /* 23261 */ "COPY_I64_S\000"
5607 /* 23272 */ "CLZ_I64_S\000"
5608 /* 23282 */ "EQZ_I64_S\000"
5609 /* 23292 */ "CTZ_I64_S\000"
5610 /* 23302 */ "ARGUMENT_v2f64_S\000"
5611 /* 23319 */ "ARGUMENT_f64_S\000"
5612 /* 23334 */ "ARGUMENT_v2i64_S\000"
5613 /* 23351 */ "ARGUMENT_i64_S\000"
5614 /* 23366 */ "CONST_V128_F32x4_S\000"
5615 /* 23385 */ "SUB_F32x4_S\000"
5616 /* 23397 */ "TRUNC_F32x4_S\000"
5617 /* 23411 */ "NMADD_F32x4_S\000"
5618 /* 23425 */ "GE_F32x4_S\000"
5619 /* 23436 */ "LE_F32x4_S\000"
5620 /* 23447 */ "REPLACE_LANE_F32x4_S\000"
5621 /* 23468 */ "EXTRACT_LANE_F32x4_S\000"
5622 /* 23489 */ "NEG_F32x4_S\000"
5623 /* 23501 */ "CEIL_F32x4_S\000"
5624 /* 23514 */ "MUL_F32x4_S\000"
5625 /* 23526 */ "SIMD_RELAXED_FMIN_F32x4_S\000"
5626 /* 23552 */ "PMIN_F32x4_S\000"
5627 /* 23565 */ "EQ_F32x4_S\000"
5628 /* 23576 */ "FLOOR_F32x4_S\000"
5629 /* 23590 */ "ABS_F32x4_S\000"
5630 /* 23602 */ "SPLAT_F32x4_S\000"
5631 /* 23616 */ "GT_F32x4_S\000"
5632 /* 23627 */ "LT_F32x4_S\000"
5633 /* 23638 */ "SQRT_F32x4_S\000"
5634 /* 23651 */ "NEAREST_F32x4_S\000"
5635 /* 23667 */ "DIV_F32x4_S\000"
5636 /* 23679 */ "SIMD_RELAXED_FMAX_F32x4_S\000"
5637 /* 23705 */ "PMAX_F32x4_S\000"
5638 /* 23718 */ "demote_zero_F32x4_S\000"
5639 /* 23738 */ "sint_to_fp_F32x4_S\000"
5640 /* 23757 */ "uint_to_fp_F32x4_S\000"
5641 /* 23776 */ "CONST_V128_I32x4_S\000"
5642 /* 23795 */ "SUB_I32x4_S\000"
5643 /* 23807 */ "ADD_I32x4_S\000"
5644 /* 23819 */ "REPLACE_LANE_I32x4_S\000"
5645 /* 23840 */ "EXTRACT_LANE_I32x4_S\000"
5646 /* 23861 */ "ALLTRUE_I32x4_S\000"
5647 /* 23877 */ "NEG_I32x4_S\000"
5648 /* 23889 */ "BITMASK_I32x4_S\000"
5649 /* 23905 */ "SHL_I32x4_S\000"
5650 /* 23917 */ "MUL_I32x4_S\000"
5651 /* 23929 */ "EQ_I32x4_S\000"
5652 /* 23940 */ "ABS_I32x4_S\000"
5653 /* 23952 */ "GE_S_I32x4_S\000"
5654 /* 23965 */ "LE_S_I32x4_S\000"
5655 /* 23978 */ "EXTMUL_HIGH_S_I32x4_S\000"
5656 /* 24000 */ "MIN_S_I32x4_S\000"
5657 /* 24014 */ "SHR_S_I32x4_S\000"
5658 /* 24028 */ "GT_S_I32x4_S\000"
5659 /* 24041 */ "LT_S_I32x4_S\000"
5660 /* 24054 */ "EXTMUL_LOW_S_I32x4_S\000"
5661 /* 24075 */ "MAX_S_I32x4_S\000"
5662 /* 24089 */ "SPLAT_I32x4_S\000"
5663 /* 24103 */ "LANESELECT_I32x4_S\000"
5664 /* 24122 */ "GE_U_I32x4_S\000"
5665 /* 24135 */ "LE_U_I32x4_S\000"
5666 /* 24148 */ "EXTMUL_HIGH_U_I32x4_S\000"
5667 /* 24170 */ "MIN_U_I32x4_S\000"
5668 /* 24184 */ "SHR_U_I32x4_S\000"
5669 /* 24198 */ "GT_U_I32x4_S\000"
5670 /* 24211 */ "LT_U_I32x4_S\000"
5671 /* 24224 */ "EXTMUL_LOW_U_I32x4_S\000"
5672 /* 24245 */ "MAX_U_I32x4_S\000"
5673 /* 24259 */ "int_wasm_relaxed_trunc_signed_I32x4_S\000"
5674 /* 24297 */ "int_wasm_extadd_pairwise_signed_I32x4_S\000"
5675 /* 24337 */ "int_wasm_relaxed_trunc_unsigned_I32x4_S\000"
5676 /* 24377 */ "int_wasm_extadd_pairwise_unsigned_I32x4_S\000"
5677 /* 24419 */ "int_wasm_relaxed_trunc_signed_zero_I32x4_S\000"
5678 /* 24462 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4_S\000"
5679 /* 24507 */ "extend_high_s_I32x4_S\000"
5680 /* 24529 */ "trunc_sat_zero_s_I32x4_S\000"
5681 /* 24554 */ "extend_low_s_I32x4_S\000"
5682 /* 24575 */ "fp_to_sint_I32x4_S\000"
5683 /* 24594 */ "fp_to_uint_I32x4_S\000"
5684 /* 24613 */ "extend_high_u_I32x4_S\000"
5685 /* 24635 */ "trunc_sat_zero_u_I32x4_S\000"
5686 /* 24660 */ "extend_low_u_I32x4_S\000"
5687 /* 24681 */ "ARGUMENT_v8f16_S\000"
5688 /* 24698 */ "ARGUMENT_v8i16_S\000"
5689 /* 24715 */ "CONST_V128_I8x16_S\000"
5690 /* 24734 */ "SUB_I8x16_S\000"
5691 /* 24746 */ "ADD_I8x16_S\000"
5692 /* 24758 */ "REPLACE_LANE_I8x16_S\000"
5693 /* 24779 */ "ALLTRUE_I8x16_S\000"
5694 /* 24795 */ "NEG_I8x16_S\000"
5695 /* 24807 */ "BITMASK_I8x16_S\000"
5696 /* 24823 */ "SHL_I8x16_S\000"
5697 /* 24835 */ "EQ_I8x16_S\000"
5698 /* 24846 */ "ABS_I8x16_S\000"
5699 /* 24858 */ "GE_S_I8x16_S\000"
5700 /* 24871 */ "LE_S_I8x16_S\000"
5701 /* 24884 */ "MIN_S_I8x16_S\000"
5702 /* 24898 */ "SHR_S_I8x16_S\000"
5703 /* 24912 */ "SUB_SAT_S_I8x16_S\000"
5704 /* 24930 */ "ADD_SAT_S_I8x16_S\000"
5705 /* 24948 */ "GT_S_I8x16_S\000"
5706 /* 24961 */ "LT_S_I8x16_S\000"
5707 /* 24974 */ "NARROW_S_I8x16_S\000"
5708 /* 24991 */ "MAX_S_I8x16_S\000"
5709 /* 25005 */ "SPLAT_I8x16_S\000"
5710 /* 25019 */ "LANESELECT_I8x16_S\000"
5711 /* 25038 */ "POPCNT_I8x16_S\000"
5712 /* 25053 */ "GE_U_I8x16_S\000"
5713 /* 25066 */ "LE_U_I8x16_S\000"
5714 /* 25079 */ "MIN_U_I8x16_S\000"
5715 /* 25093 */ "AVGR_U_I8x16_S\000"
5716 /* 25108 */ "SHR_U_I8x16_S\000"
5717 /* 25122 */ "SUB_SAT_U_I8x16_S\000"
5718 /* 25140 */ "ADD_SAT_U_I8x16_S\000"
5719 /* 25158 */ "GT_U_I8x16_S\000"
5720 /* 25171 */ "LT_U_I8x16_S\000"
5721 /* 25184 */ "NARROW_U_I8x16_S\000"
5722 /* 25201 */ "MAX_U_I8x16_S\000"
5723 /* 25215 */ "I64_SUB128_S\000"
5724 /* 25228 */ "I64_ADD128_S\000"
5725 /* 25241 */ "LOCAL_TEE_V128_S\000"
5726 /* 25258 */ "DROP_V128_S\000"
5727 /* 25270 */ "SELECT_V128_S\000"
5728 /* 25284 */ "GLOBAL_GET_V128_S\000"
5729 /* 25302 */ "LOCAL_GET_V128_S\000"
5730 /* 25319 */ "GLOBAL_SET_V128_S\000"
5731 /* 25337 */ "LOCAL_SET_V128_S\000"
5732 /* 25354 */ "COPY_V128_S\000"
5733 /* 25366 */ "ARGUMENT_v16i8_S\000"
5734 /* 25383 */ "SUB_F16x8_S\000"
5735 /* 25395 */ "TRUNC_F16x8_S\000"
5736 /* 25409 */ "NMADD_F16x8_S\000"
5737 /* 25423 */ "GE_F16x8_S\000"
5738 /* 25434 */ "LE_F16x8_S\000"
5739 /* 25445 */ "REPLACE_LANE_F16x8_S\000"
5740 /* 25466 */ "EXTRACT_LANE_F16x8_S\000"
5741 /* 25487 */ "NEG_F16x8_S\000"
5742 /* 25499 */ "CEIL_F16x8_S\000"
5743 /* 25512 */ "MUL_F16x8_S\000"
5744 /* 25524 */ "PMIN_F16x8_S\000"
5745 /* 25537 */ "EQ_F16x8_S\000"
5746 /* 25548 */ "FLOOR_F16x8_S\000"
5747 /* 25562 */ "ABS_F16x8_S\000"
5748 /* 25574 */ "SPLAT_F16x8_S\000"
5749 /* 25588 */ "GT_F16x8_S\000"
5750 /* 25599 */ "LT_F16x8_S\000"
5751 /* 25610 */ "SQRT_F16x8_S\000"
5752 /* 25623 */ "NEAREST_F16x8_S\000"
5753 /* 25639 */ "DIV_F16x8_S\000"
5754 /* 25651 */ "PMAX_F16x8_S\000"
5755 /* 25664 */ "sint_to_fp_F16x8_S\000"
5756 /* 25683 */ "uint_to_fp_F16x8_S\000"
5757 /* 25702 */ "CONST_V128_I16x8_S\000"
5758 /* 25721 */ "SUB_I16x8_S\000"
5759 /* 25733 */ "ADD_I16x8_S\000"
5760 /* 25745 */ "REPLACE_LANE_I16x8_S\000"
5761 /* 25766 */ "ALLTRUE_I16x8_S\000"
5762 /* 25782 */ "NEG_I16x8_S\000"
5763 /* 25794 */ "BITMASK_I16x8_S\000"
5764 /* 25810 */ "SHL_I16x8_S\000"
5765 /* 25822 */ "MUL_I16x8_S\000"
5766 /* 25834 */ "EQ_I16x8_S\000"
5767 /* 25845 */ "ABS_I16x8_S\000"
5768 /* 25857 */ "GE_S_I16x8_S\000"
5769 /* 25870 */ "LE_S_I16x8_S\000"
5770 /* 25883 */ "EXTMUL_HIGH_S_I16x8_S\000"
5771 /* 25905 */ "MIN_S_I16x8_S\000"
5772 /* 25919 */ "SHR_S_I16x8_S\000"
5773 /* 25933 */ "RELAXED_Q15MULR_S_I16x8_S\000"
5774 /* 25959 */ "SUB_SAT_S_I16x8_S\000"
5775 /* 25977 */ "ADD_SAT_S_I16x8_S\000"
5776 /* 25995 */ "Q15MULR_SAT_S_I16x8_S\000"
5777 /* 26017 */ "GT_S_I16x8_S\000"
5778 /* 26030 */ "LT_S_I16x8_S\000"
5779 /* 26043 */ "EXTMUL_LOW_S_I16x8_S\000"
5780 /* 26064 */ "NARROW_S_I16x8_S\000"
5781 /* 26081 */ "MAX_S_I16x8_S\000"
5782 /* 26095 */ "SPLAT_I16x8_S\000"
5783 /* 26109 */ "LANESELECT_I16x8_S\000"
5784 /* 26128 */ "GE_U_I16x8_S\000"
5785 /* 26141 */ "LE_U_I16x8_S\000"
5786 /* 26154 */ "EXTMUL_HIGH_U_I16x8_S\000"
5787 /* 26176 */ "MIN_U_I16x8_S\000"
5788 /* 26190 */ "AVGR_U_I16x8_S\000"
5789 /* 26205 */ "SHR_U_I16x8_S\000"
5790 /* 26219 */ "SUB_SAT_U_I16x8_S\000"
5791 /* 26237 */ "ADD_SAT_U_I16x8_S\000"
5792 /* 26255 */ "GT_U_I16x8_S\000"
5793 /* 26268 */ "LT_U_I16x8_S\000"
5794 /* 26281 */ "EXTMUL_LOW_U_I16x8_S\000"
5795 /* 26302 */ "NARROW_U_I16x8_S\000"
5796 /* 26319 */ "MAX_U_I16x8_S\000"
5797 /* 26333 */ "int_wasm_extadd_pairwise_signed_I16x8_S\000"
5798 /* 26373 */ "int_wasm_extadd_pairwise_unsigned_I16x8_S\000"
5799 /* 26415 */ "extend_high_s_I16x8_S\000"
5800 /* 26437 */ "extend_low_s_I16x8_S\000"
5801 /* 26458 */ "fp_to_sint_I16x8_S\000"
5802 /* 26477 */ "fp_to_uint_I16x8_S\000"
5803 /* 26496 */ "extend_high_u_I16x8_S\000"
5804 /* 26518 */ "extend_low_u_I16x8_S\000"
5805 /* 26539 */ "RELAXED_DOT_ADD_S\000"
5806 /* 26557 */ "AND_S\000"
5807 /* 26563 */ "END_S\000"
5808 /* 26569 */ "ATOMIC_FENCE_S\000"
5809 /* 26584 */ "COMPILER_FENCE_S\000"
5810 /* 26601 */ "I64_MUL_WIDE_S\000"
5811 /* 26616 */ "DEBUG_UNREACHABLE_S\000"
5812 /* 26636 */ "END_TRY_TABLE_S\000"
5813 /* 26652 */ "SHUFFLE_S\000"
5814 /* 26662 */ "RELAXED_SWIZZLE_S\000"
5815 /* 26680 */ "ELSE_S\000"
5816 /* 26687 */ "DELEGATE_S\000"
5817 /* 26698 */ "ANYTRUE_S\000"
5818 /* 26708 */ "TABLE_SIZE_S\000"
5819 /* 26721 */ "LOCAL_TEE_FUNCREF_S\000"
5820 /* 26741 */ "TABLE_FILL_FUNCREF_S\000"
5821 /* 26762 */ "REF_NULL_FUNCREF_S\000"
5822 /* 26781 */ "REF_IS_NULL_FUNCREF_S\000"
5823 /* 26803 */ "DROP_FUNCREF_S\000"
5824 /* 26818 */ "SELECT_FUNCREF_S\000"
5825 /* 26835 */ "TABLE_GET_FUNCREF_S\000"
5826 /* 26855 */ "GLOBAL_GET_FUNCREF_S\000"
5827 /* 26876 */ "LOCAL_GET_FUNCREF_S\000"
5828 /* 26896 */ "TABLE_SET_FUNCREF_S\000"
5829 /* 26916 */ "GLOBAL_SET_FUNCREF_S\000"
5830 /* 26937 */ "LOCAL_SET_FUNCREF_S\000"
5831 /* 26957 */ "TABLE_GROW_FUNCREF_S\000"
5832 /* 26978 */ "COPY_FUNCREF_S\000"
5833 /* 26993 */ "LOCAL_TEE_EXTERNREF_S\000"
5834 /* 27015 */ "TABLE_FILL_EXTERNREF_S\000"
5835 /* 27038 */ "REF_NULL_EXTERNREF_S\000"
5836 /* 27059 */ "REF_IS_NULL_EXTERNREF_S\000"
5837 /* 27083 */ "DROP_EXTERNREF_S\000"
5838 /* 27100 */ "SELECT_EXTERNREF_S\000"
5839 /* 27119 */ "TABLE_GET_EXTERNREF_S\000"
5840 /* 27141 */ "GLOBAL_GET_EXTERNREF_S\000"
5841 /* 27164 */ "LOCAL_GET_EXTERNREF_S\000"
5842 /* 27186 */ "TABLE_SET_EXTERNREF_S\000"
5843 /* 27208 */ "GLOBAL_SET_EXTERNREF_S\000"
5844 /* 27231 */ "LOCAL_SET_EXTERNREF_S\000"
5845 /* 27253 */ "TABLE_GROW_EXTERNREF_S\000"
5846 /* 27276 */ "COPY_EXTERNREF_S\000"
5847 /* 27293 */ "LOCAL_TEE_EXNREF_S\000"
5848 /* 27312 */ "TABLE_FILL_EXNREF_S\000"
5849 /* 27332 */ "REF_NULL_EXNREF_S\000"
5850 /* 27350 */ "REF_IS_NULL_EXNREF_S\000"
5851 /* 27371 */ "DROP_EXNREF_S\000"
5852 /* 27385 */ "SELECT_EXNREF_S\000"
5853 /* 27401 */ "TABLE_GET_EXNREF_S\000"
5854 /* 27420 */ "GLOBAL_GET_EXNREF_S\000"
5855 /* 27440 */ "LOCAL_GET_EXNREF_S\000"
5856 /* 27459 */ "TABLE_SET_EXNREF_S\000"
5857 /* 27478 */ "GLOBAL_SET_EXNREF_S\000"
5858 /* 27498 */ "LOCAL_SET_EXNREF_S\000"
5859 /* 27517 */ "TABLE_GROW_EXNREF_S\000"
5860 /* 27537 */ "COPY_EXNREF_S\000"
5861 /* 27551 */ "CATCH_REF_S\000"
5862 /* 27563 */ "CATCH_ALL_REF_S\000"
5863 /* 27579 */ "THROW_REF_S\000"
5864 /* 27591 */ "END_IF_S\000"
5865 /* 27600 */ "BR_IF_S\000"
5866 /* 27608 */ "CATCH_S\000"
5867 /* 27616 */ "END_BLOCK_S\000"
5868 /* 27628 */ "RET_CALL_S\000"
5869 /* 27639 */ "CATCH_ALL_S\000"
5870 /* 27651 */ "END_FUNCTION_S\000"
5871 /* 27666 */ "FALLTHROUGH_RETURN_S\000"
5872 /* 27687 */ "ADJCALLSTACKDOWN_S\000"
5873 /* 27706 */ "NOP_S\000"
5874 /* 27712 */ "END_LOOP_S\000"
5875 /* 27723 */ "DATA_DROP_S\000"
5876 /* 27735 */ "ADJCALLSTACKUP_S\000"
5877 /* 27752 */ "BR_S\000"
5878 /* 27757 */ "XOR_S\000"
5879 /* 27763 */ "CALL_PARAMS_S\000"
5880 /* 27777 */ "BR_UNLESS_S\000"
5881 /* 27789 */ "RET_CALL_RESULTS_S\000"
5882 /* 27808 */ "I64_MUL_WIDE_S_S\000"
5883 /* 27825 */ "RELAXED_DOT_BFLOAT_S\000"
5884 /* 27846 */ "BITSELECT_S\000"
5885 /* 27858 */ "RET_CALL_INDIRECT_S\000"
5886 /* 27878 */ "CATCHRET_S\000"
5887 /* 27889 */ "CLEANUPRET_S\000"
5888 /* 27902 */ "RELAXED_DOT_S\000"
5889 /* 27916 */ "ANDNOT_S\000"
5890 /* 27925 */ "I64_MUL_WIDE_U_S\000"
5891 /* 27942 */ "RETHROW_S\000"
5892 /* 27952 */ "CATCH_LEGACY_S\000"
5893 /* 27967 */ "CATCH_ALL_LEGACY_S\000"
5894 /* 27986 */ "TABLE_COPY_S\000"
5895 /* 27999 */ "END_TRY_S\000"
5896 /* 28009 */ "ARGUMENT_funcref_S\000"
5897 /* 28028 */ "ARGUMENT_externref_S\000"
5898 /* 28049 */ "ARGUMENT_exnref_S\000"
5899 /* 28067 */ "EXTRACT_LANE_I8x16_s_S\000"
5900 /* 28090 */ "EXTRACT_LANE_I16x8_s_S\000"
5901 /* 28113 */ "EXTRACT_LANE_I8x16_u_S\000"
5902 /* 28136 */ "EXTRACT_LANE_I16x8_u_S\000"
5903 /* 28159 */ "RELAXED_DOT_BFLOAT\000"
5904 /* 28178 */ "G_SSUBSAT\000"
5905 /* 28188 */ "G_USUBSAT\000"
5906 /* 28198 */ "G_SADDSAT\000"
5907 /* 28208 */ "G_UADDSAT\000"
5908 /* 28218 */ "G_SSHLSAT\000"
5909 /* 28228 */ "G_USHLSAT\000"
5910 /* 28238 */ "G_SMULFIXSAT\000"
5911 /* 28251 */ "G_UMULFIXSAT\000"
5912 /* 28264 */ "G_SDIVFIXSAT\000"
5913 /* 28277 */ "G_UDIVFIXSAT\000"
5914 /* 28290 */ "G_ATOMICRMW_USUB_SAT\000"
5915 /* 28311 */ "G_FPTOSI_SAT\000"
5916 /* 28324 */ "G_FPTOUI_SAT\000"
5917 /* 28337 */ "G_EXTRACT\000"
5918 /* 28347 */ "BITSELECT\000"
5919 /* 28357 */ "G_SELECT\000"
5920 /* 28366 */ "G_BRINDIRECT\000"
5921 /* 28379 */ "RET_CALL_INDIRECT\000"
5922 /* 28397 */ "CATCHRET\000"
5923 /* 28406 */ "CLEANUPRET\000"
5924 /* 28417 */ "PATCHABLE_RET\000"
5925 /* 28431 */ "G_MEMSET\000"
5926 /* 28440 */ "PATCHABLE_FUNCTION_EXIT\000"
5927 /* 28464 */ "G_BRJT\000"
5928 /* 28471 */ "G_EXTRACT_VECTOR_ELT\000"
5929 /* 28492 */ "G_INSERT_VECTOR_ELT\000"
5930 /* 28512 */ "G_FCONSTANT\000"
5931 /* 28524 */ "G_CONSTANT\000"
5932 /* 28535 */ "G_INTRINSIC_CONVERGENT\000"
5933 /* 28558 */ "STATEPOINT\000"
5934 /* 28569 */ "PATCHPOINT\000"
5935 /* 28580 */ "G_PTRTOINT\000"
5936 /* 28591 */ "G_FRINT\000"
5937 /* 28599 */ "G_INTRINSIC_LLRINT\000"
5938 /* 28618 */ "G_INTRINSIC_LRINT\000"
5939 /* 28636 */ "G_FNEARBYINT\000"
5940 /* 28649 */ "RELAXED_DOT\000"
5941 /* 28661 */ "ANDNOT\000"
5942 /* 28668 */ "G_VASTART\000"
5943 /* 28678 */ "LIFETIME_START\000"
5944 /* 28693 */ "G_INVOKE_REGION_START\000"
5945 /* 28715 */ "G_INSERT\000"
5946 /* 28724 */ "G_FSQRT\000"
5947 /* 28732 */ "G_STRICT_FSQRT\000"
5948 /* 28747 */ "G_BITCAST\000"
5949 /* 28757 */ "G_ADDRSPACE_CAST\000"
5950 /* 28774 */ "DBG_VALUE_LIST\000"
5951 /* 28789 */ "G_FPEXT\000"
5952 /* 28797 */ "G_SEXT\000"
5953 /* 28804 */ "G_ASSERT_SEXT\000"
5954 /* 28818 */ "G_ANYEXT\000"
5955 /* 28827 */ "G_ZEXT\000"
5956 /* 28834 */ "G_ASSERT_ZEXT\000"
5957 /* 28848 */ "G_ABDU\000"
5958 /* 28855 */ "I64_MUL_WIDE_U\000"
5959 /* 28870 */ "G_FDIV\000"
5960 /* 28877 */ "G_STRICT_FDIV\000"
5961 /* 28891 */ "G_SDIV\000"
5962 /* 28898 */ "G_UDIV\000"
5963 /* 28905 */ "G_GET_FPENV\000"
5964 /* 28917 */ "G_RESET_FPENV\000"
5965 /* 28931 */ "G_SET_FPENV\000"
5966 /* 28943 */ "G_FPOW\000"
5967 /* 28950 */ "RETHROW\000"
5968 /* 28958 */ "G_VECREDUCE_FMAX\000"
5969 /* 28975 */ "G_ATOMICRMW_FMAX\000"
5970 /* 28992 */ "G_VECREDUCE_SMAX\000"
5971 /* 29009 */ "G_SMAX\000"
5972 /* 29016 */ "G_VECREDUCE_UMAX\000"
5973 /* 29033 */ "G_UMAX\000"
5974 /* 29040 */ "G_ATOMICRMW_UMAX\000"
5975 /* 29057 */ "G_ATOMICRMW_MAX\000"
5976 /* 29073 */ "G_FRAME_INDEX\000"
5977 /* 29087 */ "G_SBFX\000"
5978 /* 29094 */ "G_UBFX\000"
5979 /* 29101 */ "G_SMULFIX\000"
5980 /* 29111 */ "G_UMULFIX\000"
5981 /* 29121 */ "G_SDIVFIX\000"
5982 /* 29131 */ "G_UDIVFIX\000"
5983 /* 29141 */ "CATCH_LEGACY\000"
5984 /* 29154 */ "CATCH_ALL_LEGACY\000"
5985 /* 29171 */ "G_MEMCPY\000"
5986 /* 29180 */ "TABLE_COPY\000"
5987 /* 29191 */ "CONVERGENCECTRL_ENTRY\000"
5988 /* 29213 */ "END_TRY\000"
5989 /* 29221 */ "G_CTLZ\000"
5990 /* 29228 */ "G_CTTZ\000"
5991 /* 29235 */ "ARGUMENT_funcref\000"
5992 /* 29252 */ "ARGUMENT_externref\000"
5993 /* 29271 */ "ARGUMENT_exnref\000"
5994 /* 29287 */ "EXTRACT_LANE_I8x16_s\000"
5995 /* 29308 */ "EXTRACT_LANE_I16x8_s\000"
5996 /* 29329 */ "EXTRACT_LANE_I8x16_u\000"
5997 /* 29350 */ "EXTRACT_LANE_I16x8_u\000"
5998};
5999#ifdef __GNUC__
6000#pragma GCC diagnostic pop
6001#endif
6002
6003extern const unsigned WebAssemblyInstrNameIndices[] = {
6004 12775U, 13174U, 13970U, 13545U, 12844U, 12825U, 12853U, 13010U,
6005 12592U, 12607U, 11765U, 11752U, 12634U, 14478U, 11581U, 28774U,
6006 12548U, 12771U, 12834U, 11292U, 29186U, 11446U, 28678U, 11091U,
6007 11215U, 11265U, 13675U, 12988U, 28569U, 11198U, 13905U, 12697U,
6008 28558U, 11493U, 13878U, 13865U, 14031U, 28417U, 28440U, 12911U,
6009 12967U, 12940U, 12870U, 11563U, 13996U, 13629U, 29191U, 14149U,
6010 13826U, 11629U, 28804U, 28834U, 13375U, 10988U, 10699U, 13113U,
6011 28891U, 28898U, 13140U, 13147U, 13154U, 13164U, 11069U, 14334U,
6012 14297U, 14385U, 28848U, 11763U, 12773U, 29073U, 11591U, 11606U,
6013 13015U, 28337U, 14392U, 28715U, 14409U, 14220U, 10769U, 14461U,
6014 28580U, 14361U, 28747U, 11680U, 14007U, 11172U, 10743U, 11154U,
6015 28618U, 28599U, 13353U, 14056U, 14075U, 10889U, 10833U, 10863U,
6016 10874U, 10814U, 10844U, 11537U, 11521U, 14508U, 12648U, 12665U,
6017 11020U, 10705U, 11075U, 11036U, 14339U, 14303U, 29057U, 13501U,
6018 29040U, 13484U, 10955U, 10682U, 28975U, 13419U, 13269U, 13216U,
6019 13737U, 13715U, 11113U, 28290U, 11257U, 12720U, 11104U, 28366U,
6020 28693U, 10721U, 14566U, 28535U, 14593U, 28818U, 10761U, 28524U,
6021 28512U, 28668U, 12689U, 28797U, 12621U, 28827U, 12897U, 14142U,
6022 14128U, 12890U, 14135U, 14354U, 13031U, 13792U, 13785U, 13799U,
6023 13806U, 28357U, 13621U, 11313U, 13605U, 11236U, 13613U, 11305U,
6024 13597U, 11228U, 13659U, 13651U, 12739U, 12731U, 28208U, 28198U,
6025 28188U, 28178U, 28228U, 28218U, 29101U, 29111U, 28238U, 28251U,
6026 29121U, 29131U, 28264U, 28277U, 10913U, 10661U, 13055U, 10642U,
6027 10807U, 28870U, 13119U, 28943U, 12797U, 13949U, 3557U, 9U,
6028 12682U, 3540U, 0U, 13924U, 13956U, 12585U, 28789U, 10733U,
6029 12779U, 12788U, 13767U, 13776U, 28311U, 28324U, 14372U, 13390U,
6030 14495U, 11689U, 13318U, 13328U, 11362U, 11377U, 13205U, 13258U,
6031 13290U, 13304U, 28905U, 28931U, 28917U, 11321U, 11349U, 11334U,
6032 10994U, 12815U, 13453U, 29009U, 13477U, 29033U, 14379U, 11145U,
6033 11135U, 13965U, 28464U, 11392U, 14201U, 14181U, 28492U, 28471U,
6034 14235U, 14266U, 14252U, 14548U, 29228U, 11734U, 29221U, 11716U,
6035 13847U, 13759U, 11550U, 12903U, 14444U, 13525U, 14451U, 13346U,
6036 14436U, 13517U, 13338U, 3548U, 12763U, 12755U, 12747U, 28724U,
6037 14172U, 28591U, 28636U, 28757U, 13983U, 11419U, 10790U, 11658U,
6038 11506U, 10941U, 10668U, 13083U, 28877U, 13126U, 10648U, 28732U,
6039 13933U, 14095U, 14111U, 29171U, 11477U, 11670U, 28431U, 13667U,
6040 13708U, 13684U, 13696U, 10920U, 13062U, 10896U, 13038U, 28958U,
6041 13402U, 13237U, 13184U, 10972U, 13097U, 11053U, 14319U, 14281U,
6042 28992U, 13436U, 29016U, 13460U, 29087U, 29094U, 14424U, 27763U,
6043 14635U, 27793U, 28397U, 27878U, 28406U, 27889U, 11277U, 26584U,
6044 14631U, 27789U, 9781U, 25562U, 2639U, 17521U, 8045U, 23590U,
6045 6952U, 22319U, 3759U, 18794U, 10024U, 25845U, 8349U, 23940U,
6046 4069U, 19150U, 9163U, 24846U, 9652U, 25411U, 2508U, 17362U,
6047 7892U, 23413U, 6822U, 22161U, 3606U, 18617U, 9928U, 25733U,
6048 2958U, 17888U, 8234U, 23807U, 7271U, 22686U, 3954U, 19017U,
6049 9077U, 24746U, 10140U, 25977U, 9235U, 24930U, 10368U, 26237U,
6050 9417U, 25140U, 13580U, 27687U, 13890U, 27735U, 9957U, 25766U,
6051 8282U, 23861U, 4002U, 19071U, 9106U, 24779U, 11049U, 28661U,
6052 27916U, 2966U, 17898U, 7279U, 22696U, 26557U, 11650U, 26698U,
6053 29271U, 28049U, 29252U, 28028U, 3499U, 18523U, 7810U, 23319U,
6054 29235U, 28009U, 3527U, 18555U, 7838U, 23351U, 9613U, 25366U,
6055 7795U, 23302U, 7823U, 23334U, 3484U, 18506U, 3512U, 18538U,
6056 9020U, 24681U, 9035U, 24698U, 11244U, 26569U, 743U, 15435U,
6057 5057U, 20234U, 1865U, 16651U, 6179U, 21450U, 1841U, 16625U,
6058 6155U, 21424U, 767U, 15461U, 5081U, 20260U, 1889U, 16677U,
6059 6203U, 21476U, 201U, 14849U, 4515U, 19648U, 1116U, 15842U,
6060 5430U, 20641U, 221U, 14871U, 4535U, 19670U, 1163U, 15893U,
6061 5477U, 20692U, 297U, 14953U, 4611U, 19752U, 1266U, 16004U,
6062 5580U, 20803U, 394U, 15058U, 4708U, 19857U, 1394U, 16142U,
6063 5708U, 20941U, 637U, 15319U, 4951U, 20118U, 1718U, 16490U,
6064 6032U, 21289U, 125U, 14767U, 4439U, 19566U, 1040U, 15760U,
6065 5354U, 20559U, 482U, 15152U, 4796U, 19951U, 1510U, 16266U,
6066 5824U, 21065U, 561U, 15237U, 4875U, 20036U, 1616U, 16380U,
6067 5930U, 21179U, 1136U, 15864U, 5450U, 20663U, 1239U, 15975U,
6068 5553U, 20774U, 1363U, 16109U, 5677U, 20908U, 1692U, 16462U,
6069 6006U, 21261U, 1013U, 15731U, 5327U, 20530U, 1482U, 16236U,
6070 5796U, 21035U, 1589U, 16351U, 5903U, 21150U, 248U, 14900U,
6071 4562U, 19699U, 1190U, 15922U, 5504U, 20721U, 324U, 14982U,
6072 4638U, 19781U, 1293U, 16033U, 5607U, 20832U, 425U, 15091U,
6073 4739U, 19890U, 1425U, 16175U, 5739U, 20974U, 663U, 15347U,
6074 4977U, 20146U, 1744U, 16518U, 6058U, 21317U, 152U, 14796U,
6075 4466U, 19595U, 1067U, 15789U, 5381U, 20588U, 510U, 15182U,
6076 4824U, 19981U, 1538U, 16296U, 5852U, 21095U, 588U, 15266U,
6077 4902U, 20065U, 1643U, 16409U, 5957U, 21208U, 274U, 14928U,
6078 4588U, 19727U, 1216U, 15950U, 5530U, 20749U, 350U, 15010U,
6079 4664U, 19809U, 1319U, 16061U, 5633U, 20860U, 455U, 15123U,
6080 4769U, 19922U, 1455U, 16207U, 5769U, 21006U, 688U, 15374U,
6081 5002U, 20173U, 1769U, 16545U, 6083U, 21344U, 178U, 14824U,
6082 4492U, 19623U, 1093U, 15817U, 5407U, 20616U, 537U, 15211U,
6083 4851U, 20010U, 1565U, 16325U, 5879U, 21124U, 614U, 15294U,
6084 4928U, 20093U, 1669U, 16437U, 5983U, 21236U, 80U, 14718U,
6085 4394U, 19517U, 968U, 15682U, 5282U, 20481U, 945U, 15657U,
6086 5259U, 20456U, 103U, 14743U, 4417U, 19542U, 991U, 15707U,
6087 5305U, 20506U, 373U, 15035U, 4687U, 19834U, 1342U, 16086U,
6088 5656U, 20885U, 10327U, 26190U, 9376U, 25093U, 9981U, 25794U,
6089 8306U, 23889U, 4026U, 19099U, 9130U, 24807U, 28347U, 27846U,
6090 12809U, 27620U, 13967U, 12579U, 27600U, 27752U, 2988U, 17924U,
6091 7301U, 22722U, 14538U, 27777U, 12926U, 28383U, 27862U, 27632U,
6092 12714U, 13000U, 29154U, 27967U, 12534U, 27563U, 27639U, 29141U,
6093 27952U, 12524U, 27551U, 27608U, 9728U, 25499U, 2575U, 17443U,
6094 7968U, 23501U, 6888U, 22241U, 3682U, 18705U, 3460U, 18476U,
6095 7771U, 23272U, 2883U, 17799U, 7196U, 22597U, 3322U, 18314U,
6096 7650U, 23129U, 7851U, 23366U, 3565U, 18570U, 9901U, 25702U,
6097 8207U, 23776U, 3927U, 18986U, 9050U, 24715U, 2592U, 17464U,
6098 6905U, 22262U, 12512U, 27537U, 12279U, 27276U, 2941U, 17867U,
6099 7254U, 22665U, 12009U, 26978U, 3451U, 18465U, 7762U, 23261U,
6100 9603U, 25354U, 3476U, 18496U, 7787U, 23292U, 13855U, 27723U,
6101 11401U, 26616U, 11572U, 26687U, 9846U, 25639U, 2925U, 17847U,
6102 8110U, 23667U, 7238U, 22645U, 3824U, 18871U, 3212U, 18188U,
6103 7540U, 23003U, 3441U, 18453U, 7752U, 23249U, 28657U, 27910U,
6104 12364U, 27371U, 12104U, 27083U, 2613U, 17489U, 6926U, 22287U,
6105 11852U, 26803U, 3033U, 17979U, 7359U, 22792U, 9519U, 25258U,
6106 11545U, 26680U, 11100U, 12805U, 27616U, 13532U, 27651U, 12572U,
6107 27591U, 13817U, 27712U, 26563U, 29213U, 27999U, 11432U, 26636U,
6108 3468U, 18486U, 7779U, 23282U, 9760U, 25537U, 2622U, 17500U,
6109 8024U, 23565U, 6935U, 22298U, 3738U, 18769U, 10015U, 25834U,
6110 3042U, 17990U, 8340U, 23929U, 7368U, 22803U, 4060U, 19139U,
6111 9154U, 24835U, 10056U, 25883U, 8381U, 23978U, 4101U, 19188U,
6112 10295U, 26154U, 8529U, 24148U, 4203U, 19304U, 10198U, 26043U,
6113 8447U, 24054U, 4155U, 19250U, 10406U, 26281U, 8595U, 24224U,
6114 4235U, 19340U, 9699U, 25466U, 7939U, 23468U, 3653U, 18672U,
6115 29308U, 28090U, 29350U, 28136U, 8263U, 23840U, 3983U, 19050U,
6116 29287U, 28067U, 29329U, 28113U, 3176U, 18148U, 7504U, 22963U,
6117 3405U, 18413U, 7716U, 23209U, 6865U, 22214U, 3262U, 18246U,
6118 3194U, 18168U, 7522U, 22983U, 3423U, 18433U, 7734U, 23229U,
6119 2551U, 17415U, 7590U, 23061U, 13561U, 27666U, 9769U, 25548U,
6120 2629U, 17509U, 8033U, 23576U, 6942U, 22307U, 3747U, 18780U,
6121 2414U, 17256U, 6728U, 22055U, 2452U, 17298U, 6766U, 22097U,
6122 2433U, 17277U, 6747U, 22076U, 2471U, 17319U, 6785U, 22118U,
6123 9662U, 25423U, 2530U, 17388U, 7902U, 23425U, 6844U, 22187U,
6124 3616U, 18629U, 10034U, 25857U, 3120U, 18080U, 8359U, 23952U,
6125 7448U, 22895U, 4079U, 19162U, 9173U, 24858U, 10273U, 26128U,
6126 3349U, 18345U, 8507U, 24122U, 7660U, 23141U, 9342U, 25053U,
6127 12407U, 27420U, 12156U, 27141U, 2770U, 17668U, 7083U, 22466U,
6128 11898U, 26855U, 3233U, 18213U, 7561U, 23028U, 9541U, 25284U,
6129 12459U, 27478U, 12217U, 27208U, 2819U, 17723U, 7132U, 22521U,
6130 11953U, 26916U, 3282U, 18268U, 7610U, 23083U, 9572U, 25319U,
6131 9803U, 25588U, 2848U, 17756U, 8067U, 23616U, 7161U, 22554U,
6132 3781U, 18820U, 10176U, 26017U, 3158U, 18126U, 8425U, 24028U,
6133 7486U, 22941U, 4133U, 19224U, 9251U, 24948U, 10384U, 26255U,
6134 3387U, 18391U, 8573U, 24198U, 7698U, 23187U, 9433U, 25158U,
6135 3066U, 18020U, 3085U, 18041U, 2799U, 17701U, 2647U, 17531U,
6136 6960U, 22329U, 2679U, 17567U, 6992U, 22365U, 2893U, 17811U,
6137 7206U, 22609U, 2719U, 17611U, 7032U, 22409U, 7346U, 22777U,
6138 9493U, 25228U, 7411U, 22854U, 7392U, 22833U, 7430U, 22875U,
6139 3103U, 18061U, 3332U, 18326U, 26601U, 27808U, 28855U, 27925U,
6140 7112U, 22499U, 9482U, 25215U, 2663U, 17549U, 6976U, 22347U,
6141 2699U, 17589U, 7012U, 22387U, 2909U, 17829U, 7222U, 22627U,
6142 2739U, 17633U, 7052U, 22431U, 12576U, 27595U, 10256U, 26109U,
6143 8490U, 24103U, 4186U, 19285U, 9312U, 25019U, 9671U, 25434U,
6144 2537U, 17397U, 7911U, 23436U, 6851U, 22196U, 3625U, 18640U,
6145 10045U, 25870U, 3129U, 18091U, 8370U, 23965U, 7457U, 22906U,
6146 4090U, 19175U, 9184U, 24871U, 10284U, 26141U, 3358U, 18356U,
6147 8518U, 24135U, 7669U, 23152U, 9353U, 25066U, 2272U, 17098U,
6148 6586U, 21897U, 710U, 15398U, 5024U, 20197U, 1808U, 16588U,
6149 6122U, 21387U, 750U, 15442U, 5064U, 20241U, 1872U, 16658U,
6150 6186U, 21457U, 2238U, 17060U, 6552U, 21859U, 1791U, 16569U,
6151 6105U, 21368U, 1848U, 16632U, 6162U, 21431U, 2255U, 17079U,
6152 6569U, 21878U, 2289U, 17117U, 6603U, 21916U, 727U, 15417U,
6153 5041U, 20216U, 1825U, 16607U, 6139U, 21406U, 774U, 15468U,
6154 5088U, 20267U, 1896U, 16684U, 6210U, 21483U, 2144U, 16958U,
6155 6458U, 21757U, 1992U, 16790U, 6306U, 21589U, 870U, 15574U,
6156 5184U, 20373U, 2168U, 16984U, 6482U, 21783U, 2016U, 16816U,
6157 6330U, 21615U, 894U, 15600U, 5208U, 20399U, 18U, 14648U,
6158 4332U, 19447U, 53U, 14687U, 4367U, 19486U, 918U, 15626U,
6159 5232U, 20425U, 208U, 14856U, 4522U, 19655U, 1123U, 15849U,
6160 5437U, 20648U, 2040U, 16842U, 6354U, 21641U, 815U, 15513U,
6161 5129U, 20312U, 1937U, 16729U, 6251U, 21528U, 2107U, 16917U,
6162 6421U, 21716U, 2078U, 16884U, 6392U, 21683U, 832U, 15532U,
6163 5146U, 20331U, 1954U, 16748U, 6268U, 21547U, 12425U, 27440U,
6164 12177U, 27164U, 2785U, 17685U, 7098U, 22483U, 11917U, 26876U,
6165 3248U, 18230U, 7576U, 23045U, 9557U, 25302U, 12477U, 27498U,
6166 12238U, 27231U, 2834U, 17740U, 7147U, 22538U, 11972U, 26937U,
6167 3297U, 18285U, 7625U, 23100U, 9588U, 25337U, 12294U, 27293U,
6168 12022U, 26993U, 2516U, 17372U, 6830U, 22171U, 11778U, 26721U,
6169 2974U, 17908U, 7287U, 22706U, 9504U, 25241U, 13821U, 27716U,
6170 9812U, 25599U, 2855U, 17765U, 8076U, 23627U, 7168U, 22563U,
6171 3790U, 18831U, 10187U, 26030U, 3167U, 18137U, 8436U, 24041U,
6172 7495U, 22952U, 4144U, 19237U, 9262U, 24961U, 10395U, 26268U,
6173 3396U, 18402U, 8584U, 24211U, 7707U, 23198U, 9444U, 25171U,
6174 9651U, 25410U, 7891U, 23412U, 3605U, 18616U, 9857U, 25652U,
6175 2933U, 17857U, 8134U, 23693U, 7246U, 22655U, 3848U, 18897U,
6176 10232U, 26081U, 8466U, 24075U, 9288U, 24991U, 10440U, 26319U,
6177 8614U, 24245U, 9470U, 25201U, 2387U, 17225U, 6701U, 22024U,
6178 2362U, 17198U, 6676U, 21997U, 790U, 15486U, 5104U, 20285U,
6179 1912U, 16702U, 6226U, 21501U, 2398U, 17238U, 6712U, 22037U,
6180 2222U, 17042U, 6536U, 21841U, 2316U, 17148U, 6630U, 21947U,
6181 2305U, 17135U, 6619U, 21934U, 9750U, 25525U, 2605U, 17479U,
6182 8003U, 23540U, 6918U, 22277U, 3717U, 18744U, 10076U, 25905U,
6183 8401U, 24000U, 9195U, 24884U, 10315U, 26176U, 8549U, 24170U,
6184 9364U, 25079U, 9739U, 25512U, 2584U, 17454U, 7979U, 23514U,
6185 6897U, 22252U, 3693U, 18718U, 10005U, 25822U, 3025U, 17969U,
6186 8330U, 23917U, 7338U, 22767U, 4050U, 19127U, 10217U, 26064U,
6187 9273U, 24974U, 10425U, 26302U, 9455U, 25184U, 9832U, 25623U,
6188 2871U, 17785U, 8096U, 23651U, 7184U, 22583U, 3810U, 18855U,
6189 9718U, 25487U, 2567U, 17433U, 7958U, 23489U, 6880U, 22231U,
6190 3672U, 18693U, 9971U, 25782U, 8296U, 23877U, 4016U, 19087U,
6191 9120U, 24795U, 9690U, 25455U, 2544U, 17406U, 7930U, 23457U,
6192 6858U, 22205U, 3644U, 18661U, 9948U, 25755U, 3001U, 17939U,
6193 8254U, 23829U, 7314U, 22737U, 3974U, 19039U, 9097U, 24768U,
6194 9650U, 25409U, 7890U, 23411U, 3604U, 18615U, 13813U, 27706U,
6195 28664U, 27919U, 14169U, 3050U, 18000U, 7376U, 22813U, 27758U,
6196 9856U, 25651U, 8144U, 23705U, 3858U, 18909U, 9749U, 25524U,
6197 8013U, 23552U, 3727U, 18756U, 3311U, 18301U, 7639U, 23116U,
6198 9329U, 25038U, 10156U, 25995U, 12345U, 27350U, 12082U, 27059U,
6199 11832U, 26781U, 12329U, 27332U, 12063U, 27038U, 11815U, 26762U,
6200 28649U, 11004U, 26539U, 28159U, 27825U, 27902U, 10100U, 25933U,
6201 11461U, 26662U, 3138U, 18102U, 7466U, 22917U, 3367U, 18367U,
6202 7678U, 23163U, 9680U, 25445U, 7920U, 23447U, 3634U, 18651U,
6203 9938U, 25745U, 8244U, 23819U, 3964U, 19029U, 9087U, 24758U,
6204 28950U, 27942U, 13573U, 27678U, 12931U, 28379U, 27858U, 27628U,
6205 3016U, 17958U, 7329U, 22756U, 3057U, 18009U, 7383U, 22822U,
6206 12376U, 27385U, 12119U, 27100U, 2759U, 17655U, 7072U, 22453U,
6207 11865U, 26818U, 3222U, 18200U, 7550U, 23015U, 9529U, 25270U,
6208 9995U, 25810U, 3008U, 17948U, 8320U, 23905U, 7321U, 22746U,
6209 4040U, 19115U, 9144U, 24823U, 10088U, 25919U, 3148U, 18114U,
6210 8413U, 24014U, 7476U, 22929U, 4121U, 19210U, 9207U, 24898U,
6211 10340U, 26205U, 3377U, 18379U, 8561U, 24184U, 7688U, 23175U,
6212 4223U, 19326U, 9389U, 25108U, 11453U, 26652U, 8120U, 23679U,
6213 3834U, 18883U, 7989U, 23526U, 3703U, 18730U, 9791U, 25574U,
6214 8055U, 23602U, 3769U, 18806U, 10244U, 26095U, 8478U, 24089U,
6215 4174U, 19271U, 9300U, 25005U, 9821U, 25610U, 2862U, 17774U,
6216 8085U, 23638U, 7175U, 22572U, 3799U, 18842U, 87U, 14725U,
6217 4401U, 19524U, 975U, 15689U, 5289U, 20488U, 952U, 15664U,
6218 5266U, 20463U, 110U, 14750U, 4424U, 19549U, 998U, 15714U,
6219 5312U, 20513U, 35U, 14667U, 4349U, 19466U, 66U, 14702U,
6220 4380U, 19501U, 931U, 15641U, 5245U, 20440U, 380U, 15042U,
6221 4694U, 19841U, 1349U, 16093U, 5663U, 20892U, 2123U, 16935U,
6222 6437U, 21734U, 1971U, 16767U, 6285U, 21566U, 849U, 15551U,
6223 5163U, 20350U, 2057U, 16861U, 6371U, 21660U, 2092U, 16900U,
6224 6406U, 21699U, 9628U, 25383U, 2490U, 17340U, 7868U, 23385U,
6225 6804U, 22139U, 3582U, 18589U, 9918U, 25721U, 2950U, 17878U,
6226 8224U, 23795U, 7263U, 22676U, 3944U, 19005U, 9067U, 24734U,
6227 10124U, 25959U, 9219U, 24912U, 10352U, 26219U, 9401U, 25122U,
6228 11469U, 26670U, 29180U, 27986U, 12311U, 27312U, 12042U, 27015U,
6229 11796U, 26741U, 12390U, 27401U, 12136U, 27119U, 11880U, 26835U,
6230 12494U, 27517U, 12258U, 27253U, 11990U, 26957U, 12442U, 27459U,
6231 12197U, 27186U, 11935U, 26896U, 11705U, 26708U, 12300U, 27299U,
6232 12028U, 26999U, 2522U, 17378U, 6836U, 22177U, 11784U, 26727U,
6233 2980U, 17914U, 7293U, 22712U, 9510U, 25247U, 28952U, 12562U,
6234 27579U, 27944U, 9638U, 25395U, 2498U, 17350U, 7878U, 23397U,
6235 6812U, 22149U, 3592U, 18601U, 29209U, 28003U, 11436U, 26640U,
6236 11407U, 26622U, 14293U, 3049U, 17999U, 7375U, 22812U, 27757U,
6237 2332U, 17166U, 2192U, 17010U, 6646U, 21965U, 6506U, 21809U,
6238 3869U, 18922U, 3889U, 18944U, 8155U, 23718U, 10530U, 26415U,
6239 8862U, 24507U, 4254U, 19361U, 10603U, 26496U, 8958U, 24613U,
6240 4293U, 19404U, 10550U, 26437U, 8905U, 24554U, 4274U, 19383U,
6241 10623U, 26518U, 9001U, 24660U, 4313U, 19426U, 10569U, 26458U,
6242 8924U, 24575U, 10586U, 26477U, 8941U, 24594U, 10452U, 26333U,
6243 8662U, 24297U, 10490U, 26373U, 8738U, 24377U, 8626U, 24259U,
6244 8778U, 24419U, 8700U, 24337U, 8819U, 24462U, 3909U, 18966U,
6245 9867U, 25664U, 8173U, 23738U, 8882U, 24529U, 8978U, 24635U,
6246 9884U, 25683U, 8190U, 23757U,
6247};
6248
6249static inline void InitWebAssemblyMCInstrInfo(MCInstrInfo *II) {
6250 II->InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1940);
6251}
6252
6253} // end namespace llvm
6254#endif // GET_INSTRINFO_MC_DESC
6255
6256#ifdef GET_INSTRINFO_HEADER
6257#undef GET_INSTRINFO_HEADER
6258namespace llvm {
6259struct WebAssemblyGenInstrInfo : public TargetInstrInfo {
6260 explicit WebAssemblyGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
6261 ~WebAssemblyGenInstrInfo() override = default;
6262
6263};
6264} // end namespace llvm
6265#endif // GET_INSTRINFO_HEADER
6266
6267#ifdef GET_INSTRINFO_HELPER_DECLS
6268#undef GET_INSTRINFO_HELPER_DECLS
6269
6270
6271#endif // GET_INSTRINFO_HELPER_DECLS
6272
6273#ifdef GET_INSTRINFO_HELPERS
6274#undef GET_INSTRINFO_HELPERS
6275
6276#endif // GET_INSTRINFO_HELPERS
6277
6278#ifdef GET_INSTRINFO_CTOR_DTOR
6279#undef GET_INSTRINFO_CTOR_DTOR
6280namespace llvm {
6281extern const WebAssemblyInstrTable WebAssemblyDescs;
6282extern const unsigned WebAssemblyInstrNameIndices[];
6283extern const char WebAssemblyInstrNameData[];
6284WebAssemblyGenInstrInfo::WebAssemblyGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
6285 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
6286 InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1940);
6287}
6288} // end namespace llvm
6289#endif // GET_INSTRINFO_CTOR_DTOR
6290
6291#ifdef GET_INSTRINFO_OPERAND_ENUM
6292#undef GET_INSTRINFO_OPERAND_ENUM
6293namespace llvm::WebAssembly {
6294enum class OpName {
6295 addr = 0,
6296 count = 1,
6297 dst = 2,
6298 exp = 3,
6299 idx = 4,
6300 new_ = 5,
6301 off = 6,
6302 p2align = 7,
6303 timeout = 8,
6304 val = 9,
6305 vec = 10,
6306 NUM_OPERAND_NAMES = 11,
6307}; // enum class OpName
6308
6309LLVM_READONLY
6310int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name);
6311} // end namespace llvm::WebAssembly
6312#endif //GET_INSTRINFO_OPERAND_ENUM
6313
6314#ifdef GET_INSTRINFO_NAMED_OPS
6315#undef GET_INSTRINFO_NAMED_OPS
6316namespace llvm::WebAssembly {
6317LLVM_READONLY
6318int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name) {
6319 assert(Name != OpName::NUM_OPERAND_NAMES);
6320 static constexpr int8_t OperandMap[][11] = {
6321 {3, -1, 0, -1, -1, -1, 2, 1, -1, -1, -1, },
6322 {3, -1, 0, -1, -1, -1, 2, 1, -1, 4, -1, },
6323 {3, -1, 0, 4, -1, 5, 2, 1, -1, -1, -1, },
6324 {3, -1, 0, 4, -1, -1, 2, 1, 5, -1, -1, },
6325 {3, 4, 0, -1, -1, -1, 2, 1, -1, -1, -1, },
6326 {4, -1, 0, -1, 3, -1, 2, 1, -1, -1, 5, },
6327 {-1, -1, -1, -1, -1, -1, 1, 0, -1, -1, -1, },
6328 {2, -1, -1, -1, -1, -1, 1, 0, -1, 3, -1, },
6329 {2, -1, -1, -1, -1, -1, 1, 0, -1, -1, 3, },
6330 {3, -1, -1, -1, 2, -1, 1, 0, -1, -1, 4, },
6331 {-1, -1, -1, -1, 2, -1, 1, 0, -1, -1, -1, },
6332 };
6333 switch(Opcode) {
6334 case WebAssembly::ATOMIC_LOAD16_U_I32_A32:
6335 case WebAssembly::ATOMIC_LOAD16_U_I32_A64:
6336 case WebAssembly::ATOMIC_LOAD16_U_I64_A32:
6337 case WebAssembly::ATOMIC_LOAD16_U_I64_A64:
6338 case WebAssembly::ATOMIC_LOAD32_U_I64_A32:
6339 case WebAssembly::ATOMIC_LOAD32_U_I64_A64:
6340 case WebAssembly::ATOMIC_LOAD8_U_I32_A32:
6341 case WebAssembly::ATOMIC_LOAD8_U_I32_A64:
6342 case WebAssembly::ATOMIC_LOAD8_U_I64_A32:
6343 case WebAssembly::ATOMIC_LOAD8_U_I64_A64:
6344 case WebAssembly::ATOMIC_LOAD_I32_A32:
6345 case WebAssembly::ATOMIC_LOAD_I32_A64:
6346 case WebAssembly::ATOMIC_LOAD_I64_A32:
6347 case WebAssembly::ATOMIC_LOAD_I64_A64:
6348 case WebAssembly::LOAD16_SPLAT_A32:
6349 case WebAssembly::LOAD16_SPLAT_A64:
6350 case WebAssembly::LOAD16_S_I32_A32:
6351 case WebAssembly::LOAD16_S_I32_A64:
6352 case WebAssembly::LOAD16_S_I64_A32:
6353 case WebAssembly::LOAD16_S_I64_A64:
6354 case WebAssembly::LOAD16_U_I32_A32:
6355 case WebAssembly::LOAD16_U_I32_A64:
6356 case WebAssembly::LOAD16_U_I64_A32:
6357 case WebAssembly::LOAD16_U_I64_A64:
6358 case WebAssembly::LOAD32_SPLAT_A32:
6359 case WebAssembly::LOAD32_SPLAT_A64:
6360 case WebAssembly::LOAD32_S_I64_A32:
6361 case WebAssembly::LOAD32_S_I64_A64:
6362 case WebAssembly::LOAD32_U_I64_A32:
6363 case WebAssembly::LOAD32_U_I64_A64:
6364 case WebAssembly::LOAD64_SPLAT_A32:
6365 case WebAssembly::LOAD64_SPLAT_A64:
6366 case WebAssembly::LOAD8_SPLAT_A32:
6367 case WebAssembly::LOAD8_SPLAT_A64:
6368 case WebAssembly::LOAD8_S_I32_A32:
6369 case WebAssembly::LOAD8_S_I32_A64:
6370 case WebAssembly::LOAD8_S_I64_A32:
6371 case WebAssembly::LOAD8_S_I64_A64:
6372 case WebAssembly::LOAD8_U_I32_A32:
6373 case WebAssembly::LOAD8_U_I32_A64:
6374 case WebAssembly::LOAD8_U_I64_A32:
6375 case WebAssembly::LOAD8_U_I64_A64:
6376 case WebAssembly::LOAD_EXTEND_S_I16x8_A32:
6377 case WebAssembly::LOAD_EXTEND_S_I16x8_A64:
6378 case WebAssembly::LOAD_EXTEND_S_I32x4_A32:
6379 case WebAssembly::LOAD_EXTEND_S_I32x4_A64:
6380 case WebAssembly::LOAD_EXTEND_S_I64x2_A32:
6381 case WebAssembly::LOAD_EXTEND_S_I64x2_A64:
6382 case WebAssembly::LOAD_EXTEND_U_I16x8_A32:
6383 case WebAssembly::LOAD_EXTEND_U_I16x8_A64:
6384 case WebAssembly::LOAD_EXTEND_U_I32x4_A32:
6385 case WebAssembly::LOAD_EXTEND_U_I32x4_A64:
6386 case WebAssembly::LOAD_EXTEND_U_I64x2_A32:
6387 case WebAssembly::LOAD_EXTEND_U_I64x2_A64:
6388 case WebAssembly::LOAD_F16_F32_A32:
6389 case WebAssembly::LOAD_F16_F32_A64:
6390 case WebAssembly::LOAD_F32_A32:
6391 case WebAssembly::LOAD_F32_A64:
6392 case WebAssembly::LOAD_F64_A32:
6393 case WebAssembly::LOAD_F64_A64:
6394 case WebAssembly::LOAD_I32_A32:
6395 case WebAssembly::LOAD_I32_A64:
6396 case WebAssembly::LOAD_I64_A32:
6397 case WebAssembly::LOAD_I64_A64:
6398 case WebAssembly::LOAD_V128_A32:
6399 case WebAssembly::LOAD_V128_A64:
6400 case WebAssembly::LOAD_ZERO_32_A32:
6401 case WebAssembly::LOAD_ZERO_32_A64:
6402 case WebAssembly::LOAD_ZERO_64_A32:
6403 case WebAssembly::LOAD_ZERO_64_A64:
6404 return OperandMap[0][static_cast<unsigned>(Name)];
6405 case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32:
6406 case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64:
6407 case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32:
6408 case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64:
6409 case WebAssembly::ATOMIC_RMW16_U_AND_I32_A32:
6410 case WebAssembly::ATOMIC_RMW16_U_AND_I32_A64:
6411 case WebAssembly::ATOMIC_RMW16_U_AND_I64_A32:
6412 case WebAssembly::ATOMIC_RMW16_U_AND_I64_A64:
6413 case WebAssembly::ATOMIC_RMW16_U_OR_I32_A32:
6414 case WebAssembly::ATOMIC_RMW16_U_OR_I32_A64:
6415 case WebAssembly::ATOMIC_RMW16_U_OR_I64_A32:
6416 case WebAssembly::ATOMIC_RMW16_U_OR_I64_A64:
6417 case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32:
6418 case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64:
6419 case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32:
6420 case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64:
6421 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32:
6422 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64:
6423 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32:
6424 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64:
6425 case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32:
6426 case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64:
6427 case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32:
6428 case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64:
6429 case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32:
6430 case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64:
6431 case WebAssembly::ATOMIC_RMW32_U_AND_I64_A32:
6432 case WebAssembly::ATOMIC_RMW32_U_AND_I64_A64:
6433 case WebAssembly::ATOMIC_RMW32_U_OR_I64_A32:
6434 case WebAssembly::ATOMIC_RMW32_U_OR_I64_A64:
6435 case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32:
6436 case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64:
6437 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32:
6438 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64:
6439 case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32:
6440 case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64:
6441 case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32:
6442 case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64:
6443 case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32:
6444 case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64:
6445 case WebAssembly::ATOMIC_RMW8_U_AND_I32_A32:
6446 case WebAssembly::ATOMIC_RMW8_U_AND_I32_A64:
6447 case WebAssembly::ATOMIC_RMW8_U_AND_I64_A32:
6448 case WebAssembly::ATOMIC_RMW8_U_AND_I64_A64:
6449 case WebAssembly::ATOMIC_RMW8_U_OR_I32_A32:
6450 case WebAssembly::ATOMIC_RMW8_U_OR_I32_A64:
6451 case WebAssembly::ATOMIC_RMW8_U_OR_I64_A32:
6452 case WebAssembly::ATOMIC_RMW8_U_OR_I64_A64:
6453 case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32:
6454 case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64:
6455 case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32:
6456 case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64:
6457 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32:
6458 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64:
6459 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32:
6460 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64:
6461 case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32:
6462 case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64:
6463 case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32:
6464 case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64:
6465 case WebAssembly::ATOMIC_RMW_ADD_I32_A32:
6466 case WebAssembly::ATOMIC_RMW_ADD_I32_A64:
6467 case WebAssembly::ATOMIC_RMW_ADD_I64_A32:
6468 case WebAssembly::ATOMIC_RMW_ADD_I64_A64:
6469 case WebAssembly::ATOMIC_RMW_AND_I32_A32:
6470 case WebAssembly::ATOMIC_RMW_AND_I32_A64:
6471 case WebAssembly::ATOMIC_RMW_AND_I64_A32:
6472 case WebAssembly::ATOMIC_RMW_AND_I64_A64:
6473 case WebAssembly::ATOMIC_RMW_OR_I32_A32:
6474 case WebAssembly::ATOMIC_RMW_OR_I32_A64:
6475 case WebAssembly::ATOMIC_RMW_OR_I64_A32:
6476 case WebAssembly::ATOMIC_RMW_OR_I64_A64:
6477 case WebAssembly::ATOMIC_RMW_SUB_I32_A32:
6478 case WebAssembly::ATOMIC_RMW_SUB_I32_A64:
6479 case WebAssembly::ATOMIC_RMW_SUB_I64_A32:
6480 case WebAssembly::ATOMIC_RMW_SUB_I64_A64:
6481 case WebAssembly::ATOMIC_RMW_XCHG_I32_A32:
6482 case WebAssembly::ATOMIC_RMW_XCHG_I32_A64:
6483 case WebAssembly::ATOMIC_RMW_XCHG_I64_A32:
6484 case WebAssembly::ATOMIC_RMW_XCHG_I64_A64:
6485 case WebAssembly::ATOMIC_RMW_XOR_I32_A32:
6486 case WebAssembly::ATOMIC_RMW_XOR_I32_A64:
6487 case WebAssembly::ATOMIC_RMW_XOR_I64_A32:
6488 case WebAssembly::ATOMIC_RMW_XOR_I64_A64:
6489 return OperandMap[1][static_cast<unsigned>(Name)];
6490 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32:
6491 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64:
6492 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32:
6493 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64:
6494 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32:
6495 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64:
6496 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32:
6497 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64:
6498 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32:
6499 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64:
6500 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32:
6501 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64:
6502 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32:
6503 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64:
6504 return OperandMap[2][static_cast<unsigned>(Name)];
6505 case WebAssembly::MEMORY_ATOMIC_WAIT32_A32:
6506 case WebAssembly::MEMORY_ATOMIC_WAIT32_A64:
6507 case WebAssembly::MEMORY_ATOMIC_WAIT64_A32:
6508 case WebAssembly::MEMORY_ATOMIC_WAIT64_A64:
6509 return OperandMap[3][static_cast<unsigned>(Name)];
6510 case WebAssembly::MEMORY_ATOMIC_NOTIFY_A32:
6511 case WebAssembly::MEMORY_ATOMIC_NOTIFY_A64:
6512 return OperandMap[4][static_cast<unsigned>(Name)];
6513 case WebAssembly::LOAD_LANE_16_A32:
6514 case WebAssembly::LOAD_LANE_16_A64:
6515 case WebAssembly::LOAD_LANE_32_A32:
6516 case WebAssembly::LOAD_LANE_32_A64:
6517 case WebAssembly::LOAD_LANE_64_A32:
6518 case WebAssembly::LOAD_LANE_64_A64:
6519 case WebAssembly::LOAD_LANE_8_A32:
6520 case WebAssembly::LOAD_LANE_8_A64:
6521 return OperandMap[5][static_cast<unsigned>(Name)];
6522 case WebAssembly::ATOMIC_LOAD16_U_I32_A32_S:
6523 case WebAssembly::ATOMIC_LOAD16_U_I32_A64_S:
6524 case WebAssembly::ATOMIC_LOAD16_U_I64_A32_S:
6525 case WebAssembly::ATOMIC_LOAD16_U_I64_A64_S:
6526 case WebAssembly::ATOMIC_LOAD32_U_I64_A32_S:
6527 case WebAssembly::ATOMIC_LOAD32_U_I64_A64_S:
6528 case WebAssembly::ATOMIC_LOAD8_U_I32_A32_S:
6529 case WebAssembly::ATOMIC_LOAD8_U_I32_A64_S:
6530 case WebAssembly::ATOMIC_LOAD8_U_I64_A32_S:
6531 case WebAssembly::ATOMIC_LOAD8_U_I64_A64_S:
6532 case WebAssembly::ATOMIC_LOAD_I32_A32_S:
6533 case WebAssembly::ATOMIC_LOAD_I32_A64_S:
6534 case WebAssembly::ATOMIC_LOAD_I64_A32_S:
6535 case WebAssembly::ATOMIC_LOAD_I64_A64_S:
6536 case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32_S:
6537 case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64_S:
6538 case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32_S:
6539 case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64_S:
6540 case WebAssembly::ATOMIC_RMW16_U_AND_I32_A32_S:
6541 case WebAssembly::ATOMIC_RMW16_U_AND_I32_A64_S:
6542 case WebAssembly::ATOMIC_RMW16_U_AND_I64_A32_S:
6543 case WebAssembly::ATOMIC_RMW16_U_AND_I64_A64_S:
6544 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32_S:
6545 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64_S:
6546 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32_S:
6547 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64_S:
6548 case WebAssembly::ATOMIC_RMW16_U_OR_I32_A32_S:
6549 case WebAssembly::ATOMIC_RMW16_U_OR_I32_A64_S:
6550 case WebAssembly::ATOMIC_RMW16_U_OR_I64_A32_S:
6551 case WebAssembly::ATOMIC_RMW16_U_OR_I64_A64_S:
6552 case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32_S:
6553 case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64_S:
6554 case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32_S:
6555 case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64_S:
6556 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32_S:
6557 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64_S:
6558 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32_S:
6559 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64_S:
6560 case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32_S:
6561 case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64_S:
6562 case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32_S:
6563 case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64_S:
6564 case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32_S:
6565 case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64_S:
6566 case WebAssembly::ATOMIC_RMW32_U_AND_I64_A32_S:
6567 case WebAssembly::ATOMIC_RMW32_U_AND_I64_A64_S:
6568 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32_S:
6569 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64_S:
6570 case WebAssembly::ATOMIC_RMW32_U_OR_I64_A32_S:
6571 case WebAssembly::ATOMIC_RMW32_U_OR_I64_A64_S:
6572 case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32_S:
6573 case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64_S:
6574 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32_S:
6575 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64_S:
6576 case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32_S:
6577 case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64_S:
6578 case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32_S:
6579 case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64_S:
6580 case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32_S:
6581 case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64_S:
6582 case WebAssembly::ATOMIC_RMW8_U_AND_I32_A32_S:
6583 case WebAssembly::ATOMIC_RMW8_U_AND_I32_A64_S:
6584 case WebAssembly::ATOMIC_RMW8_U_AND_I64_A32_S:
6585 case WebAssembly::ATOMIC_RMW8_U_AND_I64_A64_S:
6586 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32_S:
6587 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64_S:
6588 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32_S:
6589 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64_S:
6590 case WebAssembly::ATOMIC_RMW8_U_OR_I32_A32_S:
6591 case WebAssembly::ATOMIC_RMW8_U_OR_I32_A64_S:
6592 case WebAssembly::ATOMIC_RMW8_U_OR_I64_A32_S:
6593 case WebAssembly::ATOMIC_RMW8_U_OR_I64_A64_S:
6594 case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32_S:
6595 case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64_S:
6596 case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32_S:
6597 case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64_S:
6598 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32_S:
6599 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64_S:
6600 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32_S:
6601 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64_S:
6602 case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32_S:
6603 case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64_S:
6604 case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32_S:
6605 case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64_S:
6606 case WebAssembly::ATOMIC_RMW_ADD_I32_A32_S:
6607 case WebAssembly::ATOMIC_RMW_ADD_I32_A64_S:
6608 case WebAssembly::ATOMIC_RMW_ADD_I64_A32_S:
6609 case WebAssembly::ATOMIC_RMW_ADD_I64_A64_S:
6610 case WebAssembly::ATOMIC_RMW_AND_I32_A32_S:
6611 case WebAssembly::ATOMIC_RMW_AND_I32_A64_S:
6612 case WebAssembly::ATOMIC_RMW_AND_I64_A32_S:
6613 case WebAssembly::ATOMIC_RMW_AND_I64_A64_S:
6614 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32_S:
6615 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64_S:
6616 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32_S:
6617 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64_S:
6618 case WebAssembly::ATOMIC_RMW_OR_I32_A32_S:
6619 case WebAssembly::ATOMIC_RMW_OR_I32_A64_S:
6620 case WebAssembly::ATOMIC_RMW_OR_I64_A32_S:
6621 case WebAssembly::ATOMIC_RMW_OR_I64_A64_S:
6622 case WebAssembly::ATOMIC_RMW_SUB_I32_A32_S:
6623 case WebAssembly::ATOMIC_RMW_SUB_I32_A64_S:
6624 case WebAssembly::ATOMIC_RMW_SUB_I64_A32_S:
6625 case WebAssembly::ATOMIC_RMW_SUB_I64_A64_S:
6626 case WebAssembly::ATOMIC_RMW_XCHG_I32_A32_S:
6627 case WebAssembly::ATOMIC_RMW_XCHG_I32_A64_S:
6628 case WebAssembly::ATOMIC_RMW_XCHG_I64_A32_S:
6629 case WebAssembly::ATOMIC_RMW_XCHG_I64_A64_S:
6630 case WebAssembly::ATOMIC_RMW_XOR_I32_A32_S:
6631 case WebAssembly::ATOMIC_RMW_XOR_I32_A64_S:
6632 case WebAssembly::ATOMIC_RMW_XOR_I64_A32_S:
6633 case WebAssembly::ATOMIC_RMW_XOR_I64_A64_S:
6634 case WebAssembly::ATOMIC_STORE16_I32_A32_S:
6635 case WebAssembly::ATOMIC_STORE16_I32_A64_S:
6636 case WebAssembly::ATOMIC_STORE16_I64_A32_S:
6637 case WebAssembly::ATOMIC_STORE16_I64_A64_S:
6638 case WebAssembly::ATOMIC_STORE32_I64_A32_S:
6639 case WebAssembly::ATOMIC_STORE32_I64_A64_S:
6640 case WebAssembly::ATOMIC_STORE8_I32_A32_S:
6641 case WebAssembly::ATOMIC_STORE8_I32_A64_S:
6642 case WebAssembly::ATOMIC_STORE8_I64_A32_S:
6643 case WebAssembly::ATOMIC_STORE8_I64_A64_S:
6644 case WebAssembly::ATOMIC_STORE_I32_A32_S:
6645 case WebAssembly::ATOMIC_STORE_I32_A64_S:
6646 case WebAssembly::ATOMIC_STORE_I64_A32_S:
6647 case WebAssembly::ATOMIC_STORE_I64_A64_S:
6648 case WebAssembly::LOAD16_SPLAT_A32_S:
6649 case WebAssembly::LOAD16_SPLAT_A64_S:
6650 case WebAssembly::LOAD16_S_I32_A32_S:
6651 case WebAssembly::LOAD16_S_I32_A64_S:
6652 case WebAssembly::LOAD16_S_I64_A32_S:
6653 case WebAssembly::LOAD16_S_I64_A64_S:
6654 case WebAssembly::LOAD16_U_I32_A32_S:
6655 case WebAssembly::LOAD16_U_I32_A64_S:
6656 case WebAssembly::LOAD16_U_I64_A32_S:
6657 case WebAssembly::LOAD16_U_I64_A64_S:
6658 case WebAssembly::LOAD32_SPLAT_A32_S:
6659 case WebAssembly::LOAD32_SPLAT_A64_S:
6660 case WebAssembly::LOAD32_S_I64_A32_S:
6661 case WebAssembly::LOAD32_S_I64_A64_S:
6662 case WebAssembly::LOAD32_U_I64_A32_S:
6663 case WebAssembly::LOAD32_U_I64_A64_S:
6664 case WebAssembly::LOAD64_SPLAT_A32_S:
6665 case WebAssembly::LOAD64_SPLAT_A64_S:
6666 case WebAssembly::LOAD8_SPLAT_A32_S:
6667 case WebAssembly::LOAD8_SPLAT_A64_S:
6668 case WebAssembly::LOAD8_S_I32_A32_S:
6669 case WebAssembly::LOAD8_S_I32_A64_S:
6670 case WebAssembly::LOAD8_S_I64_A32_S:
6671 case WebAssembly::LOAD8_S_I64_A64_S:
6672 case WebAssembly::LOAD8_U_I32_A32_S:
6673 case WebAssembly::LOAD8_U_I32_A64_S:
6674 case WebAssembly::LOAD8_U_I64_A32_S:
6675 case WebAssembly::LOAD8_U_I64_A64_S:
6676 case WebAssembly::LOAD_EXTEND_S_I16x8_A32_S:
6677 case WebAssembly::LOAD_EXTEND_S_I16x8_A64_S:
6678 case WebAssembly::LOAD_EXTEND_S_I32x4_A32_S:
6679 case WebAssembly::LOAD_EXTEND_S_I32x4_A64_S:
6680 case WebAssembly::LOAD_EXTEND_S_I64x2_A32_S:
6681 case WebAssembly::LOAD_EXTEND_S_I64x2_A64_S:
6682 case WebAssembly::LOAD_EXTEND_U_I16x8_A32_S:
6683 case WebAssembly::LOAD_EXTEND_U_I16x8_A64_S:
6684 case WebAssembly::LOAD_EXTEND_U_I32x4_A32_S:
6685 case WebAssembly::LOAD_EXTEND_U_I32x4_A64_S:
6686 case WebAssembly::LOAD_EXTEND_U_I64x2_A32_S:
6687 case WebAssembly::LOAD_EXTEND_U_I64x2_A64_S:
6688 case WebAssembly::LOAD_F16_F32_A32_S:
6689 case WebAssembly::LOAD_F16_F32_A64_S:
6690 case WebAssembly::LOAD_F32_A32_S:
6691 case WebAssembly::LOAD_F32_A64_S:
6692 case WebAssembly::LOAD_F64_A32_S:
6693 case WebAssembly::LOAD_F64_A64_S:
6694 case WebAssembly::LOAD_I32_A32_S:
6695 case WebAssembly::LOAD_I32_A64_S:
6696 case WebAssembly::LOAD_I64_A32_S:
6697 case WebAssembly::LOAD_I64_A64_S:
6698 case WebAssembly::LOAD_V128_A32_S:
6699 case WebAssembly::LOAD_V128_A64_S:
6700 case WebAssembly::LOAD_ZERO_32_A32_S:
6701 case WebAssembly::LOAD_ZERO_32_A64_S:
6702 case WebAssembly::LOAD_ZERO_64_A32_S:
6703 case WebAssembly::LOAD_ZERO_64_A64_S:
6704 case WebAssembly::MEMORY_ATOMIC_NOTIFY_A32_S:
6705 case WebAssembly::MEMORY_ATOMIC_NOTIFY_A64_S:
6706 case WebAssembly::MEMORY_ATOMIC_WAIT32_A32_S:
6707 case WebAssembly::MEMORY_ATOMIC_WAIT32_A64_S:
6708 case WebAssembly::MEMORY_ATOMIC_WAIT64_A32_S:
6709 case WebAssembly::MEMORY_ATOMIC_WAIT64_A64_S:
6710 case WebAssembly::STORE16_I32_A32_S:
6711 case WebAssembly::STORE16_I32_A64_S:
6712 case WebAssembly::STORE16_I64_A32_S:
6713 case WebAssembly::STORE16_I64_A64_S:
6714 case WebAssembly::STORE32_I64_A32_S:
6715 case WebAssembly::STORE32_I64_A64_S:
6716 case WebAssembly::STORE8_I32_A32_S:
6717 case WebAssembly::STORE8_I32_A64_S:
6718 case WebAssembly::STORE8_I64_A32_S:
6719 case WebAssembly::STORE8_I64_A64_S:
6720 case WebAssembly::STORE_F16_F32_A32_S:
6721 case WebAssembly::STORE_F16_F32_A64_S:
6722 case WebAssembly::STORE_F32_A32_S:
6723 case WebAssembly::STORE_F32_A64_S:
6724 case WebAssembly::STORE_F64_A32_S:
6725 case WebAssembly::STORE_F64_A64_S:
6726 case WebAssembly::STORE_I32_A32_S:
6727 case WebAssembly::STORE_I32_A64_S:
6728 case WebAssembly::STORE_I64_A32_S:
6729 case WebAssembly::STORE_I64_A64_S:
6730 case WebAssembly::STORE_V128_A32_S:
6731 case WebAssembly::STORE_V128_A64_S:
6732 return OperandMap[6][static_cast<unsigned>(Name)];
6733 case WebAssembly::ATOMIC_STORE16_I32_A32:
6734 case WebAssembly::ATOMIC_STORE16_I32_A64:
6735 case WebAssembly::ATOMIC_STORE16_I64_A32:
6736 case WebAssembly::ATOMIC_STORE16_I64_A64:
6737 case WebAssembly::ATOMIC_STORE32_I64_A32:
6738 case WebAssembly::ATOMIC_STORE32_I64_A64:
6739 case WebAssembly::ATOMIC_STORE8_I32_A32:
6740 case WebAssembly::ATOMIC_STORE8_I32_A64:
6741 case WebAssembly::ATOMIC_STORE8_I64_A32:
6742 case WebAssembly::ATOMIC_STORE8_I64_A64:
6743 case WebAssembly::ATOMIC_STORE_I32_A32:
6744 case WebAssembly::ATOMIC_STORE_I32_A64:
6745 case WebAssembly::ATOMIC_STORE_I64_A32:
6746 case WebAssembly::ATOMIC_STORE_I64_A64:
6747 case WebAssembly::STORE16_I32_A32:
6748 case WebAssembly::STORE16_I32_A64:
6749 case WebAssembly::STORE16_I64_A32:
6750 case WebAssembly::STORE16_I64_A64:
6751 case WebAssembly::STORE32_I64_A32:
6752 case WebAssembly::STORE32_I64_A64:
6753 case WebAssembly::STORE8_I32_A32:
6754 case WebAssembly::STORE8_I32_A64:
6755 case WebAssembly::STORE8_I64_A32:
6756 case WebAssembly::STORE8_I64_A64:
6757 case WebAssembly::STORE_F16_F32_A32:
6758 case WebAssembly::STORE_F16_F32_A64:
6759 case WebAssembly::STORE_F32_A32:
6760 case WebAssembly::STORE_F32_A64:
6761 case WebAssembly::STORE_F64_A32:
6762 case WebAssembly::STORE_F64_A64:
6763 case WebAssembly::STORE_I32_A32:
6764 case WebAssembly::STORE_I32_A64:
6765 case WebAssembly::STORE_I64_A32:
6766 case WebAssembly::STORE_I64_A64:
6767 return OperandMap[7][static_cast<unsigned>(Name)];
6768 case WebAssembly::STORE_V128_A32:
6769 case WebAssembly::STORE_V128_A64:
6770 return OperandMap[8][static_cast<unsigned>(Name)];
6771 case WebAssembly::STORE_LANE_I16x8_A32:
6772 case WebAssembly::STORE_LANE_I16x8_A64:
6773 case WebAssembly::STORE_LANE_I32x4_A32:
6774 case WebAssembly::STORE_LANE_I32x4_A64:
6775 case WebAssembly::STORE_LANE_I64x2_A32:
6776 case WebAssembly::STORE_LANE_I64x2_A64:
6777 case WebAssembly::STORE_LANE_I8x16_A32:
6778 case WebAssembly::STORE_LANE_I8x16_A64:
6779 return OperandMap[9][static_cast<unsigned>(Name)];
6780 case WebAssembly::LOAD_LANE_16_A32_S:
6781 case WebAssembly::LOAD_LANE_16_A64_S:
6782 case WebAssembly::LOAD_LANE_32_A32_S:
6783 case WebAssembly::LOAD_LANE_32_A64_S:
6784 case WebAssembly::LOAD_LANE_64_A32_S:
6785 case WebAssembly::LOAD_LANE_64_A64_S:
6786 case WebAssembly::LOAD_LANE_8_A32_S:
6787 case WebAssembly::LOAD_LANE_8_A64_S:
6788 case WebAssembly::STORE_LANE_I16x8_A32_S:
6789 case WebAssembly::STORE_LANE_I16x8_A64_S:
6790 case WebAssembly::STORE_LANE_I32x4_A32_S:
6791 case WebAssembly::STORE_LANE_I32x4_A64_S:
6792 case WebAssembly::STORE_LANE_I64x2_A32_S:
6793 case WebAssembly::STORE_LANE_I64x2_A64_S:
6794 case WebAssembly::STORE_LANE_I8x16_A32_S:
6795 case WebAssembly::STORE_LANE_I8x16_A64_S:
6796 return OperandMap[10][static_cast<unsigned>(Name)];
6797 default: return -1;
6798 }
6799}
6800} // end namespace llvm::WebAssembly
6801#endif //GET_INSTRINFO_NAMED_OPS
6802
6803#ifdef GET_INSTRINFO_MC_HELPER_DECLS
6804#undef GET_INSTRINFO_MC_HELPER_DECLS
6805
6806namespace llvm {
6807class MCInst;
6808class FeatureBitset;
6809
6810namespace WebAssembly_MC {
6811
6812void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
6813
6814} // end namespace WebAssembly_MC
6815} // end namespace llvm
6816
6817#endif // GET_INSTRINFO_MC_HELPER_DECLS
6818
6819#ifdef GET_INSTRINFO_MC_HELPERS
6820#undef GET_INSTRINFO_MC_HELPERS
6821
6822namespace llvm::WebAssembly_MC {
6823} // end namespace llvm::WebAssembly_MC
6824#endif // GET_GENISTRINFO_MC_HELPERS
6825
6826#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
6827 defined(GET_AVAILABLE_OPCODE_CHECKER)
6828#define GET_COMPUTE_FEATURES
6829#endif
6830#ifdef GET_COMPUTE_FEATURES
6831#undef GET_COMPUTE_FEATURES
6832namespace llvm::WebAssembly_MC {
6833// Bits for subtarget features that participate in instruction matching.
6834enum SubtargetFeatureBits : uint8_t {
6835 Feature_HasAtomicsBit = 0,
6836 Feature_HasBulkMemoryBit = 1,
6837 Feature_HasBulkMemoryOptBit = 2,
6838 Feature_HasCallIndirectOverlongBit = 3,
6839 Feature_HasExceptionHandlingBit = 4,
6840 Feature_HasExtendedConstBit = 5,
6841 Feature_HasFP16Bit = 6,
6842 Feature_HasMultiMemoryBit = 7,
6843 Feature_HasMultivalueBit = 8,
6844 Feature_HasMutableGlobalsBit = 9,
6845 Feature_HasNontrappingFPToIntBit = 10,
6846 Feature_NotHasNontrappingFPToIntBit = 17,
6847 Feature_HasReferenceTypesBit = 11,
6848 Feature_HasRelaxedSIMDBit = 12,
6849 Feature_HasSignExtBit = 14,
6850 Feature_HasSIMD128Bit = 13,
6851 Feature_HasTailCallBit = 15,
6852 Feature_HasWideArithmeticBit = 16,
6853};
6854
6855inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
6856 FeatureBitset Features;
6857 if (FB[WebAssembly::FeatureAtomics])
6858 Features.set(Feature_HasAtomicsBit);
6859 if (FB[WebAssembly::FeatureBulkMemory])
6860 Features.set(Feature_HasBulkMemoryBit);
6861 if (FB[WebAssembly::FeatureBulkMemoryOpt])
6862 Features.set(Feature_HasBulkMemoryOptBit);
6863 if (FB[WebAssembly::FeatureCallIndirectOverlong])
6864 Features.set(Feature_HasCallIndirectOverlongBit);
6865 if (FB[WebAssembly::FeatureExceptionHandling])
6866 Features.set(Feature_HasExceptionHandlingBit);
6867 if (FB[WebAssembly::FeatureExtendedConst])
6868 Features.set(Feature_HasExtendedConstBit);
6869 if (FB[WebAssembly::FeatureFP16])
6870 Features.set(Feature_HasFP16Bit);
6871 if (FB[WebAssembly::FeatureMultiMemory])
6872 Features.set(Feature_HasMultiMemoryBit);
6873 if (FB[WebAssembly::FeatureMultivalue])
6874 Features.set(Feature_HasMultivalueBit);
6875 if (FB[WebAssembly::FeatureMutableGlobals])
6876 Features.set(Feature_HasMutableGlobalsBit);
6877 if (FB[WebAssembly::FeatureNontrappingFPToInt])
6878 Features.set(Feature_HasNontrappingFPToIntBit);
6879 if (!FB[WebAssembly::FeatureNontrappingFPToInt])
6880 Features.set(Feature_NotHasNontrappingFPToIntBit);
6881 if (FB[WebAssembly::FeatureReferenceTypes])
6882 Features.set(Feature_HasReferenceTypesBit);
6883 if (FB[WebAssembly::FeatureRelaxedSIMD])
6884 Features.set(Feature_HasRelaxedSIMDBit);
6885 if (FB[WebAssembly::FeatureSignExt])
6886 Features.set(Feature_HasSignExtBit);
6887 if (FB[WebAssembly::FeatureSIMD128] || FB[WebAssembly::FeatureRelaxedSIMD])
6888 Features.set(Feature_HasSIMD128Bit);
6889 if (FB[WebAssembly::FeatureTailCall])
6890 Features.set(Feature_HasTailCallBit);
6891 if (FB[WebAssembly::FeatureWideArithmetic])
6892 Features.set(Feature_HasWideArithmeticBit);
6893 return Features;
6894}
6895
6896inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
6897 enum : uint8_t {
6898 CEFBS_None,
6899 CEFBS_HasAtomics,
6900 CEFBS_HasBulkMemoryOpt,
6901 CEFBS_HasExceptionHandling,
6902 CEFBS_HasFP16,
6903 CEFBS_HasNontrappingFPToInt,
6904 CEFBS_HasReferenceTypes,
6905 CEFBS_HasRelaxedSIMD,
6906 CEFBS_HasSIMD128,
6907 CEFBS_HasSignExt,
6908 CEFBS_HasTailCall,
6909 CEFBS_HasWideArithmetic,
6910 CEFBS_NotHasNontrappingFPToInt,
6911 CEFBS_HasReferenceTypes_HasExceptionHandling,
6912 CEFBS_HasSIMD128_HasFP16,
6913 CEFBS_HasSIMD128_HasRelaxedSIMD,
6914 };
6915
6916 static constexpr FeatureBitset FeatureBitsets[] = {
6917 {}, // CEFBS_None
6918 {Feature_HasAtomicsBit, },
6919 {Feature_HasBulkMemoryOptBit, },
6920 {Feature_HasExceptionHandlingBit, },
6921 {Feature_HasFP16Bit, },
6922 {Feature_HasNontrappingFPToIntBit, },
6923 {Feature_HasReferenceTypesBit, },
6924 {Feature_HasRelaxedSIMDBit, },
6925 {Feature_HasSIMD128Bit, },
6926 {Feature_HasSignExtBit, },
6927 {Feature_HasTailCallBit, },
6928 {Feature_HasWideArithmeticBit, },
6929 {Feature_NotHasNontrappingFPToIntBit, },
6930 {Feature_HasReferenceTypesBit, Feature_HasExceptionHandlingBit, },
6931 {Feature_HasSIMD128Bit, Feature_HasFP16Bit, },
6932 {Feature_HasSIMD128Bit, Feature_HasRelaxedSIMDBit, },
6933 };
6934 static constexpr uint8_t RequiredFeaturesRefs[] = {
6935 CEFBS_None, // PHI = 0
6936 CEFBS_None, // INLINEASM = 1
6937 CEFBS_None, // INLINEASM_BR = 2
6938 CEFBS_None, // CFI_INSTRUCTION = 3
6939 CEFBS_None, // EH_LABEL = 4
6940 CEFBS_None, // GC_LABEL = 5
6941 CEFBS_None, // ANNOTATION_LABEL = 6
6942 CEFBS_None, // KILL = 7
6943 CEFBS_None, // EXTRACT_SUBREG = 8
6944 CEFBS_None, // INSERT_SUBREG = 9
6945 CEFBS_None, // IMPLICIT_DEF = 10
6946 CEFBS_None, // INIT_UNDEF = 11
6947 CEFBS_None, // SUBREG_TO_REG = 12
6948 CEFBS_None, // COPY_TO_REGCLASS = 13
6949 CEFBS_None, // DBG_VALUE = 14
6950 CEFBS_None, // DBG_VALUE_LIST = 15
6951 CEFBS_None, // DBG_INSTR_REF = 16
6952 CEFBS_None, // DBG_PHI = 17
6953 CEFBS_None, // DBG_LABEL = 18
6954 CEFBS_None, // REG_SEQUENCE = 19
6955 CEFBS_None, // COPY = 20
6956 CEFBS_None, // BUNDLE = 21
6957 CEFBS_None, // LIFETIME_START = 22
6958 CEFBS_None, // LIFETIME_END = 23
6959 CEFBS_None, // PSEUDO_PROBE = 24
6960 CEFBS_None, // ARITH_FENCE = 25
6961 CEFBS_None, // STACKMAP = 26
6962 CEFBS_None, // FENTRY_CALL = 27
6963 CEFBS_None, // PATCHPOINT = 28
6964 CEFBS_None, // LOAD_STACK_GUARD = 29
6965 CEFBS_None, // PREALLOCATED_SETUP = 30
6966 CEFBS_None, // PREALLOCATED_ARG = 31
6967 CEFBS_None, // STATEPOINT = 32
6968 CEFBS_None, // LOCAL_ESCAPE = 33
6969 CEFBS_None, // FAULTING_OP = 34
6970 CEFBS_None, // PATCHABLE_OP = 35
6971 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
6972 CEFBS_None, // PATCHABLE_RET = 37
6973 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
6974 CEFBS_None, // PATCHABLE_TAIL_CALL = 39
6975 CEFBS_None, // PATCHABLE_EVENT_CALL = 40
6976 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
6977 CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
6978 CEFBS_None, // FAKE_USE = 43
6979 CEFBS_None, // MEMBARRIER = 44
6980 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
6981 CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
6982 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
6983 CEFBS_None, // CONVERGENCECTRL_LOOP = 48
6984 CEFBS_None, // CONVERGENCECTRL_GLUE = 49
6985 CEFBS_None, // G_ASSERT_SEXT = 50
6986 CEFBS_None, // G_ASSERT_ZEXT = 51
6987 CEFBS_None, // G_ASSERT_ALIGN = 52
6988 CEFBS_None, // G_ADD = 53
6989 CEFBS_None, // G_SUB = 54
6990 CEFBS_None, // G_MUL = 55
6991 CEFBS_None, // G_SDIV = 56
6992 CEFBS_None, // G_UDIV = 57
6993 CEFBS_None, // G_SREM = 58
6994 CEFBS_None, // G_UREM = 59
6995 CEFBS_None, // G_SDIVREM = 60
6996 CEFBS_None, // G_UDIVREM = 61
6997 CEFBS_None, // G_AND = 62
6998 CEFBS_None, // G_OR = 63
6999 CEFBS_None, // G_XOR = 64
7000 CEFBS_None, // G_ABDS = 65
7001 CEFBS_None, // G_ABDU = 66
7002 CEFBS_None, // G_IMPLICIT_DEF = 67
7003 CEFBS_None, // G_PHI = 68
7004 CEFBS_None, // G_FRAME_INDEX = 69
7005 CEFBS_None, // G_GLOBAL_VALUE = 70
7006 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
7007 CEFBS_None, // G_CONSTANT_POOL = 72
7008 CEFBS_None, // G_EXTRACT = 73
7009 CEFBS_None, // G_UNMERGE_VALUES = 74
7010 CEFBS_None, // G_INSERT = 75
7011 CEFBS_None, // G_MERGE_VALUES = 76
7012 CEFBS_None, // G_BUILD_VECTOR = 77
7013 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
7014 CEFBS_None, // G_CONCAT_VECTORS = 79
7015 CEFBS_None, // G_PTRTOINT = 80
7016 CEFBS_None, // G_INTTOPTR = 81
7017 CEFBS_None, // G_BITCAST = 82
7018 CEFBS_None, // G_FREEZE = 83
7019 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
7020 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
7021 CEFBS_None, // G_INTRINSIC_TRUNC = 86
7022 CEFBS_None, // G_INTRINSIC_ROUND = 87
7023 CEFBS_None, // G_INTRINSIC_LRINT = 88
7024 CEFBS_None, // G_INTRINSIC_LLRINT = 89
7025 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
7026 CEFBS_None, // G_READCYCLECOUNTER = 91
7027 CEFBS_None, // G_READSTEADYCOUNTER = 92
7028 CEFBS_None, // G_LOAD = 93
7029 CEFBS_None, // G_SEXTLOAD = 94
7030 CEFBS_None, // G_ZEXTLOAD = 95
7031 CEFBS_None, // G_INDEXED_LOAD = 96
7032 CEFBS_None, // G_INDEXED_SEXTLOAD = 97
7033 CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
7034 CEFBS_None, // G_STORE = 99
7035 CEFBS_None, // G_INDEXED_STORE = 100
7036 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
7037 CEFBS_None, // G_ATOMIC_CMPXCHG = 102
7038 CEFBS_None, // G_ATOMICRMW_XCHG = 103
7039 CEFBS_None, // G_ATOMICRMW_ADD = 104
7040 CEFBS_None, // G_ATOMICRMW_SUB = 105
7041 CEFBS_None, // G_ATOMICRMW_AND = 106
7042 CEFBS_None, // G_ATOMICRMW_NAND = 107
7043 CEFBS_None, // G_ATOMICRMW_OR = 108
7044 CEFBS_None, // G_ATOMICRMW_XOR = 109
7045 CEFBS_None, // G_ATOMICRMW_MAX = 110
7046 CEFBS_None, // G_ATOMICRMW_MIN = 111
7047 CEFBS_None, // G_ATOMICRMW_UMAX = 112
7048 CEFBS_None, // G_ATOMICRMW_UMIN = 113
7049 CEFBS_None, // G_ATOMICRMW_FADD = 114
7050 CEFBS_None, // G_ATOMICRMW_FSUB = 115
7051 CEFBS_None, // G_ATOMICRMW_FMAX = 116
7052 CEFBS_None, // G_ATOMICRMW_FMIN = 117
7053 CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118
7054 CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119
7055 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120
7056 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121
7057 CEFBS_None, // G_ATOMICRMW_USUB_COND = 122
7058 CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123
7059 CEFBS_None, // G_FENCE = 124
7060 CEFBS_None, // G_PREFETCH = 125
7061 CEFBS_None, // G_BRCOND = 126
7062 CEFBS_None, // G_BRINDIRECT = 127
7063 CEFBS_None, // G_INVOKE_REGION_START = 128
7064 CEFBS_None, // G_INTRINSIC = 129
7065 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130
7066 CEFBS_None, // G_INTRINSIC_CONVERGENT = 131
7067 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132
7068 CEFBS_None, // G_ANYEXT = 133
7069 CEFBS_None, // G_TRUNC = 134
7070 CEFBS_None, // G_CONSTANT = 135
7071 CEFBS_None, // G_FCONSTANT = 136
7072 CEFBS_None, // G_VASTART = 137
7073 CEFBS_None, // G_VAARG = 138
7074 CEFBS_None, // G_SEXT = 139
7075 CEFBS_None, // G_SEXT_INREG = 140
7076 CEFBS_None, // G_ZEXT = 141
7077 CEFBS_None, // G_SHL = 142
7078 CEFBS_None, // G_LSHR = 143
7079 CEFBS_None, // G_ASHR = 144
7080 CEFBS_None, // G_FSHL = 145
7081 CEFBS_None, // G_FSHR = 146
7082 CEFBS_None, // G_ROTR = 147
7083 CEFBS_None, // G_ROTL = 148
7084 CEFBS_None, // G_ICMP = 149
7085 CEFBS_None, // G_FCMP = 150
7086 CEFBS_None, // G_SCMP = 151
7087 CEFBS_None, // G_UCMP = 152
7088 CEFBS_None, // G_SELECT = 153
7089 CEFBS_None, // G_UADDO = 154
7090 CEFBS_None, // G_UADDE = 155
7091 CEFBS_None, // G_USUBO = 156
7092 CEFBS_None, // G_USUBE = 157
7093 CEFBS_None, // G_SADDO = 158
7094 CEFBS_None, // G_SADDE = 159
7095 CEFBS_None, // G_SSUBO = 160
7096 CEFBS_None, // G_SSUBE = 161
7097 CEFBS_None, // G_UMULO = 162
7098 CEFBS_None, // G_SMULO = 163
7099 CEFBS_None, // G_UMULH = 164
7100 CEFBS_None, // G_SMULH = 165
7101 CEFBS_None, // G_UADDSAT = 166
7102 CEFBS_None, // G_SADDSAT = 167
7103 CEFBS_None, // G_USUBSAT = 168
7104 CEFBS_None, // G_SSUBSAT = 169
7105 CEFBS_None, // G_USHLSAT = 170
7106 CEFBS_None, // G_SSHLSAT = 171
7107 CEFBS_None, // G_SMULFIX = 172
7108 CEFBS_None, // G_UMULFIX = 173
7109 CEFBS_None, // G_SMULFIXSAT = 174
7110 CEFBS_None, // G_UMULFIXSAT = 175
7111 CEFBS_None, // G_SDIVFIX = 176
7112 CEFBS_None, // G_UDIVFIX = 177
7113 CEFBS_None, // G_SDIVFIXSAT = 178
7114 CEFBS_None, // G_UDIVFIXSAT = 179
7115 CEFBS_None, // G_FADD = 180
7116 CEFBS_None, // G_FSUB = 181
7117 CEFBS_None, // G_FMUL = 182
7118 CEFBS_None, // G_FMA = 183
7119 CEFBS_None, // G_FMAD = 184
7120 CEFBS_None, // G_FDIV = 185
7121 CEFBS_None, // G_FREM = 186
7122 CEFBS_None, // G_FPOW = 187
7123 CEFBS_None, // G_FPOWI = 188
7124 CEFBS_None, // G_FEXP = 189
7125 CEFBS_None, // G_FEXP2 = 190
7126 CEFBS_None, // G_FEXP10 = 191
7127 CEFBS_None, // G_FLOG = 192
7128 CEFBS_None, // G_FLOG2 = 193
7129 CEFBS_None, // G_FLOG10 = 194
7130 CEFBS_None, // G_FLDEXP = 195
7131 CEFBS_None, // G_FFREXP = 196
7132 CEFBS_None, // G_FNEG = 197
7133 CEFBS_None, // G_FPEXT = 198
7134 CEFBS_None, // G_FPTRUNC = 199
7135 CEFBS_None, // G_FPTOSI = 200
7136 CEFBS_None, // G_FPTOUI = 201
7137 CEFBS_None, // G_SITOFP = 202
7138 CEFBS_None, // G_UITOFP = 203
7139 CEFBS_None, // G_FPTOSI_SAT = 204
7140 CEFBS_None, // G_FPTOUI_SAT = 205
7141 CEFBS_None, // G_FABS = 206
7142 CEFBS_None, // G_FCOPYSIGN = 207
7143 CEFBS_None, // G_IS_FPCLASS = 208
7144 CEFBS_None, // G_FCANONICALIZE = 209
7145 CEFBS_None, // G_FMINNUM = 210
7146 CEFBS_None, // G_FMAXNUM = 211
7147 CEFBS_None, // G_FMINNUM_IEEE = 212
7148 CEFBS_None, // G_FMAXNUM_IEEE = 213
7149 CEFBS_None, // G_FMINIMUM = 214
7150 CEFBS_None, // G_FMAXIMUM = 215
7151 CEFBS_None, // G_FMINIMUMNUM = 216
7152 CEFBS_None, // G_FMAXIMUMNUM = 217
7153 CEFBS_None, // G_GET_FPENV = 218
7154 CEFBS_None, // G_SET_FPENV = 219
7155 CEFBS_None, // G_RESET_FPENV = 220
7156 CEFBS_None, // G_GET_FPMODE = 221
7157 CEFBS_None, // G_SET_FPMODE = 222
7158 CEFBS_None, // G_RESET_FPMODE = 223
7159 CEFBS_None, // G_PTR_ADD = 224
7160 CEFBS_None, // G_PTRMASK = 225
7161 CEFBS_None, // G_SMIN = 226
7162 CEFBS_None, // G_SMAX = 227
7163 CEFBS_None, // G_UMIN = 228
7164 CEFBS_None, // G_UMAX = 229
7165 CEFBS_None, // G_ABS = 230
7166 CEFBS_None, // G_LROUND = 231
7167 CEFBS_None, // G_LLROUND = 232
7168 CEFBS_None, // G_BR = 233
7169 CEFBS_None, // G_BRJT = 234
7170 CEFBS_None, // G_VSCALE = 235
7171 CEFBS_None, // G_INSERT_SUBVECTOR = 236
7172 CEFBS_None, // G_EXTRACT_SUBVECTOR = 237
7173 CEFBS_None, // G_INSERT_VECTOR_ELT = 238
7174 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239
7175 CEFBS_None, // G_SHUFFLE_VECTOR = 240
7176 CEFBS_None, // G_SPLAT_VECTOR = 241
7177 CEFBS_None, // G_STEP_VECTOR = 242
7178 CEFBS_None, // G_VECTOR_COMPRESS = 243
7179 CEFBS_None, // G_CTTZ = 244
7180 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245
7181 CEFBS_None, // G_CTLZ = 246
7182 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247
7183 CEFBS_None, // G_CTPOP = 248
7184 CEFBS_None, // G_BSWAP = 249
7185 CEFBS_None, // G_BITREVERSE = 250
7186 CEFBS_None, // G_FCEIL = 251
7187 CEFBS_None, // G_FCOS = 252
7188 CEFBS_None, // G_FSIN = 253
7189 CEFBS_None, // G_FSINCOS = 254
7190 CEFBS_None, // G_FTAN = 255
7191 CEFBS_None, // G_FACOS = 256
7192 CEFBS_None, // G_FASIN = 257
7193 CEFBS_None, // G_FATAN = 258
7194 CEFBS_None, // G_FATAN2 = 259
7195 CEFBS_None, // G_FCOSH = 260
7196 CEFBS_None, // G_FSINH = 261
7197 CEFBS_None, // G_FTANH = 262
7198 CEFBS_None, // G_FSQRT = 263
7199 CEFBS_None, // G_FFLOOR = 264
7200 CEFBS_None, // G_FRINT = 265
7201 CEFBS_None, // G_FNEARBYINT = 266
7202 CEFBS_None, // G_ADDRSPACE_CAST = 267
7203 CEFBS_None, // G_BLOCK_ADDR = 268
7204 CEFBS_None, // G_JUMP_TABLE = 269
7205 CEFBS_None, // G_DYN_STACKALLOC = 270
7206 CEFBS_None, // G_STACKSAVE = 271
7207 CEFBS_None, // G_STACKRESTORE = 272
7208 CEFBS_None, // G_STRICT_FADD = 273
7209 CEFBS_None, // G_STRICT_FSUB = 274
7210 CEFBS_None, // G_STRICT_FMUL = 275
7211 CEFBS_None, // G_STRICT_FDIV = 276
7212 CEFBS_None, // G_STRICT_FREM = 277
7213 CEFBS_None, // G_STRICT_FMA = 278
7214 CEFBS_None, // G_STRICT_FSQRT = 279
7215 CEFBS_None, // G_STRICT_FLDEXP = 280
7216 CEFBS_None, // G_READ_REGISTER = 281
7217 CEFBS_None, // G_WRITE_REGISTER = 282
7218 CEFBS_None, // G_MEMCPY = 283
7219 CEFBS_None, // G_MEMCPY_INLINE = 284
7220 CEFBS_None, // G_MEMMOVE = 285
7221 CEFBS_None, // G_MEMSET = 286
7222 CEFBS_None, // G_BZERO = 287
7223 CEFBS_None, // G_TRAP = 288
7224 CEFBS_None, // G_DEBUGTRAP = 289
7225 CEFBS_None, // G_UBSANTRAP = 290
7226 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291
7227 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292
7228 CEFBS_None, // G_VECREDUCE_FADD = 293
7229 CEFBS_None, // G_VECREDUCE_FMUL = 294
7230 CEFBS_None, // G_VECREDUCE_FMAX = 295
7231 CEFBS_None, // G_VECREDUCE_FMIN = 296
7232 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297
7233 CEFBS_None, // G_VECREDUCE_FMINIMUM = 298
7234 CEFBS_None, // G_VECREDUCE_ADD = 299
7235 CEFBS_None, // G_VECREDUCE_MUL = 300
7236 CEFBS_None, // G_VECREDUCE_AND = 301
7237 CEFBS_None, // G_VECREDUCE_OR = 302
7238 CEFBS_None, // G_VECREDUCE_XOR = 303
7239 CEFBS_None, // G_VECREDUCE_SMAX = 304
7240 CEFBS_None, // G_VECREDUCE_SMIN = 305
7241 CEFBS_None, // G_VECREDUCE_UMAX = 306
7242 CEFBS_None, // G_VECREDUCE_UMIN = 307
7243 CEFBS_None, // G_SBFX = 308
7244 CEFBS_None, // G_UBFX = 309
7245 CEFBS_None, // CALL_PARAMS = 310
7246 CEFBS_None, // CALL_PARAMS_S = 311
7247 CEFBS_None, // CALL_RESULTS = 312
7248 CEFBS_None, // CALL_RESULTS_S = 313
7249 CEFBS_HasExceptionHandling, // CATCHRET = 314
7250 CEFBS_HasExceptionHandling, // CATCHRET_S = 315
7251 CEFBS_HasExceptionHandling, // CLEANUPRET = 316
7252 CEFBS_HasExceptionHandling, // CLEANUPRET_S = 317
7253 CEFBS_HasAtomics, // COMPILER_FENCE = 318
7254 CEFBS_HasAtomics, // COMPILER_FENCE_S = 319
7255 CEFBS_None, // RET_CALL_RESULTS = 320
7256 CEFBS_None, // RET_CALL_RESULTS_S = 321
7257 CEFBS_HasSIMD128_HasFP16, // ABS_F16x8 = 322
7258 CEFBS_HasSIMD128_HasFP16, // ABS_F16x8_S = 323
7259 CEFBS_None, // ABS_F32 = 324
7260 CEFBS_None, // ABS_F32_S = 325
7261 CEFBS_HasSIMD128, // ABS_F32x4 = 326
7262 CEFBS_HasSIMD128, // ABS_F32x4_S = 327
7263 CEFBS_None, // ABS_F64 = 328
7264 CEFBS_None, // ABS_F64_S = 329
7265 CEFBS_HasSIMD128, // ABS_F64x2 = 330
7266 CEFBS_HasSIMD128, // ABS_F64x2_S = 331
7267 CEFBS_HasSIMD128, // ABS_I16x8 = 332
7268 CEFBS_HasSIMD128, // ABS_I16x8_S = 333
7269 CEFBS_HasSIMD128, // ABS_I32x4 = 334
7270 CEFBS_HasSIMD128, // ABS_I32x4_S = 335
7271 CEFBS_HasSIMD128, // ABS_I64x2 = 336
7272 CEFBS_HasSIMD128, // ABS_I64x2_S = 337
7273 CEFBS_HasSIMD128, // ABS_I8x16 = 338
7274 CEFBS_HasSIMD128, // ABS_I8x16_S = 339
7275 CEFBS_HasSIMD128_HasFP16, // ADD_F16x8 = 340
7276 CEFBS_HasSIMD128_HasFP16, // ADD_F16x8_S = 341
7277 CEFBS_None, // ADD_F32 = 342
7278 CEFBS_None, // ADD_F32_S = 343
7279 CEFBS_HasSIMD128, // ADD_F32x4 = 344
7280 CEFBS_HasSIMD128, // ADD_F32x4_S = 345
7281 CEFBS_None, // ADD_F64 = 346
7282 CEFBS_None, // ADD_F64_S = 347
7283 CEFBS_HasSIMD128, // ADD_F64x2 = 348
7284 CEFBS_HasSIMD128, // ADD_F64x2_S = 349
7285 CEFBS_HasSIMD128, // ADD_I16x8 = 350
7286 CEFBS_HasSIMD128, // ADD_I16x8_S = 351
7287 CEFBS_None, // ADD_I32 = 352
7288 CEFBS_None, // ADD_I32_S = 353
7289 CEFBS_HasSIMD128, // ADD_I32x4 = 354
7290 CEFBS_HasSIMD128, // ADD_I32x4_S = 355
7291 CEFBS_None, // ADD_I64 = 356
7292 CEFBS_None, // ADD_I64_S = 357
7293 CEFBS_HasSIMD128, // ADD_I64x2 = 358
7294 CEFBS_HasSIMD128, // ADD_I64x2_S = 359
7295 CEFBS_HasSIMD128, // ADD_I8x16 = 360
7296 CEFBS_HasSIMD128, // ADD_I8x16_S = 361
7297 CEFBS_HasSIMD128, // ADD_SAT_S_I16x8 = 362
7298 CEFBS_HasSIMD128, // ADD_SAT_S_I16x8_S = 363
7299 CEFBS_HasSIMD128, // ADD_SAT_S_I8x16 = 364
7300 CEFBS_HasSIMD128, // ADD_SAT_S_I8x16_S = 365
7301 CEFBS_HasSIMD128, // ADD_SAT_U_I16x8 = 366
7302 CEFBS_HasSIMD128, // ADD_SAT_U_I16x8_S = 367
7303 CEFBS_HasSIMD128, // ADD_SAT_U_I8x16 = 368
7304 CEFBS_HasSIMD128, // ADD_SAT_U_I8x16_S = 369
7305 CEFBS_None, // ADJCALLSTACKDOWN = 370
7306 CEFBS_None, // ADJCALLSTACKDOWN_S = 371
7307 CEFBS_None, // ADJCALLSTACKUP = 372
7308 CEFBS_None, // ADJCALLSTACKUP_S = 373
7309 CEFBS_HasSIMD128, // ALLTRUE_I16x8 = 374
7310 CEFBS_HasSIMD128, // ALLTRUE_I16x8_S = 375
7311 CEFBS_HasSIMD128, // ALLTRUE_I32x4 = 376
7312 CEFBS_HasSIMD128, // ALLTRUE_I32x4_S = 377
7313 CEFBS_HasSIMD128, // ALLTRUE_I64x2 = 378
7314 CEFBS_HasSIMD128, // ALLTRUE_I64x2_S = 379
7315 CEFBS_HasSIMD128, // ALLTRUE_I8x16 = 380
7316 CEFBS_HasSIMD128, // ALLTRUE_I8x16_S = 381
7317 CEFBS_HasSIMD128, // AND = 382
7318 CEFBS_HasSIMD128, // ANDNOT = 383
7319 CEFBS_HasSIMD128, // ANDNOT_S = 384
7320 CEFBS_None, // AND_I32 = 385
7321 CEFBS_None, // AND_I32_S = 386
7322 CEFBS_None, // AND_I64 = 387
7323 CEFBS_None, // AND_I64_S = 388
7324 CEFBS_HasSIMD128, // AND_S = 389
7325 CEFBS_HasSIMD128, // ANYTRUE = 390
7326 CEFBS_HasSIMD128, // ANYTRUE_S = 391
7327 CEFBS_None, // ARGUMENT_exnref = 392
7328 CEFBS_None, // ARGUMENT_exnref_S = 393
7329 CEFBS_None, // ARGUMENT_externref = 394
7330 CEFBS_None, // ARGUMENT_externref_S = 395
7331 CEFBS_None, // ARGUMENT_f32 = 396
7332 CEFBS_None, // ARGUMENT_f32_S = 397
7333 CEFBS_None, // ARGUMENT_f64 = 398
7334 CEFBS_None, // ARGUMENT_f64_S = 399
7335 CEFBS_None, // ARGUMENT_funcref = 400
7336 CEFBS_None, // ARGUMENT_funcref_S = 401
7337 CEFBS_None, // ARGUMENT_i32 = 402
7338 CEFBS_None, // ARGUMENT_i32_S = 403
7339 CEFBS_None, // ARGUMENT_i64 = 404
7340 CEFBS_None, // ARGUMENT_i64_S = 405
7341 CEFBS_None, // ARGUMENT_v16i8 = 406
7342 CEFBS_None, // ARGUMENT_v16i8_S = 407
7343 CEFBS_None, // ARGUMENT_v2f64 = 408
7344 CEFBS_None, // ARGUMENT_v2f64_S = 409
7345 CEFBS_None, // ARGUMENT_v2i64 = 410
7346 CEFBS_None, // ARGUMENT_v2i64_S = 411
7347 CEFBS_None, // ARGUMENT_v4f32 = 412
7348 CEFBS_None, // ARGUMENT_v4f32_S = 413
7349 CEFBS_None, // ARGUMENT_v4i32 = 414
7350 CEFBS_None, // ARGUMENT_v4i32_S = 415
7351 CEFBS_None, // ARGUMENT_v8f16 = 416
7352 CEFBS_None, // ARGUMENT_v8f16_S = 417
7353 CEFBS_None, // ARGUMENT_v8i16 = 418
7354 CEFBS_None, // ARGUMENT_v8i16_S = 419
7355 CEFBS_HasAtomics, // ATOMIC_FENCE = 420
7356 CEFBS_HasAtomics, // ATOMIC_FENCE_S = 421
7357 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32 = 422
7358 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32_S = 423
7359 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64 = 424
7360 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64_S = 425
7361 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32 = 426
7362 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32_S = 427
7363 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64 = 428
7364 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64_S = 429
7365 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32 = 430
7366 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32_S = 431
7367 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64 = 432
7368 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64_S = 433
7369 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32 = 434
7370 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32_S = 435
7371 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64 = 436
7372 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64_S = 437
7373 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32 = 438
7374 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32_S = 439
7375 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64 = 440
7376 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64_S = 441
7377 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32 = 442
7378 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32_S = 443
7379 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64 = 444
7380 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64_S = 445
7381 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32 = 446
7382 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32_S = 447
7383 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64 = 448
7384 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64_S = 449
7385 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32 = 450
7386 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32_S = 451
7387 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64 = 452
7388 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64_S = 453
7389 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32 = 454
7390 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32_S = 455
7391 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64 = 456
7392 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64_S = 457
7393 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32 = 458
7394 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32_S = 459
7395 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64 = 460
7396 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64_S = 461
7397 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32 = 462
7398 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32_S = 463
7399 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64 = 464
7400 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64_S = 465
7401 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32 = 466
7402 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S = 467
7403 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64 = 468
7404 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S = 469
7405 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32 = 470
7406 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S = 471
7407 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64 = 472
7408 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S = 473
7409 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32 = 474
7410 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32_S = 475
7411 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64 = 476
7412 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64_S = 477
7413 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32 = 478
7414 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32_S = 479
7415 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64 = 480
7416 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64_S = 481
7417 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32 = 482
7418 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32_S = 483
7419 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64 = 484
7420 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64_S = 485
7421 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32 = 486
7422 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32_S = 487
7423 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64 = 488
7424 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64_S = 489
7425 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32 = 490
7426 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32_S = 491
7427 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64 = 492
7428 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64_S = 493
7429 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32 = 494
7430 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32_S = 495
7431 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64 = 496
7432 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64_S = 497
7433 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32 = 498
7434 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32_S = 499
7435 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64 = 500
7436 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64_S = 501
7437 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32 = 502
7438 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32_S = 503
7439 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64 = 504
7440 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64_S = 505
7441 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32 = 506
7442 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32_S = 507
7443 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64 = 508
7444 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64_S = 509
7445 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32 = 510
7446 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32_S = 511
7447 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64 = 512
7448 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64_S = 513
7449 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32 = 514
7450 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S = 515
7451 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64 = 516
7452 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S = 517
7453 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32 = 518
7454 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32_S = 519
7455 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64 = 520
7456 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64_S = 521
7457 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32 = 522
7458 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32_S = 523
7459 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64 = 524
7460 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64_S = 525
7461 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32 = 526
7462 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32_S = 527
7463 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64 = 528
7464 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64_S = 529
7465 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32 = 530
7466 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32_S = 531
7467 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64 = 532
7468 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64_S = 533
7469 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32 = 534
7470 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32_S = 535
7471 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64 = 536
7472 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64_S = 537
7473 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32 = 538
7474 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32_S = 539
7475 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64 = 540
7476 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64_S = 541
7477 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32 = 542
7478 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32_S = 543
7479 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64 = 544
7480 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64_S = 545
7481 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32 = 546
7482 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32_S = 547
7483 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64 = 548
7484 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64_S = 549
7485 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32 = 550
7486 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S = 551
7487 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64 = 552
7488 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S = 553
7489 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32 = 554
7490 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S = 555
7491 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64 = 556
7492 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S = 557
7493 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32 = 558
7494 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32_S = 559
7495 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64 = 560
7496 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64_S = 561
7497 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32 = 562
7498 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32_S = 563
7499 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64 = 564
7500 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64_S = 565
7501 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32 = 566
7502 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32_S = 567
7503 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64 = 568
7504 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64_S = 569
7505 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32 = 570
7506 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32_S = 571
7507 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64 = 572
7508 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64_S = 573
7509 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32 = 574
7510 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32_S = 575
7511 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64 = 576
7512 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64_S = 577
7513 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32 = 578
7514 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32_S = 579
7515 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64 = 580
7516 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64_S = 581
7517 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32 = 582
7518 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32_S = 583
7519 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64 = 584
7520 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64_S = 585
7521 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32 = 586
7522 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32_S = 587
7523 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64 = 588
7524 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64_S = 589
7525 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32 = 590
7526 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32_S = 591
7527 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64 = 592
7528 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64_S = 593
7529 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32 = 594
7530 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32_S = 595
7531 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64 = 596
7532 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64_S = 597
7533 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32 = 598
7534 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32_S = 599
7535 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64 = 600
7536 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64_S = 601
7537 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32 = 602
7538 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32_S = 603
7539 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64 = 604
7540 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64_S = 605
7541 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32 = 606
7542 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32_S = 607
7543 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64 = 608
7544 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64_S = 609
7545 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32 = 610
7546 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32_S = 611
7547 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64 = 612
7548 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64_S = 613
7549 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32 = 614
7550 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32_S = 615
7551 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64 = 616
7552 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64_S = 617
7553 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32 = 618
7554 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32_S = 619
7555 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64 = 620
7556 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64_S = 621
7557 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32 = 622
7558 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32_S = 623
7559 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64 = 624
7560 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64_S = 625
7561 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32 = 626
7562 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32_S = 627
7563 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64 = 628
7564 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64_S = 629
7565 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32 = 630
7566 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32_S = 631
7567 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64 = 632
7568 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64_S = 633
7569 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32 = 634
7570 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32_S = 635
7571 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64 = 636
7572 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64_S = 637
7573 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32 = 638
7574 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32_S = 639
7575 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64 = 640
7576 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64_S = 641
7577 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32 = 642
7578 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32_S = 643
7579 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64 = 644
7580 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64_S = 645
7581 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32 = 646
7582 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32_S = 647
7583 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64 = 648
7584 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64_S = 649
7585 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32 = 650
7586 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32_S = 651
7587 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64 = 652
7588 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64_S = 653
7589 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32 = 654
7590 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32_S = 655
7591 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64 = 656
7592 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64_S = 657
7593 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32 = 658
7594 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32_S = 659
7595 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64 = 660
7596 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64_S = 661
7597 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32 = 662
7598 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32_S = 663
7599 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64 = 664
7600 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64_S = 665
7601 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32 = 666
7602 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32_S = 667
7603 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64 = 668
7604 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64_S = 669
7605 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32 = 670
7606 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32_S = 671
7607 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64 = 672
7608 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64_S = 673
7609 CEFBS_HasSIMD128, // AVGR_U_I16x8 = 674
7610 CEFBS_HasSIMD128, // AVGR_U_I16x8_S = 675
7611 CEFBS_HasSIMD128, // AVGR_U_I8x16 = 676
7612 CEFBS_HasSIMD128, // AVGR_U_I8x16_S = 677
7613 CEFBS_HasSIMD128, // BITMASK_I16x8 = 678
7614 CEFBS_HasSIMD128, // BITMASK_I16x8_S = 679
7615 CEFBS_HasSIMD128, // BITMASK_I32x4 = 680
7616 CEFBS_HasSIMD128, // BITMASK_I32x4_S = 681
7617 CEFBS_HasSIMD128, // BITMASK_I64x2 = 682
7618 CEFBS_HasSIMD128, // BITMASK_I64x2_S = 683
7619 CEFBS_HasSIMD128, // BITMASK_I8x16 = 684
7620 CEFBS_HasSIMD128, // BITMASK_I8x16_S = 685
7621 CEFBS_HasSIMD128, // BITSELECT = 686
7622 CEFBS_HasSIMD128, // BITSELECT_S = 687
7623 CEFBS_None, // BLOCK = 688
7624 CEFBS_None, // BLOCK_S = 689
7625 CEFBS_None, // BR = 690
7626 CEFBS_None, // BR_IF = 691
7627 CEFBS_None, // BR_IF_S = 692
7628 CEFBS_None, // BR_S = 693
7629 CEFBS_None, // BR_TABLE_I32 = 694
7630 CEFBS_None, // BR_TABLE_I32_S = 695
7631 CEFBS_None, // BR_TABLE_I64 = 696
7632 CEFBS_None, // BR_TABLE_I64_S = 697
7633 CEFBS_None, // BR_UNLESS = 698
7634 CEFBS_None, // BR_UNLESS_S = 699
7635 CEFBS_None, // CALL = 700
7636 CEFBS_None, // CALL_INDIRECT = 701
7637 CEFBS_None, // CALL_INDIRECT_S = 702
7638 CEFBS_None, // CALL_S = 703
7639 CEFBS_HasExceptionHandling, // CATCH = 704
7640 CEFBS_HasExceptionHandling, // CATCH_ALL = 705
7641 CEFBS_HasExceptionHandling, // CATCH_ALL_LEGACY = 706
7642 CEFBS_HasExceptionHandling, // CATCH_ALL_LEGACY_S = 707
7643 CEFBS_HasExceptionHandling, // CATCH_ALL_REF = 708
7644 CEFBS_HasExceptionHandling, // CATCH_ALL_REF_S = 709
7645 CEFBS_HasExceptionHandling, // CATCH_ALL_S = 710
7646 CEFBS_HasExceptionHandling, // CATCH_LEGACY = 711
7647 CEFBS_HasExceptionHandling, // CATCH_LEGACY_S = 712
7648 CEFBS_HasExceptionHandling, // CATCH_REF = 713
7649 CEFBS_HasExceptionHandling, // CATCH_REF_S = 714
7650 CEFBS_HasExceptionHandling, // CATCH_S = 715
7651 CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8 = 716
7652 CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8_S = 717
7653 CEFBS_None, // CEIL_F32 = 718
7654 CEFBS_None, // CEIL_F32_S = 719
7655 CEFBS_HasSIMD128, // CEIL_F32x4 = 720
7656 CEFBS_HasSIMD128, // CEIL_F32x4_S = 721
7657 CEFBS_None, // CEIL_F64 = 722
7658 CEFBS_None, // CEIL_F64_S = 723
7659 CEFBS_HasSIMD128, // CEIL_F64x2 = 724
7660 CEFBS_HasSIMD128, // CEIL_F64x2_S = 725
7661 CEFBS_None, // CLZ_I32 = 726
7662 CEFBS_None, // CLZ_I32_S = 727
7663 CEFBS_None, // CLZ_I64 = 728
7664 CEFBS_None, // CLZ_I64_S = 729
7665 CEFBS_None, // CONST_F32 = 730
7666 CEFBS_None, // CONST_F32_S = 731
7667 CEFBS_None, // CONST_F64 = 732
7668 CEFBS_None, // CONST_F64_S = 733
7669 CEFBS_None, // CONST_I32 = 734
7670 CEFBS_None, // CONST_I32_S = 735
7671 CEFBS_None, // CONST_I64 = 736
7672 CEFBS_None, // CONST_I64_S = 737
7673 CEFBS_HasSIMD128, // CONST_V128_F32x4 = 738
7674 CEFBS_HasSIMD128, // CONST_V128_F32x4_S = 739
7675 CEFBS_HasSIMD128, // CONST_V128_F64x2 = 740
7676 CEFBS_HasSIMD128, // CONST_V128_F64x2_S = 741
7677 CEFBS_HasSIMD128, // CONST_V128_I16x8 = 742
7678 CEFBS_HasSIMD128, // CONST_V128_I16x8_S = 743
7679 CEFBS_HasSIMD128, // CONST_V128_I32x4 = 744
7680 CEFBS_HasSIMD128, // CONST_V128_I32x4_S = 745
7681 CEFBS_HasSIMD128, // CONST_V128_I64x2 = 746
7682 CEFBS_HasSIMD128, // CONST_V128_I64x2_S = 747
7683 CEFBS_HasSIMD128, // CONST_V128_I8x16 = 748
7684 CEFBS_HasSIMD128, // CONST_V128_I8x16_S = 749
7685 CEFBS_None, // COPYSIGN_F32 = 750
7686 CEFBS_None, // COPYSIGN_F32_S = 751
7687 CEFBS_None, // COPYSIGN_F64 = 752
7688 CEFBS_None, // COPYSIGN_F64_S = 753
7689 CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF = 754
7690 CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF_S = 755
7691 CEFBS_HasReferenceTypes, // COPY_EXTERNREF = 756
7692 CEFBS_HasReferenceTypes, // COPY_EXTERNREF_S = 757
7693 CEFBS_None, // COPY_F32 = 758
7694 CEFBS_None, // COPY_F32_S = 759
7695 CEFBS_None, // COPY_F64 = 760
7696 CEFBS_None, // COPY_F64_S = 761
7697 CEFBS_HasReferenceTypes, // COPY_FUNCREF = 762
7698 CEFBS_HasReferenceTypes, // COPY_FUNCREF_S = 763
7699 CEFBS_None, // COPY_I32 = 764
7700 CEFBS_None, // COPY_I32_S = 765
7701 CEFBS_None, // COPY_I64 = 766
7702 CEFBS_None, // COPY_I64_S = 767
7703 CEFBS_HasSIMD128, // COPY_V128 = 768
7704 CEFBS_HasSIMD128, // COPY_V128_S = 769
7705 CEFBS_None, // CTZ_I32 = 770
7706 CEFBS_None, // CTZ_I32_S = 771
7707 CEFBS_None, // CTZ_I64 = 772
7708 CEFBS_None, // CTZ_I64_S = 773
7709 CEFBS_HasBulkMemoryOpt, // DATA_DROP = 774
7710 CEFBS_HasBulkMemoryOpt, // DATA_DROP_S = 775
7711 CEFBS_None, // DEBUG_UNREACHABLE = 776
7712 CEFBS_None, // DEBUG_UNREACHABLE_S = 777
7713 CEFBS_HasExceptionHandling, // DELEGATE = 778
7714 CEFBS_HasExceptionHandling, // DELEGATE_S = 779
7715 CEFBS_HasSIMD128_HasFP16, // DIV_F16x8 = 780
7716 CEFBS_HasSIMD128_HasFP16, // DIV_F16x8_S = 781
7717 CEFBS_None, // DIV_F32 = 782
7718 CEFBS_None, // DIV_F32_S = 783
7719 CEFBS_HasSIMD128, // DIV_F32x4 = 784
7720 CEFBS_HasSIMD128, // DIV_F32x4_S = 785
7721 CEFBS_None, // DIV_F64 = 786
7722 CEFBS_None, // DIV_F64_S = 787
7723 CEFBS_HasSIMD128, // DIV_F64x2 = 788
7724 CEFBS_HasSIMD128, // DIV_F64x2_S = 789
7725 CEFBS_None, // DIV_S_I32 = 790
7726 CEFBS_None, // DIV_S_I32_S = 791
7727 CEFBS_None, // DIV_S_I64 = 792
7728 CEFBS_None, // DIV_S_I64_S = 793
7729 CEFBS_None, // DIV_U_I32 = 794
7730 CEFBS_None, // DIV_U_I32_S = 795
7731 CEFBS_None, // DIV_U_I64 = 796
7732 CEFBS_None, // DIV_U_I64_S = 797
7733 CEFBS_HasSIMD128, // DOT = 798
7734 CEFBS_HasSIMD128, // DOT_S = 799
7735 CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF = 800
7736 CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF_S = 801
7737 CEFBS_HasReferenceTypes, // DROP_EXTERNREF = 802
7738 CEFBS_HasReferenceTypes, // DROP_EXTERNREF_S = 803
7739 CEFBS_None, // DROP_F32 = 804
7740 CEFBS_None, // DROP_F32_S = 805
7741 CEFBS_None, // DROP_F64 = 806
7742 CEFBS_None, // DROP_F64_S = 807
7743 CEFBS_HasReferenceTypes, // DROP_FUNCREF = 808
7744 CEFBS_HasReferenceTypes, // DROP_FUNCREF_S = 809
7745 CEFBS_None, // DROP_I32 = 810
7746 CEFBS_None, // DROP_I32_S = 811
7747 CEFBS_None, // DROP_I64 = 812
7748 CEFBS_None, // DROP_I64_S = 813
7749 CEFBS_HasSIMD128, // DROP_V128 = 814
7750 CEFBS_HasSIMD128, // DROP_V128_S = 815
7751 CEFBS_None, // ELSE = 816
7752 CEFBS_None, // ELSE_S = 817
7753 CEFBS_None, // END = 818
7754 CEFBS_None, // END_BLOCK = 819
7755 CEFBS_None, // END_BLOCK_S = 820
7756 CEFBS_None, // END_FUNCTION = 821
7757 CEFBS_None, // END_FUNCTION_S = 822
7758 CEFBS_None, // END_IF = 823
7759 CEFBS_None, // END_IF_S = 824
7760 CEFBS_None, // END_LOOP = 825
7761 CEFBS_None, // END_LOOP_S = 826
7762 CEFBS_None, // END_S = 827
7763 CEFBS_HasExceptionHandling, // END_TRY = 828
7764 CEFBS_HasExceptionHandling, // END_TRY_S = 829
7765 CEFBS_HasExceptionHandling, // END_TRY_TABLE = 830
7766 CEFBS_HasExceptionHandling, // END_TRY_TABLE_S = 831
7767 CEFBS_None, // EQZ_I32 = 832
7768 CEFBS_None, // EQZ_I32_S = 833
7769 CEFBS_None, // EQZ_I64 = 834
7770 CEFBS_None, // EQZ_I64_S = 835
7771 CEFBS_HasSIMD128_HasFP16, // EQ_F16x8 = 836
7772 CEFBS_HasSIMD128_HasFP16, // EQ_F16x8_S = 837
7773 CEFBS_None, // EQ_F32 = 838
7774 CEFBS_None, // EQ_F32_S = 839
7775 CEFBS_HasSIMD128, // EQ_F32x4 = 840
7776 CEFBS_HasSIMD128, // EQ_F32x4_S = 841
7777 CEFBS_None, // EQ_F64 = 842
7778 CEFBS_None, // EQ_F64_S = 843
7779 CEFBS_HasSIMD128, // EQ_F64x2 = 844
7780 CEFBS_HasSIMD128, // EQ_F64x2_S = 845
7781 CEFBS_HasSIMD128, // EQ_I16x8 = 846
7782 CEFBS_HasSIMD128, // EQ_I16x8_S = 847
7783 CEFBS_None, // EQ_I32 = 848
7784 CEFBS_None, // EQ_I32_S = 849
7785 CEFBS_HasSIMD128, // EQ_I32x4 = 850
7786 CEFBS_HasSIMD128, // EQ_I32x4_S = 851
7787 CEFBS_None, // EQ_I64 = 852
7788 CEFBS_None, // EQ_I64_S = 853
7789 CEFBS_HasSIMD128, // EQ_I64x2 = 854
7790 CEFBS_HasSIMD128, // EQ_I64x2_S = 855
7791 CEFBS_HasSIMD128, // EQ_I8x16 = 856
7792 CEFBS_HasSIMD128, // EQ_I8x16_S = 857
7793 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8 = 858
7794 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8_S = 859
7795 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4 = 860
7796 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4_S = 861
7797 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2 = 862
7798 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2_S = 863
7799 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8 = 864
7800 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8_S = 865
7801 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4 = 866
7802 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4_S = 867
7803 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2 = 868
7804 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2_S = 869
7805 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8 = 870
7806 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8_S = 871
7807 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4 = 872
7808 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4_S = 873
7809 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2 = 874
7810 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2_S = 875
7811 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8 = 876
7812 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8_S = 877
7813 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4 = 878
7814 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4_S = 879
7815 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2 = 880
7816 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2_S = 881
7817 CEFBS_HasFP16, // EXTRACT_LANE_F16x8 = 882
7818 CEFBS_HasFP16, // EXTRACT_LANE_F16x8_S = 883
7819 CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4 = 884
7820 CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4_S = 885
7821 CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2 = 886
7822 CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2_S = 887
7823 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s = 888
7824 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s_S = 889
7825 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u = 890
7826 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u_S = 891
7827 CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4 = 892
7828 CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4_S = 893
7829 CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2 = 894
7830 CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2_S = 895
7831 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s = 896
7832 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s_S = 897
7833 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u = 898
7834 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u_S = 899
7835 CEFBS_None, // F32_CONVERT_S_I32 = 900
7836 CEFBS_None, // F32_CONVERT_S_I32_S = 901
7837 CEFBS_None, // F32_CONVERT_S_I64 = 902
7838 CEFBS_None, // F32_CONVERT_S_I64_S = 903
7839 CEFBS_None, // F32_CONVERT_U_I32 = 904
7840 CEFBS_None, // F32_CONVERT_U_I32_S = 905
7841 CEFBS_None, // F32_CONVERT_U_I64 = 906
7842 CEFBS_None, // F32_CONVERT_U_I64_S = 907
7843 CEFBS_None, // F32_DEMOTE_F64 = 908
7844 CEFBS_None, // F32_DEMOTE_F64_S = 909
7845 CEFBS_None, // F32_REINTERPRET_I32 = 910
7846 CEFBS_None, // F32_REINTERPRET_I32_S = 911
7847 CEFBS_None, // F64_CONVERT_S_I32 = 912
7848 CEFBS_None, // F64_CONVERT_S_I32_S = 913
7849 CEFBS_None, // F64_CONVERT_S_I64 = 914
7850 CEFBS_None, // F64_CONVERT_S_I64_S = 915
7851 CEFBS_None, // F64_CONVERT_U_I32 = 916
7852 CEFBS_None, // F64_CONVERT_U_I32_S = 917
7853 CEFBS_None, // F64_CONVERT_U_I64 = 918
7854 CEFBS_None, // F64_CONVERT_U_I64_S = 919
7855 CEFBS_None, // F64_PROMOTE_F32 = 920
7856 CEFBS_None, // F64_PROMOTE_F32_S = 921
7857 CEFBS_None, // F64_REINTERPRET_I64 = 922
7858 CEFBS_None, // F64_REINTERPRET_I64_S = 923
7859 CEFBS_None, // FALLTHROUGH_RETURN = 924
7860 CEFBS_None, // FALLTHROUGH_RETURN_S = 925
7861 CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8 = 926
7862 CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8_S = 927
7863 CEFBS_None, // FLOOR_F32 = 928
7864 CEFBS_None, // FLOOR_F32_S = 929
7865 CEFBS_HasSIMD128, // FLOOR_F32x4 = 930
7866 CEFBS_HasSIMD128, // FLOOR_F32x4_S = 931
7867 CEFBS_None, // FLOOR_F64 = 932
7868 CEFBS_None, // FLOOR_F64_S = 933
7869 CEFBS_HasSIMD128, // FLOOR_F64x2 = 934
7870 CEFBS_HasSIMD128, // FLOOR_F64x2_S = 935
7871 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32 = 936
7872 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32_S = 937
7873 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64 = 938
7874 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64_S = 939
7875 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32 = 940
7876 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32_S = 941
7877 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64 = 942
7878 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64_S = 943
7879 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32 = 944
7880 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32_S = 945
7881 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64 = 946
7882 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64_S = 947
7883 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32 = 948
7884 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32_S = 949
7885 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64 = 950
7886 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64_S = 951
7887 CEFBS_HasSIMD128_HasFP16, // GE_F16x8 = 952
7888 CEFBS_HasSIMD128_HasFP16, // GE_F16x8_S = 953
7889 CEFBS_None, // GE_F32 = 954
7890 CEFBS_None, // GE_F32_S = 955
7891 CEFBS_HasSIMD128, // GE_F32x4 = 956
7892 CEFBS_HasSIMD128, // GE_F32x4_S = 957
7893 CEFBS_None, // GE_F64 = 958
7894 CEFBS_None, // GE_F64_S = 959
7895 CEFBS_HasSIMD128, // GE_F64x2 = 960
7896 CEFBS_HasSIMD128, // GE_F64x2_S = 961
7897 CEFBS_HasSIMD128, // GE_S_I16x8 = 962
7898 CEFBS_HasSIMD128, // GE_S_I16x8_S = 963
7899 CEFBS_None, // GE_S_I32 = 964
7900 CEFBS_None, // GE_S_I32_S = 965
7901 CEFBS_HasSIMD128, // GE_S_I32x4 = 966
7902 CEFBS_HasSIMD128, // GE_S_I32x4_S = 967
7903 CEFBS_None, // GE_S_I64 = 968
7904 CEFBS_None, // GE_S_I64_S = 969
7905 CEFBS_HasSIMD128, // GE_S_I64x2 = 970
7906 CEFBS_HasSIMD128, // GE_S_I64x2_S = 971
7907 CEFBS_HasSIMD128, // GE_S_I8x16 = 972
7908 CEFBS_HasSIMD128, // GE_S_I8x16_S = 973
7909 CEFBS_HasSIMD128, // GE_U_I16x8 = 974
7910 CEFBS_HasSIMD128, // GE_U_I16x8_S = 975
7911 CEFBS_None, // GE_U_I32 = 976
7912 CEFBS_None, // GE_U_I32_S = 977
7913 CEFBS_HasSIMD128, // GE_U_I32x4 = 978
7914 CEFBS_HasSIMD128, // GE_U_I32x4_S = 979
7915 CEFBS_None, // GE_U_I64 = 980
7916 CEFBS_None, // GE_U_I64_S = 981
7917 CEFBS_HasSIMD128, // GE_U_I8x16 = 982
7918 CEFBS_HasSIMD128, // GE_U_I8x16_S = 983
7919 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF = 984
7920 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF_S = 985
7921 CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF = 986
7922 CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF_S = 987
7923 CEFBS_None, // GLOBAL_GET_F32 = 988
7924 CEFBS_None, // GLOBAL_GET_F32_S = 989
7925 CEFBS_None, // GLOBAL_GET_F64 = 990
7926 CEFBS_None, // GLOBAL_GET_F64_S = 991
7927 CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF = 992
7928 CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF_S = 993
7929 CEFBS_None, // GLOBAL_GET_I32 = 994
7930 CEFBS_None, // GLOBAL_GET_I32_S = 995
7931 CEFBS_None, // GLOBAL_GET_I64 = 996
7932 CEFBS_None, // GLOBAL_GET_I64_S = 997
7933 CEFBS_HasSIMD128, // GLOBAL_GET_V128 = 998
7934 CEFBS_HasSIMD128, // GLOBAL_GET_V128_S = 999
7935 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF = 1000
7936 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF_S = 1001
7937 CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF = 1002
7938 CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF_S = 1003
7939 CEFBS_None, // GLOBAL_SET_F32 = 1004
7940 CEFBS_None, // GLOBAL_SET_F32_S = 1005
7941 CEFBS_None, // GLOBAL_SET_F64 = 1006
7942 CEFBS_None, // GLOBAL_SET_F64_S = 1007
7943 CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF = 1008
7944 CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF_S = 1009
7945 CEFBS_None, // GLOBAL_SET_I32 = 1010
7946 CEFBS_None, // GLOBAL_SET_I32_S = 1011
7947 CEFBS_None, // GLOBAL_SET_I64 = 1012
7948 CEFBS_None, // GLOBAL_SET_I64_S = 1013
7949 CEFBS_HasSIMD128, // GLOBAL_SET_V128 = 1014
7950 CEFBS_HasSIMD128, // GLOBAL_SET_V128_S = 1015
7951 CEFBS_HasSIMD128_HasFP16, // GT_F16x8 = 1016
7952 CEFBS_HasSIMD128_HasFP16, // GT_F16x8_S = 1017
7953 CEFBS_None, // GT_F32 = 1018
7954 CEFBS_None, // GT_F32_S = 1019
7955 CEFBS_HasSIMD128, // GT_F32x4 = 1020
7956 CEFBS_HasSIMD128, // GT_F32x4_S = 1021
7957 CEFBS_None, // GT_F64 = 1022
7958 CEFBS_None, // GT_F64_S = 1023
7959 CEFBS_HasSIMD128, // GT_F64x2 = 1024
7960 CEFBS_HasSIMD128, // GT_F64x2_S = 1025
7961 CEFBS_HasSIMD128, // GT_S_I16x8 = 1026
7962 CEFBS_HasSIMD128, // GT_S_I16x8_S = 1027
7963 CEFBS_None, // GT_S_I32 = 1028
7964 CEFBS_None, // GT_S_I32_S = 1029
7965 CEFBS_HasSIMD128, // GT_S_I32x4 = 1030
7966 CEFBS_HasSIMD128, // GT_S_I32x4_S = 1031
7967 CEFBS_None, // GT_S_I64 = 1032
7968 CEFBS_None, // GT_S_I64_S = 1033
7969 CEFBS_HasSIMD128, // GT_S_I64x2 = 1034
7970 CEFBS_HasSIMD128, // GT_S_I64x2_S = 1035
7971 CEFBS_HasSIMD128, // GT_S_I8x16 = 1036
7972 CEFBS_HasSIMD128, // GT_S_I8x16_S = 1037
7973 CEFBS_HasSIMD128, // GT_U_I16x8 = 1038
7974 CEFBS_HasSIMD128, // GT_U_I16x8_S = 1039
7975 CEFBS_None, // GT_U_I32 = 1040
7976 CEFBS_None, // GT_U_I32_S = 1041
7977 CEFBS_HasSIMD128, // GT_U_I32x4 = 1042
7978 CEFBS_HasSIMD128, // GT_U_I32x4_S = 1043
7979 CEFBS_None, // GT_U_I64 = 1044
7980 CEFBS_None, // GT_U_I64_S = 1045
7981 CEFBS_HasSIMD128, // GT_U_I8x16 = 1046
7982 CEFBS_HasSIMD128, // GT_U_I8x16_S = 1047
7983 CEFBS_HasSignExt, // I32_EXTEND16_S_I32 = 1048
7984 CEFBS_HasSignExt, // I32_EXTEND16_S_I32_S = 1049
7985 CEFBS_HasSignExt, // I32_EXTEND8_S_I32 = 1050
7986 CEFBS_HasSignExt, // I32_EXTEND8_S_I32_S = 1051
7987 CEFBS_None, // I32_REINTERPRET_F32 = 1052
7988 CEFBS_None, // I32_REINTERPRET_F32_S = 1053
7989 CEFBS_None, // I32_TRUNC_S_F32 = 1054
7990 CEFBS_None, // I32_TRUNC_S_F32_S = 1055
7991 CEFBS_None, // I32_TRUNC_S_F64 = 1056
7992 CEFBS_None, // I32_TRUNC_S_F64_S = 1057
7993 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32 = 1058
7994 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32_S = 1059
7995 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64 = 1060
7996 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64_S = 1061
7997 CEFBS_None, // I32_TRUNC_U_F32 = 1062
7998 CEFBS_None, // I32_TRUNC_U_F32_S = 1063
7999 CEFBS_None, // I32_TRUNC_U_F64 = 1064
8000 CEFBS_None, // I32_TRUNC_U_F64_S = 1065
8001 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32 = 1066
8002 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32_S = 1067
8003 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64 = 1068
8004 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64_S = 1069
8005 CEFBS_None, // I32_WRAP_I64 = 1070
8006 CEFBS_None, // I32_WRAP_I64_S = 1071
8007 CEFBS_HasWideArithmetic, // I64_ADD128 = 1072
8008 CEFBS_HasWideArithmetic, // I64_ADD128_S = 1073
8009 CEFBS_HasSignExt, // I64_EXTEND16_S_I64 = 1074
8010 CEFBS_HasSignExt, // I64_EXTEND16_S_I64_S = 1075
8011 CEFBS_HasSignExt, // I64_EXTEND32_S_I64 = 1076
8012 CEFBS_HasSignExt, // I64_EXTEND32_S_I64_S = 1077
8013 CEFBS_HasSignExt, // I64_EXTEND8_S_I64 = 1078
8014 CEFBS_HasSignExt, // I64_EXTEND8_S_I64_S = 1079
8015 CEFBS_None, // I64_EXTEND_S_I32 = 1080
8016 CEFBS_None, // I64_EXTEND_S_I32_S = 1081
8017 CEFBS_None, // I64_EXTEND_U_I32 = 1082
8018 CEFBS_None, // I64_EXTEND_U_I32_S = 1083
8019 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_S = 1084
8020 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_S_S = 1085
8021 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_U = 1086
8022 CEFBS_HasWideArithmetic, // I64_MUL_WIDE_U_S = 1087
8023 CEFBS_None, // I64_REINTERPRET_F64 = 1088
8024 CEFBS_None, // I64_REINTERPRET_F64_S = 1089
8025 CEFBS_HasWideArithmetic, // I64_SUB128 = 1090
8026 CEFBS_HasWideArithmetic, // I64_SUB128_S = 1091
8027 CEFBS_None, // I64_TRUNC_S_F32 = 1092
8028 CEFBS_None, // I64_TRUNC_S_F32_S = 1093
8029 CEFBS_None, // I64_TRUNC_S_F64 = 1094
8030 CEFBS_None, // I64_TRUNC_S_F64_S = 1095
8031 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32 = 1096
8032 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32_S = 1097
8033 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64 = 1098
8034 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64_S = 1099
8035 CEFBS_None, // I64_TRUNC_U_F32 = 1100
8036 CEFBS_None, // I64_TRUNC_U_F32_S = 1101
8037 CEFBS_None, // I64_TRUNC_U_F64 = 1102
8038 CEFBS_None, // I64_TRUNC_U_F64_S = 1103
8039 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32 = 1104
8040 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32_S = 1105
8041 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64 = 1106
8042 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64_S = 1107
8043 CEFBS_None, // IF = 1108
8044 CEFBS_None, // IF_S = 1109
8045 CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8 = 1110
8046 CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8_S = 1111
8047 CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4 = 1112
8048 CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4_S = 1113
8049 CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2 = 1114
8050 CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2_S = 1115
8051 CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16 = 1116
8052 CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16_S = 1117
8053 CEFBS_HasSIMD128_HasFP16, // LE_F16x8 = 1118
8054 CEFBS_HasSIMD128_HasFP16, // LE_F16x8_S = 1119
8055 CEFBS_None, // LE_F32 = 1120
8056 CEFBS_None, // LE_F32_S = 1121
8057 CEFBS_HasSIMD128, // LE_F32x4 = 1122
8058 CEFBS_HasSIMD128, // LE_F32x4_S = 1123
8059 CEFBS_None, // LE_F64 = 1124
8060 CEFBS_None, // LE_F64_S = 1125
8061 CEFBS_HasSIMD128, // LE_F64x2 = 1126
8062 CEFBS_HasSIMD128, // LE_F64x2_S = 1127
8063 CEFBS_HasSIMD128, // LE_S_I16x8 = 1128
8064 CEFBS_HasSIMD128, // LE_S_I16x8_S = 1129
8065 CEFBS_None, // LE_S_I32 = 1130
8066 CEFBS_None, // LE_S_I32_S = 1131
8067 CEFBS_HasSIMD128, // LE_S_I32x4 = 1132
8068 CEFBS_HasSIMD128, // LE_S_I32x4_S = 1133
8069 CEFBS_None, // LE_S_I64 = 1134
8070 CEFBS_None, // LE_S_I64_S = 1135
8071 CEFBS_HasSIMD128, // LE_S_I64x2 = 1136
8072 CEFBS_HasSIMD128, // LE_S_I64x2_S = 1137
8073 CEFBS_HasSIMD128, // LE_S_I8x16 = 1138
8074 CEFBS_HasSIMD128, // LE_S_I8x16_S = 1139
8075 CEFBS_HasSIMD128, // LE_U_I16x8 = 1140
8076 CEFBS_HasSIMD128, // LE_U_I16x8_S = 1141
8077 CEFBS_None, // LE_U_I32 = 1142
8078 CEFBS_None, // LE_U_I32_S = 1143
8079 CEFBS_HasSIMD128, // LE_U_I32x4 = 1144
8080 CEFBS_HasSIMD128, // LE_U_I32x4_S = 1145
8081 CEFBS_None, // LE_U_I64 = 1146
8082 CEFBS_None, // LE_U_I64_S = 1147
8083 CEFBS_HasSIMD128, // LE_U_I8x16 = 1148
8084 CEFBS_HasSIMD128, // LE_U_I8x16_S = 1149
8085 CEFBS_HasSIMD128, // LOAD16_SPLAT_A32 = 1150
8086 CEFBS_HasSIMD128, // LOAD16_SPLAT_A32_S = 1151
8087 CEFBS_HasSIMD128, // LOAD16_SPLAT_A64 = 1152
8088 CEFBS_HasSIMD128, // LOAD16_SPLAT_A64_S = 1153
8089 CEFBS_None, // LOAD16_S_I32_A32 = 1154
8090 CEFBS_None, // LOAD16_S_I32_A32_S = 1155
8091 CEFBS_None, // LOAD16_S_I32_A64 = 1156
8092 CEFBS_None, // LOAD16_S_I32_A64_S = 1157
8093 CEFBS_None, // LOAD16_S_I64_A32 = 1158
8094 CEFBS_None, // LOAD16_S_I64_A32_S = 1159
8095 CEFBS_None, // LOAD16_S_I64_A64 = 1160
8096 CEFBS_None, // LOAD16_S_I64_A64_S = 1161
8097 CEFBS_None, // LOAD16_U_I32_A32 = 1162
8098 CEFBS_None, // LOAD16_U_I32_A32_S = 1163
8099 CEFBS_None, // LOAD16_U_I32_A64 = 1164
8100 CEFBS_None, // LOAD16_U_I32_A64_S = 1165
8101 CEFBS_None, // LOAD16_U_I64_A32 = 1166
8102 CEFBS_None, // LOAD16_U_I64_A32_S = 1167
8103 CEFBS_None, // LOAD16_U_I64_A64 = 1168
8104 CEFBS_None, // LOAD16_U_I64_A64_S = 1169
8105 CEFBS_HasSIMD128, // LOAD32_SPLAT_A32 = 1170
8106 CEFBS_HasSIMD128, // LOAD32_SPLAT_A32_S = 1171
8107 CEFBS_HasSIMD128, // LOAD32_SPLAT_A64 = 1172
8108 CEFBS_HasSIMD128, // LOAD32_SPLAT_A64_S = 1173
8109 CEFBS_None, // LOAD32_S_I64_A32 = 1174
8110 CEFBS_None, // LOAD32_S_I64_A32_S = 1175
8111 CEFBS_None, // LOAD32_S_I64_A64 = 1176
8112 CEFBS_None, // LOAD32_S_I64_A64_S = 1177
8113 CEFBS_None, // LOAD32_U_I64_A32 = 1178
8114 CEFBS_None, // LOAD32_U_I64_A32_S = 1179
8115 CEFBS_None, // LOAD32_U_I64_A64 = 1180
8116 CEFBS_None, // LOAD32_U_I64_A64_S = 1181
8117 CEFBS_HasSIMD128, // LOAD64_SPLAT_A32 = 1182
8118 CEFBS_HasSIMD128, // LOAD64_SPLAT_A32_S = 1183
8119 CEFBS_HasSIMD128, // LOAD64_SPLAT_A64 = 1184
8120 CEFBS_HasSIMD128, // LOAD64_SPLAT_A64_S = 1185
8121 CEFBS_HasSIMD128, // LOAD8_SPLAT_A32 = 1186
8122 CEFBS_HasSIMD128, // LOAD8_SPLAT_A32_S = 1187
8123 CEFBS_HasSIMD128, // LOAD8_SPLAT_A64 = 1188
8124 CEFBS_HasSIMD128, // LOAD8_SPLAT_A64_S = 1189
8125 CEFBS_None, // LOAD8_S_I32_A32 = 1190
8126 CEFBS_None, // LOAD8_S_I32_A32_S = 1191
8127 CEFBS_None, // LOAD8_S_I32_A64 = 1192
8128 CEFBS_None, // LOAD8_S_I32_A64_S = 1193
8129 CEFBS_None, // LOAD8_S_I64_A32 = 1194
8130 CEFBS_None, // LOAD8_S_I64_A32_S = 1195
8131 CEFBS_None, // LOAD8_S_I64_A64 = 1196
8132 CEFBS_None, // LOAD8_S_I64_A64_S = 1197
8133 CEFBS_None, // LOAD8_U_I32_A32 = 1198
8134 CEFBS_None, // LOAD8_U_I32_A32_S = 1199
8135 CEFBS_None, // LOAD8_U_I32_A64 = 1200
8136 CEFBS_None, // LOAD8_U_I32_A64_S = 1201
8137 CEFBS_None, // LOAD8_U_I64_A32 = 1202
8138 CEFBS_None, // LOAD8_U_I64_A32_S = 1203
8139 CEFBS_None, // LOAD8_U_I64_A64 = 1204
8140 CEFBS_None, // LOAD8_U_I64_A64_S = 1205
8141 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32 = 1206
8142 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32_S = 1207
8143 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64 = 1208
8144 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64_S = 1209
8145 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32 = 1210
8146 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32_S = 1211
8147 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64 = 1212
8148 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64_S = 1213
8149 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32 = 1214
8150 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32_S = 1215
8151 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64 = 1216
8152 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64_S = 1217
8153 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32 = 1218
8154 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32_S = 1219
8155 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64 = 1220
8156 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64_S = 1221
8157 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32 = 1222
8158 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32_S = 1223
8159 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64 = 1224
8160 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64_S = 1225
8161 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32 = 1226
8162 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32_S = 1227
8163 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64 = 1228
8164 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64_S = 1229
8165 CEFBS_HasFP16, // LOAD_F16_F32_A32 = 1230
8166 CEFBS_HasFP16, // LOAD_F16_F32_A32_S = 1231
8167 CEFBS_HasFP16, // LOAD_F16_F32_A64 = 1232
8168 CEFBS_HasFP16, // LOAD_F16_F32_A64_S = 1233
8169 CEFBS_None, // LOAD_F32_A32 = 1234
8170 CEFBS_None, // LOAD_F32_A32_S = 1235
8171 CEFBS_None, // LOAD_F32_A64 = 1236
8172 CEFBS_None, // LOAD_F32_A64_S = 1237
8173 CEFBS_None, // LOAD_F64_A32 = 1238
8174 CEFBS_None, // LOAD_F64_A32_S = 1239
8175 CEFBS_None, // LOAD_F64_A64 = 1240
8176 CEFBS_None, // LOAD_F64_A64_S = 1241
8177 CEFBS_None, // LOAD_I32_A32 = 1242
8178 CEFBS_None, // LOAD_I32_A32_S = 1243
8179 CEFBS_None, // LOAD_I32_A64 = 1244
8180 CEFBS_None, // LOAD_I32_A64_S = 1245
8181 CEFBS_None, // LOAD_I64_A32 = 1246
8182 CEFBS_None, // LOAD_I64_A32_S = 1247
8183 CEFBS_None, // LOAD_I64_A64 = 1248
8184 CEFBS_None, // LOAD_I64_A64_S = 1249
8185 CEFBS_HasSIMD128, // LOAD_LANE_16_A32 = 1250
8186 CEFBS_HasSIMD128, // LOAD_LANE_16_A32_S = 1251
8187 CEFBS_HasSIMD128, // LOAD_LANE_16_A64 = 1252
8188 CEFBS_HasSIMD128, // LOAD_LANE_16_A64_S = 1253
8189 CEFBS_HasSIMD128, // LOAD_LANE_32_A32 = 1254
8190 CEFBS_HasSIMD128, // LOAD_LANE_32_A32_S = 1255
8191 CEFBS_HasSIMD128, // LOAD_LANE_32_A64 = 1256
8192 CEFBS_HasSIMD128, // LOAD_LANE_32_A64_S = 1257
8193 CEFBS_HasSIMD128, // LOAD_LANE_64_A32 = 1258
8194 CEFBS_HasSIMD128, // LOAD_LANE_64_A32_S = 1259
8195 CEFBS_HasSIMD128, // LOAD_LANE_64_A64 = 1260
8196 CEFBS_HasSIMD128, // LOAD_LANE_64_A64_S = 1261
8197 CEFBS_HasSIMD128, // LOAD_LANE_8_A32 = 1262
8198 CEFBS_HasSIMD128, // LOAD_LANE_8_A32_S = 1263
8199 CEFBS_HasSIMD128, // LOAD_LANE_8_A64 = 1264
8200 CEFBS_HasSIMD128, // LOAD_LANE_8_A64_S = 1265
8201 CEFBS_HasSIMD128, // LOAD_V128_A32 = 1266
8202 CEFBS_HasSIMD128, // LOAD_V128_A32_S = 1267
8203 CEFBS_HasSIMD128, // LOAD_V128_A64 = 1268
8204 CEFBS_HasSIMD128, // LOAD_V128_A64_S = 1269
8205 CEFBS_HasSIMD128, // LOAD_ZERO_32_A32 = 1270
8206 CEFBS_HasSIMD128, // LOAD_ZERO_32_A32_S = 1271
8207 CEFBS_HasSIMD128, // LOAD_ZERO_32_A64 = 1272
8208 CEFBS_HasSIMD128, // LOAD_ZERO_32_A64_S = 1273
8209 CEFBS_HasSIMD128, // LOAD_ZERO_64_A32 = 1274
8210 CEFBS_HasSIMD128, // LOAD_ZERO_64_A32_S = 1275
8211 CEFBS_HasSIMD128, // LOAD_ZERO_64_A64 = 1276
8212 CEFBS_HasSIMD128, // LOAD_ZERO_64_A64_S = 1277
8213 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF = 1278
8214 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF_S = 1279
8215 CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF = 1280
8216 CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF_S = 1281
8217 CEFBS_None, // LOCAL_GET_F32 = 1282
8218 CEFBS_None, // LOCAL_GET_F32_S = 1283
8219 CEFBS_None, // LOCAL_GET_F64 = 1284
8220 CEFBS_None, // LOCAL_GET_F64_S = 1285
8221 CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF = 1286
8222 CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF_S = 1287
8223 CEFBS_None, // LOCAL_GET_I32 = 1288
8224 CEFBS_None, // LOCAL_GET_I32_S = 1289
8225 CEFBS_None, // LOCAL_GET_I64 = 1290
8226 CEFBS_None, // LOCAL_GET_I64_S = 1291
8227 CEFBS_HasSIMD128, // LOCAL_GET_V128 = 1292
8228 CEFBS_HasSIMD128, // LOCAL_GET_V128_S = 1293
8229 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF = 1294
8230 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF_S = 1295
8231 CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF = 1296
8232 CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF_S = 1297
8233 CEFBS_None, // LOCAL_SET_F32 = 1298
8234 CEFBS_None, // LOCAL_SET_F32_S = 1299
8235 CEFBS_None, // LOCAL_SET_F64 = 1300
8236 CEFBS_None, // LOCAL_SET_F64_S = 1301
8237 CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF = 1302
8238 CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF_S = 1303
8239 CEFBS_None, // LOCAL_SET_I32 = 1304
8240 CEFBS_None, // LOCAL_SET_I32_S = 1305
8241 CEFBS_None, // LOCAL_SET_I64 = 1306
8242 CEFBS_None, // LOCAL_SET_I64_S = 1307
8243 CEFBS_HasSIMD128, // LOCAL_SET_V128 = 1308
8244 CEFBS_HasSIMD128, // LOCAL_SET_V128_S = 1309
8245 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF = 1310
8246 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF_S = 1311
8247 CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF = 1312
8248 CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF_S = 1313
8249 CEFBS_None, // LOCAL_TEE_F32 = 1314
8250 CEFBS_None, // LOCAL_TEE_F32_S = 1315
8251 CEFBS_None, // LOCAL_TEE_F64 = 1316
8252 CEFBS_None, // LOCAL_TEE_F64_S = 1317
8253 CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF = 1318
8254 CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF_S = 1319
8255 CEFBS_None, // LOCAL_TEE_I32 = 1320
8256 CEFBS_None, // LOCAL_TEE_I32_S = 1321
8257 CEFBS_None, // LOCAL_TEE_I64 = 1322
8258 CEFBS_None, // LOCAL_TEE_I64_S = 1323
8259 CEFBS_HasSIMD128, // LOCAL_TEE_V128 = 1324
8260 CEFBS_HasSIMD128, // LOCAL_TEE_V128_S = 1325
8261 CEFBS_None, // LOOP = 1326
8262 CEFBS_None, // LOOP_S = 1327
8263 CEFBS_HasSIMD128_HasFP16, // LT_F16x8 = 1328
8264 CEFBS_HasSIMD128_HasFP16, // LT_F16x8_S = 1329
8265 CEFBS_None, // LT_F32 = 1330
8266 CEFBS_None, // LT_F32_S = 1331
8267 CEFBS_HasSIMD128, // LT_F32x4 = 1332
8268 CEFBS_HasSIMD128, // LT_F32x4_S = 1333
8269 CEFBS_None, // LT_F64 = 1334
8270 CEFBS_None, // LT_F64_S = 1335
8271 CEFBS_HasSIMD128, // LT_F64x2 = 1336
8272 CEFBS_HasSIMD128, // LT_F64x2_S = 1337
8273 CEFBS_HasSIMD128, // LT_S_I16x8 = 1338
8274 CEFBS_HasSIMD128, // LT_S_I16x8_S = 1339
8275 CEFBS_None, // LT_S_I32 = 1340
8276 CEFBS_None, // LT_S_I32_S = 1341
8277 CEFBS_HasSIMD128, // LT_S_I32x4 = 1342
8278 CEFBS_HasSIMD128, // LT_S_I32x4_S = 1343
8279 CEFBS_None, // LT_S_I64 = 1344
8280 CEFBS_None, // LT_S_I64_S = 1345
8281 CEFBS_HasSIMD128, // LT_S_I64x2 = 1346
8282 CEFBS_HasSIMD128, // LT_S_I64x2_S = 1347
8283 CEFBS_HasSIMD128, // LT_S_I8x16 = 1348
8284 CEFBS_HasSIMD128, // LT_S_I8x16_S = 1349
8285 CEFBS_HasSIMD128, // LT_U_I16x8 = 1350
8286 CEFBS_HasSIMD128, // LT_U_I16x8_S = 1351
8287 CEFBS_None, // LT_U_I32 = 1352
8288 CEFBS_None, // LT_U_I32_S = 1353
8289 CEFBS_HasSIMD128, // LT_U_I32x4 = 1354
8290 CEFBS_HasSIMD128, // LT_U_I32x4_S = 1355
8291 CEFBS_None, // LT_U_I64 = 1356
8292 CEFBS_None, // LT_U_I64_S = 1357
8293 CEFBS_HasSIMD128, // LT_U_I8x16 = 1358
8294 CEFBS_HasSIMD128, // LT_U_I8x16_S = 1359
8295 CEFBS_HasSIMD128_HasFP16, // MADD_F16x8 = 1360
8296 CEFBS_HasSIMD128_HasFP16, // MADD_F16x8_S = 1361
8297 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4 = 1362
8298 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4_S = 1363
8299 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2 = 1364
8300 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2_S = 1365
8301 CEFBS_HasSIMD128_HasFP16, // MAX_F16x8 = 1366
8302 CEFBS_HasSIMD128_HasFP16, // MAX_F16x8_S = 1367
8303 CEFBS_None, // MAX_F32 = 1368
8304 CEFBS_None, // MAX_F32_S = 1369
8305 CEFBS_HasSIMD128, // MAX_F32x4 = 1370
8306 CEFBS_HasSIMD128, // MAX_F32x4_S = 1371
8307 CEFBS_None, // MAX_F64 = 1372
8308 CEFBS_None, // MAX_F64_S = 1373
8309 CEFBS_HasSIMD128, // MAX_F64x2 = 1374
8310 CEFBS_HasSIMD128, // MAX_F64x2_S = 1375
8311 CEFBS_HasSIMD128, // MAX_S_I16x8 = 1376
8312 CEFBS_HasSIMD128, // MAX_S_I16x8_S = 1377
8313 CEFBS_HasSIMD128, // MAX_S_I32x4 = 1378
8314 CEFBS_HasSIMD128, // MAX_S_I32x4_S = 1379
8315 CEFBS_HasSIMD128, // MAX_S_I8x16 = 1380
8316 CEFBS_HasSIMD128, // MAX_S_I8x16_S = 1381
8317 CEFBS_HasSIMD128, // MAX_U_I16x8 = 1382
8318 CEFBS_HasSIMD128, // MAX_U_I16x8_S = 1383
8319 CEFBS_HasSIMD128, // MAX_U_I32x4 = 1384
8320 CEFBS_HasSIMD128, // MAX_U_I32x4_S = 1385
8321 CEFBS_HasSIMD128, // MAX_U_I8x16 = 1386
8322 CEFBS_HasSIMD128, // MAX_U_I8x16_S = 1387
8323 CEFBS_HasBulkMemoryOpt, // MEMCPY_A32 = 1388
8324 CEFBS_HasBulkMemoryOpt, // MEMCPY_A32_S = 1389
8325 CEFBS_HasBulkMemoryOpt, // MEMCPY_A64 = 1390
8326 CEFBS_HasBulkMemoryOpt, // MEMCPY_A64_S = 1391
8327 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32 = 1392
8328 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32_S = 1393
8329 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64 = 1394
8330 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64_S = 1395
8331 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32 = 1396
8332 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32_S = 1397
8333 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64 = 1398
8334 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64_S = 1399
8335 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32 = 1400
8336 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32_S = 1401
8337 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64 = 1402
8338 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64_S = 1403
8339 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A32 = 1404
8340 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A32_S = 1405
8341 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A64 = 1406
8342 CEFBS_HasBulkMemoryOpt, // MEMORY_COPY_A64_S = 1407
8343 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A32 = 1408
8344 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A32_S = 1409
8345 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A64 = 1410
8346 CEFBS_HasBulkMemoryOpt, // MEMORY_FILL_A64_S = 1411
8347 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A32 = 1412
8348 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A32_S = 1413
8349 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A64 = 1414
8350 CEFBS_HasBulkMemoryOpt, // MEMORY_INIT_A64_S = 1415
8351 CEFBS_HasBulkMemoryOpt, // MEMSET_A32 = 1416
8352 CEFBS_HasBulkMemoryOpt, // MEMSET_A32_S = 1417
8353 CEFBS_HasBulkMemoryOpt, // MEMSET_A64 = 1418
8354 CEFBS_HasBulkMemoryOpt, // MEMSET_A64_S = 1419
8355 CEFBS_HasSIMD128_HasFP16, // MIN_F16x8 = 1420
8356 CEFBS_HasSIMD128_HasFP16, // MIN_F16x8_S = 1421
8357 CEFBS_None, // MIN_F32 = 1422
8358 CEFBS_None, // MIN_F32_S = 1423
8359 CEFBS_HasSIMD128, // MIN_F32x4 = 1424
8360 CEFBS_HasSIMD128, // MIN_F32x4_S = 1425
8361 CEFBS_None, // MIN_F64 = 1426
8362 CEFBS_None, // MIN_F64_S = 1427
8363 CEFBS_HasSIMD128, // MIN_F64x2 = 1428
8364 CEFBS_HasSIMD128, // MIN_F64x2_S = 1429
8365 CEFBS_HasSIMD128, // MIN_S_I16x8 = 1430
8366 CEFBS_HasSIMD128, // MIN_S_I16x8_S = 1431
8367 CEFBS_HasSIMD128, // MIN_S_I32x4 = 1432
8368 CEFBS_HasSIMD128, // MIN_S_I32x4_S = 1433
8369 CEFBS_HasSIMD128, // MIN_S_I8x16 = 1434
8370 CEFBS_HasSIMD128, // MIN_S_I8x16_S = 1435
8371 CEFBS_HasSIMD128, // MIN_U_I16x8 = 1436
8372 CEFBS_HasSIMD128, // MIN_U_I16x8_S = 1437
8373 CEFBS_HasSIMD128, // MIN_U_I32x4 = 1438
8374 CEFBS_HasSIMD128, // MIN_U_I32x4_S = 1439
8375 CEFBS_HasSIMD128, // MIN_U_I8x16 = 1440
8376 CEFBS_HasSIMD128, // MIN_U_I8x16_S = 1441
8377 CEFBS_HasSIMD128_HasFP16, // MUL_F16x8 = 1442
8378 CEFBS_HasSIMD128_HasFP16, // MUL_F16x8_S = 1443
8379 CEFBS_None, // MUL_F32 = 1444
8380 CEFBS_None, // MUL_F32_S = 1445
8381 CEFBS_HasSIMD128, // MUL_F32x4 = 1446
8382 CEFBS_HasSIMD128, // MUL_F32x4_S = 1447
8383 CEFBS_None, // MUL_F64 = 1448
8384 CEFBS_None, // MUL_F64_S = 1449
8385 CEFBS_HasSIMD128, // MUL_F64x2 = 1450
8386 CEFBS_HasSIMD128, // MUL_F64x2_S = 1451
8387 CEFBS_HasSIMD128, // MUL_I16x8 = 1452
8388 CEFBS_HasSIMD128, // MUL_I16x8_S = 1453
8389 CEFBS_None, // MUL_I32 = 1454
8390 CEFBS_None, // MUL_I32_S = 1455
8391 CEFBS_HasSIMD128, // MUL_I32x4 = 1456
8392 CEFBS_HasSIMD128, // MUL_I32x4_S = 1457
8393 CEFBS_None, // MUL_I64 = 1458
8394 CEFBS_None, // MUL_I64_S = 1459
8395 CEFBS_HasSIMD128, // MUL_I64x2 = 1460
8396 CEFBS_HasSIMD128, // MUL_I64x2_S = 1461
8397 CEFBS_HasSIMD128, // NARROW_S_I16x8 = 1462
8398 CEFBS_HasSIMD128, // NARROW_S_I16x8_S = 1463
8399 CEFBS_HasSIMD128, // NARROW_S_I8x16 = 1464
8400 CEFBS_HasSIMD128, // NARROW_S_I8x16_S = 1465
8401 CEFBS_HasSIMD128, // NARROW_U_I16x8 = 1466
8402 CEFBS_HasSIMD128, // NARROW_U_I16x8_S = 1467
8403 CEFBS_HasSIMD128, // NARROW_U_I8x16 = 1468
8404 CEFBS_HasSIMD128, // NARROW_U_I8x16_S = 1469
8405 CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8 = 1470
8406 CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8_S = 1471
8407 CEFBS_None, // NEAREST_F32 = 1472
8408 CEFBS_None, // NEAREST_F32_S = 1473
8409 CEFBS_HasSIMD128, // NEAREST_F32x4 = 1474
8410 CEFBS_HasSIMD128, // NEAREST_F32x4_S = 1475
8411 CEFBS_None, // NEAREST_F64 = 1476
8412 CEFBS_None, // NEAREST_F64_S = 1477
8413 CEFBS_HasSIMD128, // NEAREST_F64x2 = 1478
8414 CEFBS_HasSIMD128, // NEAREST_F64x2_S = 1479
8415 CEFBS_HasSIMD128_HasFP16, // NEG_F16x8 = 1480
8416 CEFBS_HasSIMD128_HasFP16, // NEG_F16x8_S = 1481
8417 CEFBS_None, // NEG_F32 = 1482
8418 CEFBS_None, // NEG_F32_S = 1483
8419 CEFBS_HasSIMD128, // NEG_F32x4 = 1484
8420 CEFBS_HasSIMD128, // NEG_F32x4_S = 1485
8421 CEFBS_None, // NEG_F64 = 1486
8422 CEFBS_None, // NEG_F64_S = 1487
8423 CEFBS_HasSIMD128, // NEG_F64x2 = 1488
8424 CEFBS_HasSIMD128, // NEG_F64x2_S = 1489
8425 CEFBS_HasSIMD128, // NEG_I16x8 = 1490
8426 CEFBS_HasSIMD128, // NEG_I16x8_S = 1491
8427 CEFBS_HasSIMD128, // NEG_I32x4 = 1492
8428 CEFBS_HasSIMD128, // NEG_I32x4_S = 1493
8429 CEFBS_HasSIMD128, // NEG_I64x2 = 1494
8430 CEFBS_HasSIMD128, // NEG_I64x2_S = 1495
8431 CEFBS_HasSIMD128, // NEG_I8x16 = 1496
8432 CEFBS_HasSIMD128, // NEG_I8x16_S = 1497
8433 CEFBS_HasSIMD128_HasFP16, // NE_F16x8 = 1498
8434 CEFBS_HasSIMD128_HasFP16, // NE_F16x8_S = 1499
8435 CEFBS_None, // NE_F32 = 1500
8436 CEFBS_None, // NE_F32_S = 1501
8437 CEFBS_HasSIMD128, // NE_F32x4 = 1502
8438 CEFBS_HasSIMD128, // NE_F32x4_S = 1503
8439 CEFBS_None, // NE_F64 = 1504
8440 CEFBS_None, // NE_F64_S = 1505
8441 CEFBS_HasSIMD128, // NE_F64x2 = 1506
8442 CEFBS_HasSIMD128, // NE_F64x2_S = 1507
8443 CEFBS_HasSIMD128, // NE_I16x8 = 1508
8444 CEFBS_HasSIMD128, // NE_I16x8_S = 1509
8445 CEFBS_None, // NE_I32 = 1510
8446 CEFBS_None, // NE_I32_S = 1511
8447 CEFBS_HasSIMD128, // NE_I32x4 = 1512
8448 CEFBS_HasSIMD128, // NE_I32x4_S = 1513
8449 CEFBS_None, // NE_I64 = 1514
8450 CEFBS_None, // NE_I64_S = 1515
8451 CEFBS_HasSIMD128, // NE_I64x2 = 1516
8452 CEFBS_HasSIMD128, // NE_I64x2_S = 1517
8453 CEFBS_HasSIMD128, // NE_I8x16 = 1518
8454 CEFBS_HasSIMD128, // NE_I8x16_S = 1519
8455 CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8 = 1520
8456 CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8_S = 1521
8457 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4 = 1522
8458 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4_S = 1523
8459 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2 = 1524
8460 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2_S = 1525
8461 CEFBS_None, // NOP = 1526
8462 CEFBS_None, // NOP_S = 1527
8463 CEFBS_HasSIMD128, // NOT = 1528
8464 CEFBS_HasSIMD128, // NOT_S = 1529
8465 CEFBS_HasSIMD128, // OR = 1530
8466 CEFBS_None, // OR_I32 = 1531
8467 CEFBS_None, // OR_I32_S = 1532
8468 CEFBS_None, // OR_I64 = 1533
8469 CEFBS_None, // OR_I64_S = 1534
8470 CEFBS_HasSIMD128, // OR_S = 1535
8471 CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8 = 1536
8472 CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8_S = 1537
8473 CEFBS_HasSIMD128, // PMAX_F32x4 = 1538
8474 CEFBS_HasSIMD128, // PMAX_F32x4_S = 1539
8475 CEFBS_HasSIMD128, // PMAX_F64x2 = 1540
8476 CEFBS_HasSIMD128, // PMAX_F64x2_S = 1541
8477 CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8 = 1542
8478 CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8_S = 1543
8479 CEFBS_HasSIMD128, // PMIN_F32x4 = 1544
8480 CEFBS_HasSIMD128, // PMIN_F32x4_S = 1545
8481 CEFBS_HasSIMD128, // PMIN_F64x2 = 1546
8482 CEFBS_HasSIMD128, // PMIN_F64x2_S = 1547
8483 CEFBS_None, // POPCNT_I32 = 1548
8484 CEFBS_None, // POPCNT_I32_S = 1549
8485 CEFBS_None, // POPCNT_I64 = 1550
8486 CEFBS_None, // POPCNT_I64_S = 1551
8487 CEFBS_HasSIMD128, // POPCNT_I8x16 = 1552
8488 CEFBS_HasSIMD128, // POPCNT_I8x16_S = 1553
8489 CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8 = 1554
8490 CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8_S = 1555
8491 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF = 1556
8492 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF_S = 1557
8493 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF = 1558
8494 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF_S = 1559
8495 CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF = 1560
8496 CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF_S = 1561
8497 CEFBS_HasReferenceTypes, // REF_NULL_EXNREF = 1562
8498 CEFBS_HasReferenceTypes, // REF_NULL_EXNREF_S = 1563
8499 CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF = 1564
8500 CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF_S = 1565
8501 CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF = 1566
8502 CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF_S = 1567
8503 CEFBS_HasRelaxedSIMD, // RELAXED_DOT = 1568
8504 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD = 1569
8505 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD_S = 1570
8506 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT = 1571
8507 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT_S = 1572
8508 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_S = 1573
8509 CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8 = 1574
8510 CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8_S = 1575
8511 CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE = 1576
8512 CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE_S = 1577
8513 CEFBS_None, // REM_S_I32 = 1578
8514 CEFBS_None, // REM_S_I32_S = 1579
8515 CEFBS_None, // REM_S_I64 = 1580
8516 CEFBS_None, // REM_S_I64_S = 1581
8517 CEFBS_None, // REM_U_I32 = 1582
8518 CEFBS_None, // REM_U_I32_S = 1583
8519 CEFBS_None, // REM_U_I64 = 1584
8520 CEFBS_None, // REM_U_I64_S = 1585
8521 CEFBS_HasFP16, // REPLACE_LANE_F16x8 = 1586
8522 CEFBS_HasFP16, // REPLACE_LANE_F16x8_S = 1587
8523 CEFBS_HasSIMD128, // REPLACE_LANE_F32x4 = 1588
8524 CEFBS_HasSIMD128, // REPLACE_LANE_F32x4_S = 1589
8525 CEFBS_HasSIMD128, // REPLACE_LANE_F64x2 = 1590
8526 CEFBS_HasSIMD128, // REPLACE_LANE_F64x2_S = 1591
8527 CEFBS_HasSIMD128, // REPLACE_LANE_I16x8 = 1592
8528 CEFBS_HasSIMD128, // REPLACE_LANE_I16x8_S = 1593
8529 CEFBS_HasSIMD128, // REPLACE_LANE_I32x4 = 1594
8530 CEFBS_HasSIMD128, // REPLACE_LANE_I32x4_S = 1595
8531 CEFBS_HasSIMD128, // REPLACE_LANE_I64x2 = 1596
8532 CEFBS_HasSIMD128, // REPLACE_LANE_I64x2_S = 1597
8533 CEFBS_HasSIMD128, // REPLACE_LANE_I8x16 = 1598
8534 CEFBS_HasSIMD128, // REPLACE_LANE_I8x16_S = 1599
8535 CEFBS_HasExceptionHandling, // RETHROW = 1600
8536 CEFBS_HasExceptionHandling, // RETHROW_S = 1601
8537 CEFBS_None, // RETURN = 1602
8538 CEFBS_None, // RETURN_S = 1603
8539 CEFBS_HasTailCall, // RET_CALL = 1604
8540 CEFBS_HasTailCall, // RET_CALL_INDIRECT = 1605
8541 CEFBS_HasTailCall, // RET_CALL_INDIRECT_S = 1606
8542 CEFBS_HasTailCall, // RET_CALL_S = 1607
8543 CEFBS_None, // ROTL_I32 = 1608
8544 CEFBS_None, // ROTL_I32_S = 1609
8545 CEFBS_None, // ROTL_I64 = 1610
8546 CEFBS_None, // ROTL_I64_S = 1611
8547 CEFBS_None, // ROTR_I32 = 1612
8548 CEFBS_None, // ROTR_I32_S = 1613
8549 CEFBS_None, // ROTR_I64 = 1614
8550 CEFBS_None, // ROTR_I64_S = 1615
8551 CEFBS_HasReferenceTypes, // SELECT_EXNREF = 1616
8552 CEFBS_HasReferenceTypes, // SELECT_EXNREF_S = 1617
8553 CEFBS_HasReferenceTypes, // SELECT_EXTERNREF = 1618
8554 CEFBS_HasReferenceTypes, // SELECT_EXTERNREF_S = 1619
8555 CEFBS_None, // SELECT_F32 = 1620
8556 CEFBS_None, // SELECT_F32_S = 1621
8557 CEFBS_None, // SELECT_F64 = 1622
8558 CEFBS_None, // SELECT_F64_S = 1623
8559 CEFBS_HasReferenceTypes, // SELECT_FUNCREF = 1624
8560 CEFBS_HasReferenceTypes, // SELECT_FUNCREF_S = 1625
8561 CEFBS_None, // SELECT_I32 = 1626
8562 CEFBS_None, // SELECT_I32_S = 1627
8563 CEFBS_None, // SELECT_I64 = 1628
8564 CEFBS_None, // SELECT_I64_S = 1629
8565 CEFBS_None, // SELECT_V128 = 1630
8566 CEFBS_None, // SELECT_V128_S = 1631
8567 CEFBS_HasSIMD128, // SHL_I16x8 = 1632
8568 CEFBS_HasSIMD128, // SHL_I16x8_S = 1633
8569 CEFBS_None, // SHL_I32 = 1634
8570 CEFBS_None, // SHL_I32_S = 1635
8571 CEFBS_HasSIMD128, // SHL_I32x4 = 1636
8572 CEFBS_HasSIMD128, // SHL_I32x4_S = 1637
8573 CEFBS_None, // SHL_I64 = 1638
8574 CEFBS_None, // SHL_I64_S = 1639
8575 CEFBS_HasSIMD128, // SHL_I64x2 = 1640
8576 CEFBS_HasSIMD128, // SHL_I64x2_S = 1641
8577 CEFBS_HasSIMD128, // SHL_I8x16 = 1642
8578 CEFBS_HasSIMD128, // SHL_I8x16_S = 1643
8579 CEFBS_HasSIMD128, // SHR_S_I16x8 = 1644
8580 CEFBS_HasSIMD128, // SHR_S_I16x8_S = 1645
8581 CEFBS_None, // SHR_S_I32 = 1646
8582 CEFBS_None, // SHR_S_I32_S = 1647
8583 CEFBS_HasSIMD128, // SHR_S_I32x4 = 1648
8584 CEFBS_HasSIMD128, // SHR_S_I32x4_S = 1649
8585 CEFBS_None, // SHR_S_I64 = 1650
8586 CEFBS_None, // SHR_S_I64_S = 1651
8587 CEFBS_HasSIMD128, // SHR_S_I64x2 = 1652
8588 CEFBS_HasSIMD128, // SHR_S_I64x2_S = 1653
8589 CEFBS_HasSIMD128, // SHR_S_I8x16 = 1654
8590 CEFBS_HasSIMD128, // SHR_S_I8x16_S = 1655
8591 CEFBS_HasSIMD128, // SHR_U_I16x8 = 1656
8592 CEFBS_HasSIMD128, // SHR_U_I16x8_S = 1657
8593 CEFBS_None, // SHR_U_I32 = 1658
8594 CEFBS_None, // SHR_U_I32_S = 1659
8595 CEFBS_HasSIMD128, // SHR_U_I32x4 = 1660
8596 CEFBS_HasSIMD128, // SHR_U_I32x4_S = 1661
8597 CEFBS_None, // SHR_U_I64 = 1662
8598 CEFBS_None, // SHR_U_I64_S = 1663
8599 CEFBS_HasSIMD128, // SHR_U_I64x2 = 1664
8600 CEFBS_HasSIMD128, // SHR_U_I64x2_S = 1665
8601 CEFBS_HasSIMD128, // SHR_U_I8x16 = 1666
8602 CEFBS_HasSIMD128, // SHR_U_I8x16_S = 1667
8603 CEFBS_HasSIMD128, // SHUFFLE = 1668
8604 CEFBS_HasSIMD128, // SHUFFLE_S = 1669
8605 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4 = 1670
8606 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4_S = 1671
8607 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2 = 1672
8608 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2_S = 1673
8609 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4 = 1674
8610 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4_S = 1675
8611 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2 = 1676
8612 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2_S = 1677
8613 CEFBS_HasFP16, // SPLAT_F16x8 = 1678
8614 CEFBS_HasFP16, // SPLAT_F16x8_S = 1679
8615 CEFBS_HasSIMD128, // SPLAT_F32x4 = 1680
8616 CEFBS_HasSIMD128, // SPLAT_F32x4_S = 1681
8617 CEFBS_HasSIMD128, // SPLAT_F64x2 = 1682
8618 CEFBS_HasSIMD128, // SPLAT_F64x2_S = 1683
8619 CEFBS_HasSIMD128, // SPLAT_I16x8 = 1684
8620 CEFBS_HasSIMD128, // SPLAT_I16x8_S = 1685
8621 CEFBS_HasSIMD128, // SPLAT_I32x4 = 1686
8622 CEFBS_HasSIMD128, // SPLAT_I32x4_S = 1687
8623 CEFBS_HasSIMD128, // SPLAT_I64x2 = 1688
8624 CEFBS_HasSIMD128, // SPLAT_I64x2_S = 1689
8625 CEFBS_HasSIMD128, // SPLAT_I8x16 = 1690
8626 CEFBS_HasSIMD128, // SPLAT_I8x16_S = 1691
8627 CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8 = 1692
8628 CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8_S = 1693
8629 CEFBS_None, // SQRT_F32 = 1694
8630 CEFBS_None, // SQRT_F32_S = 1695
8631 CEFBS_HasSIMD128, // SQRT_F32x4 = 1696
8632 CEFBS_HasSIMD128, // SQRT_F32x4_S = 1697
8633 CEFBS_None, // SQRT_F64 = 1698
8634 CEFBS_None, // SQRT_F64_S = 1699
8635 CEFBS_HasSIMD128, // SQRT_F64x2 = 1700
8636 CEFBS_HasSIMD128, // SQRT_F64x2_S = 1701
8637 CEFBS_None, // STORE16_I32_A32 = 1702
8638 CEFBS_None, // STORE16_I32_A32_S = 1703
8639 CEFBS_None, // STORE16_I32_A64 = 1704
8640 CEFBS_None, // STORE16_I32_A64_S = 1705
8641 CEFBS_None, // STORE16_I64_A32 = 1706
8642 CEFBS_None, // STORE16_I64_A32_S = 1707
8643 CEFBS_None, // STORE16_I64_A64 = 1708
8644 CEFBS_None, // STORE16_I64_A64_S = 1709
8645 CEFBS_None, // STORE32_I64_A32 = 1710
8646 CEFBS_None, // STORE32_I64_A32_S = 1711
8647 CEFBS_None, // STORE32_I64_A64 = 1712
8648 CEFBS_None, // STORE32_I64_A64_S = 1713
8649 CEFBS_None, // STORE8_I32_A32 = 1714
8650 CEFBS_None, // STORE8_I32_A32_S = 1715
8651 CEFBS_None, // STORE8_I32_A64 = 1716
8652 CEFBS_None, // STORE8_I32_A64_S = 1717
8653 CEFBS_None, // STORE8_I64_A32 = 1718
8654 CEFBS_None, // STORE8_I64_A32_S = 1719
8655 CEFBS_None, // STORE8_I64_A64 = 1720
8656 CEFBS_None, // STORE8_I64_A64_S = 1721
8657 CEFBS_HasFP16, // STORE_F16_F32_A32 = 1722
8658 CEFBS_HasFP16, // STORE_F16_F32_A32_S = 1723
8659 CEFBS_HasFP16, // STORE_F16_F32_A64 = 1724
8660 CEFBS_HasFP16, // STORE_F16_F32_A64_S = 1725
8661 CEFBS_None, // STORE_F32_A32 = 1726
8662 CEFBS_None, // STORE_F32_A32_S = 1727
8663 CEFBS_None, // STORE_F32_A64 = 1728
8664 CEFBS_None, // STORE_F32_A64_S = 1729
8665 CEFBS_None, // STORE_F64_A32 = 1730
8666 CEFBS_None, // STORE_F64_A32_S = 1731
8667 CEFBS_None, // STORE_F64_A64 = 1732
8668 CEFBS_None, // STORE_F64_A64_S = 1733
8669 CEFBS_None, // STORE_I32_A32 = 1734
8670 CEFBS_None, // STORE_I32_A32_S = 1735
8671 CEFBS_None, // STORE_I32_A64 = 1736
8672 CEFBS_None, // STORE_I32_A64_S = 1737
8673 CEFBS_None, // STORE_I64_A32 = 1738
8674 CEFBS_None, // STORE_I64_A32_S = 1739
8675 CEFBS_None, // STORE_I64_A64 = 1740
8676 CEFBS_None, // STORE_I64_A64_S = 1741
8677 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32 = 1742
8678 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32_S = 1743
8679 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64 = 1744
8680 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64_S = 1745
8681 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32 = 1746
8682 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32_S = 1747
8683 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64 = 1748
8684 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64_S = 1749
8685 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32 = 1750
8686 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32_S = 1751
8687 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64 = 1752
8688 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64_S = 1753
8689 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32 = 1754
8690 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32_S = 1755
8691 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64 = 1756
8692 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64_S = 1757
8693 CEFBS_HasSIMD128, // STORE_V128_A32 = 1758
8694 CEFBS_HasSIMD128, // STORE_V128_A32_S = 1759
8695 CEFBS_HasSIMD128, // STORE_V128_A64 = 1760
8696 CEFBS_HasSIMD128, // STORE_V128_A64_S = 1761
8697 CEFBS_HasSIMD128_HasFP16, // SUB_F16x8 = 1762
8698 CEFBS_HasSIMD128_HasFP16, // SUB_F16x8_S = 1763
8699 CEFBS_None, // SUB_F32 = 1764
8700 CEFBS_None, // SUB_F32_S = 1765
8701 CEFBS_HasSIMD128, // SUB_F32x4 = 1766
8702 CEFBS_HasSIMD128, // SUB_F32x4_S = 1767
8703 CEFBS_None, // SUB_F64 = 1768
8704 CEFBS_None, // SUB_F64_S = 1769
8705 CEFBS_HasSIMD128, // SUB_F64x2 = 1770
8706 CEFBS_HasSIMD128, // SUB_F64x2_S = 1771
8707 CEFBS_HasSIMD128, // SUB_I16x8 = 1772
8708 CEFBS_HasSIMD128, // SUB_I16x8_S = 1773
8709 CEFBS_None, // SUB_I32 = 1774
8710 CEFBS_None, // SUB_I32_S = 1775
8711 CEFBS_HasSIMD128, // SUB_I32x4 = 1776
8712 CEFBS_HasSIMD128, // SUB_I32x4_S = 1777
8713 CEFBS_None, // SUB_I64 = 1778
8714 CEFBS_None, // SUB_I64_S = 1779
8715 CEFBS_HasSIMD128, // SUB_I64x2 = 1780
8716 CEFBS_HasSIMD128, // SUB_I64x2_S = 1781
8717 CEFBS_HasSIMD128, // SUB_I8x16 = 1782
8718 CEFBS_HasSIMD128, // SUB_I8x16_S = 1783
8719 CEFBS_HasSIMD128, // SUB_SAT_S_I16x8 = 1784
8720 CEFBS_HasSIMD128, // SUB_SAT_S_I16x8_S = 1785
8721 CEFBS_HasSIMD128, // SUB_SAT_S_I8x16 = 1786
8722 CEFBS_HasSIMD128, // SUB_SAT_S_I8x16_S = 1787
8723 CEFBS_HasSIMD128, // SUB_SAT_U_I16x8 = 1788
8724 CEFBS_HasSIMD128, // SUB_SAT_U_I16x8_S = 1789
8725 CEFBS_HasSIMD128, // SUB_SAT_U_I8x16 = 1790
8726 CEFBS_HasSIMD128, // SUB_SAT_U_I8x16_S = 1791
8727 CEFBS_HasSIMD128, // SWIZZLE = 1792
8728 CEFBS_HasSIMD128, // SWIZZLE_S = 1793
8729 CEFBS_HasReferenceTypes, // TABLE_COPY = 1794
8730 CEFBS_HasReferenceTypes, // TABLE_COPY_S = 1795
8731 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF = 1796
8732 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF_S = 1797
8733 CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF = 1798
8734 CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF_S = 1799
8735 CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF = 1800
8736 CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF_S = 1801
8737 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF = 1802
8738 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF_S = 1803
8739 CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF = 1804
8740 CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF_S = 1805
8741 CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF = 1806
8742 CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF_S = 1807
8743 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF = 1808
8744 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF_S = 1809
8745 CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF = 1810
8746 CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF_S = 1811
8747 CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF = 1812
8748 CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF_S = 1813
8749 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF = 1814
8750 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF_S = 1815
8751 CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF = 1816
8752 CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF_S = 1817
8753 CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF = 1818
8754 CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF_S = 1819
8755 CEFBS_HasReferenceTypes, // TABLE_SIZE = 1820
8756 CEFBS_HasReferenceTypes, // TABLE_SIZE_S = 1821
8757 CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF = 1822
8758 CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF_S = 1823
8759 CEFBS_HasReferenceTypes, // TEE_EXTERNREF = 1824
8760 CEFBS_HasReferenceTypes, // TEE_EXTERNREF_S = 1825
8761 CEFBS_None, // TEE_F32 = 1826
8762 CEFBS_None, // TEE_F32_S = 1827
8763 CEFBS_None, // TEE_F64 = 1828
8764 CEFBS_None, // TEE_F64_S = 1829
8765 CEFBS_HasReferenceTypes, // TEE_FUNCREF = 1830
8766 CEFBS_HasReferenceTypes, // TEE_FUNCREF_S = 1831
8767 CEFBS_None, // TEE_I32 = 1832
8768 CEFBS_None, // TEE_I32_S = 1833
8769 CEFBS_None, // TEE_I64 = 1834
8770 CEFBS_None, // TEE_I64_S = 1835
8771 CEFBS_HasSIMD128, // TEE_V128 = 1836
8772 CEFBS_HasSIMD128, // TEE_V128_S = 1837
8773 CEFBS_HasExceptionHandling, // THROW = 1838
8774 CEFBS_HasExceptionHandling, // THROW_REF = 1839
8775 CEFBS_HasExceptionHandling, // THROW_REF_S = 1840
8776 CEFBS_HasExceptionHandling, // THROW_S = 1841
8777 CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8 = 1842
8778 CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8_S = 1843
8779 CEFBS_None, // TRUNC_F32 = 1844
8780 CEFBS_None, // TRUNC_F32_S = 1845
8781 CEFBS_HasSIMD128, // TRUNC_F32x4 = 1846
8782 CEFBS_HasSIMD128, // TRUNC_F32x4_S = 1847
8783 CEFBS_None, // TRUNC_F64 = 1848
8784 CEFBS_None, // TRUNC_F64_S = 1849
8785 CEFBS_HasSIMD128, // TRUNC_F64x2 = 1850
8786 CEFBS_HasSIMD128, // TRUNC_F64x2_S = 1851
8787 CEFBS_HasExceptionHandling, // TRY = 1852
8788 CEFBS_HasExceptionHandling, // TRY_S = 1853
8789 CEFBS_HasExceptionHandling, // TRY_TABLE = 1854
8790 CEFBS_HasExceptionHandling, // TRY_TABLE_S = 1855
8791 CEFBS_None, // UNREACHABLE = 1856
8792 CEFBS_None, // UNREACHABLE_S = 1857
8793 CEFBS_HasSIMD128, // XOR = 1858
8794 CEFBS_None, // XOR_I32 = 1859
8795 CEFBS_None, // XOR_I32_S = 1860
8796 CEFBS_None, // XOR_I64 = 1861
8797 CEFBS_None, // XOR_I64_S = 1862
8798 CEFBS_HasSIMD128, // XOR_S = 1863
8799 CEFBS_None, // anonymous_8818MEMORY_GROW_A32 = 1864
8800 CEFBS_None, // anonymous_8818MEMORY_GROW_A32_S = 1865
8801 CEFBS_None, // anonymous_8818MEMORY_SIZE_A32 = 1866
8802 CEFBS_None, // anonymous_8818MEMORY_SIZE_A32_S = 1867
8803 CEFBS_None, // anonymous_8819MEMORY_GROW_A64 = 1868
8804 CEFBS_None, // anonymous_8819MEMORY_GROW_A64_S = 1869
8805 CEFBS_None, // anonymous_8819MEMORY_SIZE_A64 = 1870
8806 CEFBS_None, // anonymous_8819MEMORY_SIZE_A64_S = 1871
8807 CEFBS_HasSIMD128, // convert_low_s_F64x2 = 1872
8808 CEFBS_HasSIMD128, // convert_low_s_F64x2_S = 1873
8809 CEFBS_HasSIMD128, // convert_low_u_F64x2 = 1874
8810 CEFBS_HasSIMD128, // convert_low_u_F64x2_S = 1875
8811 CEFBS_HasSIMD128, // demote_zero_F32x4 = 1876
8812 CEFBS_HasSIMD128, // demote_zero_F32x4_S = 1877
8813 CEFBS_HasSIMD128, // extend_high_s_I16x8 = 1878
8814 CEFBS_HasSIMD128, // extend_high_s_I16x8_S = 1879
8815 CEFBS_HasSIMD128, // extend_high_s_I32x4 = 1880
8816 CEFBS_HasSIMD128, // extend_high_s_I32x4_S = 1881
8817 CEFBS_HasSIMD128, // extend_high_s_I64x2 = 1882
8818 CEFBS_HasSIMD128, // extend_high_s_I64x2_S = 1883
8819 CEFBS_HasSIMD128, // extend_high_u_I16x8 = 1884
8820 CEFBS_HasSIMD128, // extend_high_u_I16x8_S = 1885
8821 CEFBS_HasSIMD128, // extend_high_u_I32x4 = 1886
8822 CEFBS_HasSIMD128, // extend_high_u_I32x4_S = 1887
8823 CEFBS_HasSIMD128, // extend_high_u_I64x2 = 1888
8824 CEFBS_HasSIMD128, // extend_high_u_I64x2_S = 1889
8825 CEFBS_HasSIMD128, // extend_low_s_I16x8 = 1890
8826 CEFBS_HasSIMD128, // extend_low_s_I16x8_S = 1891
8827 CEFBS_HasSIMD128, // extend_low_s_I32x4 = 1892
8828 CEFBS_HasSIMD128, // extend_low_s_I32x4_S = 1893
8829 CEFBS_HasSIMD128, // extend_low_s_I64x2 = 1894
8830 CEFBS_HasSIMD128, // extend_low_s_I64x2_S = 1895
8831 CEFBS_HasSIMD128, // extend_low_u_I16x8 = 1896
8832 CEFBS_HasSIMD128, // extend_low_u_I16x8_S = 1897
8833 CEFBS_HasSIMD128, // extend_low_u_I32x4 = 1898
8834 CEFBS_HasSIMD128, // extend_low_u_I32x4_S = 1899
8835 CEFBS_HasSIMD128, // extend_low_u_I64x2 = 1900
8836 CEFBS_HasSIMD128, // extend_low_u_I64x2_S = 1901
8837 CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8 = 1902
8838 CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8_S = 1903
8839 CEFBS_HasSIMD128, // fp_to_sint_I32x4 = 1904
8840 CEFBS_HasSIMD128, // fp_to_sint_I32x4_S = 1905
8841 CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8 = 1906
8842 CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8_S = 1907
8843 CEFBS_HasSIMD128, // fp_to_uint_I32x4 = 1908
8844 CEFBS_HasSIMD128, // fp_to_uint_I32x4_S = 1909
8845 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I16x8 = 1910
8846 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I16x8_S = 1911
8847 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I32x4 = 1912
8848 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I32x4_S = 1913
8849 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I16x8 = 1914
8850 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I16x8_S = 1915
8851 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I32x4 = 1916
8852 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I32x4_S = 1917
8853 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4 = 1918
8854 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4_S = 1919
8855 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4 = 1920
8856 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4_S = 1921
8857 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4 = 1922
8858 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4_S = 1923
8859 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4 = 1924
8860 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S = 1925
8861 CEFBS_HasSIMD128, // promote_low_F64x2 = 1926
8862 CEFBS_HasSIMD128, // promote_low_F64x2_S = 1927
8863 CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8 = 1928
8864 CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8_S = 1929
8865 CEFBS_HasSIMD128, // sint_to_fp_F32x4 = 1930
8866 CEFBS_HasSIMD128, // sint_to_fp_F32x4_S = 1931
8867 CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4 = 1932
8868 CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4_S = 1933
8869 CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4 = 1934
8870 CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4_S = 1935
8871 CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8 = 1936
8872 CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8_S = 1937
8873 CEFBS_HasSIMD128, // uint_to_fp_F32x4 = 1938
8874 CEFBS_HasSIMD128, // uint_to_fp_F32x4_S = 1939
8875 };
8876
8877 assert(Opcode < 1940);
8878 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
8879}
8880
8881} // end namespace llvm::WebAssembly_MC
8882#endif // GET_COMPUTE_FEATURES
8883
8884#ifdef GET_AVAILABLE_OPCODE_CHECKER
8885#undef GET_AVAILABLE_OPCODE_CHECKER
8886namespace llvm::WebAssembly_MC {
8887bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
8888 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
8889 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
8890 FeatureBitset MissingFeatures =
8891 (AvailableFeatures & RequiredFeatures) ^
8892 RequiredFeatures;
8893 return !MissingFeatures.any();
8894}
8895} // end namespace llvm::WebAssembly_MC
8896#endif // GET_AVAILABLE_OPCODE_CHECKER
8897
8898#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
8899#undef ENABLE_INSTR_PREDICATE_VERIFIER
8900#include <sstream>
8901
8902namespace llvm::WebAssembly_MC {
8903#ifndef NDEBUG
8904static const char *SubtargetFeatureNames[] = {
8905 "Feature_HasAtomics",
8906 "Feature_HasBulkMemory",
8907 "Feature_HasBulkMemoryOpt",
8908 "Feature_HasCallIndirectOverlong",
8909 "Feature_HasExceptionHandling",
8910 "Feature_HasExtendedConst",
8911 "Feature_HasFP16",
8912 "Feature_HasMultiMemory",
8913 "Feature_HasMultivalue",
8914 "Feature_HasMutableGlobals",
8915 "Feature_HasNontrappingFPToInt",
8916 "Feature_HasReferenceTypes",
8917 "Feature_HasRelaxedSIMD",
8918 "Feature_HasSIMD128",
8919 "Feature_HasSignExt",
8920 "Feature_HasTailCall",
8921 "Feature_HasWideArithmetic",
8922 "Feature_NotHasNontrappingFPToInt",
8923 nullptr
8924};
8925
8926#endif // NDEBUG
8927
8928void verifyInstructionPredicates(
8929 unsigned Opcode, const FeatureBitset &Features) {
8930#ifndef NDEBUG
8931 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
8932 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
8933 FeatureBitset MissingFeatures =
8934 (AvailableFeatures & RequiredFeatures) ^
8935 RequiredFeatures;
8936 if (MissingFeatures.any()) {
8937 std::ostringstream Msg;
8938 Msg << "Attempting to emit " << &WebAssemblyInstrNameData[WebAssemblyInstrNameIndices[Opcode]]
8939 << " instruction but the ";
8940 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
8941 if (MissingFeatures.test(i))
8942 Msg << SubtargetFeatureNames[i] << " ";
8943 Msg << "predicate(s) are not met";
8944 report_fatal_error(Msg.str().c_str());
8945 }
8946#endif // NDEBUG
8947}
8948} // end namespace llvm::WebAssembly_MC
8949#endif // ENABLE_INSTR_PREDICATE_VERIFIER
8950
8951#ifdef GET_INSTRMAP_INFO
8952#undef GET_INSTRMAP_INFO
8953namespace llvm::WebAssembly {
8954
8955enum IsWasm64 {
8956 IsWasm64_1
8957};
8958
8959enum StackBased {
8960 StackBased_0,
8961 StackBased_1
8962};
8963
8964// getRegisterOpcode
8965LLVM_READONLY
8966int getRegisterOpcode(uint16_t Opcode) {
8967 using namespace WebAssembly;
8968 static constexpr uint16_t Table[][2] = {
8969 { CALL_PARAMS_S, CALL_PARAMS },
8970 { CALL_RESULTS_S, CALL_RESULTS },
8971 { CATCHRET_S, CATCHRET },
8972 { CLEANUPRET_S, CLEANUPRET },
8973 { COMPILER_FENCE_S, COMPILER_FENCE },
8974 { RET_CALL_RESULTS_S, RET_CALL_RESULTS },
8975 { ABS_F16x8_S, ABS_F16x8 },
8976 { ABS_F32_S, ABS_F32 },
8977 { ABS_F32x4_S, ABS_F32x4 },
8978 { ABS_F64_S, ABS_F64 },
8979 { ABS_F64x2_S, ABS_F64x2 },
8980 { ABS_I16x8_S, ABS_I16x8 },
8981 { ABS_I32x4_S, ABS_I32x4 },
8982 { ABS_I64x2_S, ABS_I64x2 },
8983 { ABS_I8x16_S, ABS_I8x16 },
8984 { ADD_F16x8_S, ADD_F16x8 },
8985 { ADD_F32_S, ADD_F32 },
8986 { ADD_F32x4_S, ADD_F32x4 },
8987 { ADD_F64_S, ADD_F64 },
8988 { ADD_F64x2_S, ADD_F64x2 },
8989 { ADD_I16x8_S, ADD_I16x8 },
8990 { ADD_I32_S, ADD_I32 },
8991 { ADD_I32x4_S, ADD_I32x4 },
8992 { ADD_I64_S, ADD_I64 },
8993 { ADD_I64x2_S, ADD_I64x2 },
8994 { ADD_I8x16_S, ADD_I8x16 },
8995 { ADD_SAT_S_I16x8_S, ADD_SAT_S_I16x8 },
8996 { ADD_SAT_S_I8x16_S, ADD_SAT_S_I8x16 },
8997 { ADD_SAT_U_I16x8_S, ADD_SAT_U_I16x8 },
8998 { ADD_SAT_U_I8x16_S, ADD_SAT_U_I8x16 },
8999 { ADJCALLSTACKDOWN_S, ADJCALLSTACKDOWN },
9000 { ADJCALLSTACKUP_S, ADJCALLSTACKUP },
9001 { ALLTRUE_I16x8_S, ALLTRUE_I16x8 },
9002 { ALLTRUE_I32x4_S, ALLTRUE_I32x4 },
9003 { ALLTRUE_I64x2_S, ALLTRUE_I64x2 },
9004 { ALLTRUE_I8x16_S, ALLTRUE_I8x16 },
9005 { ANDNOT_S, ANDNOT },
9006 { AND_I32_S, AND_I32 },
9007 { AND_I64_S, AND_I64 },
9008 { AND_S, AND },
9009 { ANYTRUE_S, ANYTRUE },
9010 { ARGUMENT_exnref_S, ARGUMENT_exnref },
9011 { ARGUMENT_externref_S, ARGUMENT_externref },
9012 { ARGUMENT_f32_S, ARGUMENT_f32 },
9013 { ARGUMENT_f64_S, ARGUMENT_f64 },
9014 { ARGUMENT_funcref_S, ARGUMENT_funcref },
9015 { ARGUMENT_i32_S, ARGUMENT_i32 },
9016 { ARGUMENT_i64_S, ARGUMENT_i64 },
9017 { ARGUMENT_v16i8_S, ARGUMENT_v16i8 },
9018 { ARGUMENT_v2f64_S, ARGUMENT_v2f64 },
9019 { ARGUMENT_v2i64_S, ARGUMENT_v2i64 },
9020 { ARGUMENT_v4f32_S, ARGUMENT_v4f32 },
9021 { ARGUMENT_v4i32_S, ARGUMENT_v4i32 },
9022 { ARGUMENT_v8f16_S, ARGUMENT_v8f16 },
9023 { ARGUMENT_v8i16_S, ARGUMENT_v8i16 },
9024 { ATOMIC_FENCE_S, ATOMIC_FENCE },
9025 { ATOMIC_LOAD16_U_I32_A32_S, ATOMIC_LOAD16_U_I32_A32 },
9026 { ATOMIC_LOAD16_U_I32_A64_S, ATOMIC_LOAD16_U_I32_A64 },
9027 { ATOMIC_LOAD16_U_I64_A32_S, ATOMIC_LOAD16_U_I64_A32 },
9028 { ATOMIC_LOAD16_U_I64_A64_S, ATOMIC_LOAD16_U_I64_A64 },
9029 { ATOMIC_LOAD32_U_I64_A32_S, ATOMIC_LOAD32_U_I64_A32 },
9030 { ATOMIC_LOAD32_U_I64_A64_S, ATOMIC_LOAD32_U_I64_A64 },
9031 { ATOMIC_LOAD8_U_I32_A32_S, ATOMIC_LOAD8_U_I32_A32 },
9032 { ATOMIC_LOAD8_U_I32_A64_S, ATOMIC_LOAD8_U_I32_A64 },
9033 { ATOMIC_LOAD8_U_I64_A32_S, ATOMIC_LOAD8_U_I64_A32 },
9034 { ATOMIC_LOAD8_U_I64_A64_S, ATOMIC_LOAD8_U_I64_A64 },
9035 { ATOMIC_LOAD_I32_A32_S, ATOMIC_LOAD_I32_A32 },
9036 { ATOMIC_LOAD_I32_A64_S, ATOMIC_LOAD_I32_A64 },
9037 { ATOMIC_LOAD_I64_A32_S, ATOMIC_LOAD_I64_A32 },
9038 { ATOMIC_LOAD_I64_A64_S, ATOMIC_LOAD_I64_A64 },
9039 { ATOMIC_RMW16_U_ADD_I32_A32_S, ATOMIC_RMW16_U_ADD_I32_A32 },
9040 { ATOMIC_RMW16_U_ADD_I32_A64_S, ATOMIC_RMW16_U_ADD_I32_A64 },
9041 { ATOMIC_RMW16_U_ADD_I64_A32_S, ATOMIC_RMW16_U_ADD_I64_A32 },
9042 { ATOMIC_RMW16_U_ADD_I64_A64_S, ATOMIC_RMW16_U_ADD_I64_A64 },
9043 { ATOMIC_RMW16_U_AND_I32_A32_S, ATOMIC_RMW16_U_AND_I32_A32 },
9044 { ATOMIC_RMW16_U_AND_I32_A64_S, ATOMIC_RMW16_U_AND_I32_A64 },
9045 { ATOMIC_RMW16_U_AND_I64_A32_S, ATOMIC_RMW16_U_AND_I64_A32 },
9046 { ATOMIC_RMW16_U_AND_I64_A64_S, ATOMIC_RMW16_U_AND_I64_A64 },
9047 { ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, ATOMIC_RMW16_U_CMPXCHG_I32_A32 },
9048 { ATOMIC_RMW16_U_CMPXCHG_I32_A64_S, ATOMIC_RMW16_U_CMPXCHG_I32_A64 },
9049 { ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, ATOMIC_RMW16_U_CMPXCHG_I64_A32 },
9050 { ATOMIC_RMW16_U_CMPXCHG_I64_A64_S, ATOMIC_RMW16_U_CMPXCHG_I64_A64 },
9051 { ATOMIC_RMW16_U_OR_I32_A32_S, ATOMIC_RMW16_U_OR_I32_A32 },
9052 { ATOMIC_RMW16_U_OR_I32_A64_S, ATOMIC_RMW16_U_OR_I32_A64 },
9053 { ATOMIC_RMW16_U_OR_I64_A32_S, ATOMIC_RMW16_U_OR_I64_A32 },
9054 { ATOMIC_RMW16_U_OR_I64_A64_S, ATOMIC_RMW16_U_OR_I64_A64 },
9055 { ATOMIC_RMW16_U_SUB_I32_A32_S, ATOMIC_RMW16_U_SUB_I32_A32 },
9056 { ATOMIC_RMW16_U_SUB_I32_A64_S, ATOMIC_RMW16_U_SUB_I32_A64 },
9057 { ATOMIC_RMW16_U_SUB_I64_A32_S, ATOMIC_RMW16_U_SUB_I64_A32 },
9058 { ATOMIC_RMW16_U_SUB_I64_A64_S, ATOMIC_RMW16_U_SUB_I64_A64 },
9059 { ATOMIC_RMW16_U_XCHG_I32_A32_S, ATOMIC_RMW16_U_XCHG_I32_A32 },
9060 { ATOMIC_RMW16_U_XCHG_I32_A64_S, ATOMIC_RMW16_U_XCHG_I32_A64 },
9061 { ATOMIC_RMW16_U_XCHG_I64_A32_S, ATOMIC_RMW16_U_XCHG_I64_A32 },
9062 { ATOMIC_RMW16_U_XCHG_I64_A64_S, ATOMIC_RMW16_U_XCHG_I64_A64 },
9063 { ATOMIC_RMW16_U_XOR_I32_A32_S, ATOMIC_RMW16_U_XOR_I32_A32 },
9064 { ATOMIC_RMW16_U_XOR_I32_A64_S, ATOMIC_RMW16_U_XOR_I32_A64 },
9065 { ATOMIC_RMW16_U_XOR_I64_A32_S, ATOMIC_RMW16_U_XOR_I64_A32 },
9066 { ATOMIC_RMW16_U_XOR_I64_A64_S, ATOMIC_RMW16_U_XOR_I64_A64 },
9067 { ATOMIC_RMW32_U_ADD_I64_A32_S, ATOMIC_RMW32_U_ADD_I64_A32 },
9068 { ATOMIC_RMW32_U_ADD_I64_A64_S, ATOMIC_RMW32_U_ADD_I64_A64 },
9069 { ATOMIC_RMW32_U_AND_I64_A32_S, ATOMIC_RMW32_U_AND_I64_A32 },
9070 { ATOMIC_RMW32_U_AND_I64_A64_S, ATOMIC_RMW32_U_AND_I64_A64 },
9071 { ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, ATOMIC_RMW32_U_CMPXCHG_I64_A32 },
9072 { ATOMIC_RMW32_U_CMPXCHG_I64_A64_S, ATOMIC_RMW32_U_CMPXCHG_I64_A64 },
9073 { ATOMIC_RMW32_U_OR_I64_A32_S, ATOMIC_RMW32_U_OR_I64_A32 },
9074 { ATOMIC_RMW32_U_OR_I64_A64_S, ATOMIC_RMW32_U_OR_I64_A64 },
9075 { ATOMIC_RMW32_U_SUB_I64_A32_S, ATOMIC_RMW32_U_SUB_I64_A32 },
9076 { ATOMIC_RMW32_U_SUB_I64_A64_S, ATOMIC_RMW32_U_SUB_I64_A64 },
9077 { ATOMIC_RMW32_U_XCHG_I64_A32_S, ATOMIC_RMW32_U_XCHG_I64_A32 },
9078 { ATOMIC_RMW32_U_XCHG_I64_A64_S, ATOMIC_RMW32_U_XCHG_I64_A64 },
9079 { ATOMIC_RMW32_U_XOR_I64_A32_S, ATOMIC_RMW32_U_XOR_I64_A32 },
9080 { ATOMIC_RMW32_U_XOR_I64_A64_S, ATOMIC_RMW32_U_XOR_I64_A64 },
9081 { ATOMIC_RMW8_U_ADD_I32_A32_S, ATOMIC_RMW8_U_ADD_I32_A32 },
9082 { ATOMIC_RMW8_U_ADD_I32_A64_S, ATOMIC_RMW8_U_ADD_I32_A64 },
9083 { ATOMIC_RMW8_U_ADD_I64_A32_S, ATOMIC_RMW8_U_ADD_I64_A32 },
9084 { ATOMIC_RMW8_U_ADD_I64_A64_S, ATOMIC_RMW8_U_ADD_I64_A64 },
9085 { ATOMIC_RMW8_U_AND_I32_A32_S, ATOMIC_RMW8_U_AND_I32_A32 },
9086 { ATOMIC_RMW8_U_AND_I32_A64_S, ATOMIC_RMW8_U_AND_I32_A64 },
9087 { ATOMIC_RMW8_U_AND_I64_A32_S, ATOMIC_RMW8_U_AND_I64_A32 },
9088 { ATOMIC_RMW8_U_AND_I64_A64_S, ATOMIC_RMW8_U_AND_I64_A64 },
9089 { ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, ATOMIC_RMW8_U_CMPXCHG_I32_A32 },
9090 { ATOMIC_RMW8_U_CMPXCHG_I32_A64_S, ATOMIC_RMW8_U_CMPXCHG_I32_A64 },
9091 { ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, ATOMIC_RMW8_U_CMPXCHG_I64_A32 },
9092 { ATOMIC_RMW8_U_CMPXCHG_I64_A64_S, ATOMIC_RMW8_U_CMPXCHG_I64_A64 },
9093 { ATOMIC_RMW8_U_OR_I32_A32_S, ATOMIC_RMW8_U_OR_I32_A32 },
9094 { ATOMIC_RMW8_U_OR_I32_A64_S, ATOMIC_RMW8_U_OR_I32_A64 },
9095 { ATOMIC_RMW8_U_OR_I64_A32_S, ATOMIC_RMW8_U_OR_I64_A32 },
9096 { ATOMIC_RMW8_U_OR_I64_A64_S, ATOMIC_RMW8_U_OR_I64_A64 },
9097 { ATOMIC_RMW8_U_SUB_I32_A32_S, ATOMIC_RMW8_U_SUB_I32_A32 },
9098 { ATOMIC_RMW8_U_SUB_I32_A64_S, ATOMIC_RMW8_U_SUB_I32_A64 },
9099 { ATOMIC_RMW8_U_SUB_I64_A32_S, ATOMIC_RMW8_U_SUB_I64_A32 },
9100 { ATOMIC_RMW8_U_SUB_I64_A64_S, ATOMIC_RMW8_U_SUB_I64_A64 },
9101 { ATOMIC_RMW8_U_XCHG_I32_A32_S, ATOMIC_RMW8_U_XCHG_I32_A32 },
9102 { ATOMIC_RMW8_U_XCHG_I32_A64_S, ATOMIC_RMW8_U_XCHG_I32_A64 },
9103 { ATOMIC_RMW8_U_XCHG_I64_A32_S, ATOMIC_RMW8_U_XCHG_I64_A32 },
9104 { ATOMIC_RMW8_U_XCHG_I64_A64_S, ATOMIC_RMW8_U_XCHG_I64_A64 },
9105 { ATOMIC_RMW8_U_XOR_I32_A32_S, ATOMIC_RMW8_U_XOR_I32_A32 },
9106 { ATOMIC_RMW8_U_XOR_I32_A64_S, ATOMIC_RMW8_U_XOR_I32_A64 },
9107 { ATOMIC_RMW8_U_XOR_I64_A32_S, ATOMIC_RMW8_U_XOR_I64_A32 },
9108 { ATOMIC_RMW8_U_XOR_I64_A64_S, ATOMIC_RMW8_U_XOR_I64_A64 },
9109 { ATOMIC_RMW_ADD_I32_A32_S, ATOMIC_RMW_ADD_I32_A32 },
9110 { ATOMIC_RMW_ADD_I32_A64_S, ATOMIC_RMW_ADD_I32_A64 },
9111 { ATOMIC_RMW_ADD_I64_A32_S, ATOMIC_RMW_ADD_I64_A32 },
9112 { ATOMIC_RMW_ADD_I64_A64_S, ATOMIC_RMW_ADD_I64_A64 },
9113 { ATOMIC_RMW_AND_I32_A32_S, ATOMIC_RMW_AND_I32_A32 },
9114 { ATOMIC_RMW_AND_I32_A64_S, ATOMIC_RMW_AND_I32_A64 },
9115 { ATOMIC_RMW_AND_I64_A32_S, ATOMIC_RMW_AND_I64_A32 },
9116 { ATOMIC_RMW_AND_I64_A64_S, ATOMIC_RMW_AND_I64_A64 },
9117 { ATOMIC_RMW_CMPXCHG_I32_A32_S, ATOMIC_RMW_CMPXCHG_I32_A32 },
9118 { ATOMIC_RMW_CMPXCHG_I32_A64_S, ATOMIC_RMW_CMPXCHG_I32_A64 },
9119 { ATOMIC_RMW_CMPXCHG_I64_A32_S, ATOMIC_RMW_CMPXCHG_I64_A32 },
9120 { ATOMIC_RMW_CMPXCHG_I64_A64_S, ATOMIC_RMW_CMPXCHG_I64_A64 },
9121 { ATOMIC_RMW_OR_I32_A32_S, ATOMIC_RMW_OR_I32_A32 },
9122 { ATOMIC_RMW_OR_I32_A64_S, ATOMIC_RMW_OR_I32_A64 },
9123 { ATOMIC_RMW_OR_I64_A32_S, ATOMIC_RMW_OR_I64_A32 },
9124 { ATOMIC_RMW_OR_I64_A64_S, ATOMIC_RMW_OR_I64_A64 },
9125 { ATOMIC_RMW_SUB_I32_A32_S, ATOMIC_RMW_SUB_I32_A32 },
9126 { ATOMIC_RMW_SUB_I32_A64_S, ATOMIC_RMW_SUB_I32_A64 },
9127 { ATOMIC_RMW_SUB_I64_A32_S, ATOMIC_RMW_SUB_I64_A32 },
9128 { ATOMIC_RMW_SUB_I64_A64_S, ATOMIC_RMW_SUB_I64_A64 },
9129 { ATOMIC_RMW_XCHG_I32_A32_S, ATOMIC_RMW_XCHG_I32_A32 },
9130 { ATOMIC_RMW_XCHG_I32_A64_S, ATOMIC_RMW_XCHG_I32_A64 },
9131 { ATOMIC_RMW_XCHG_I64_A32_S, ATOMIC_RMW_XCHG_I64_A32 },
9132 { ATOMIC_RMW_XCHG_I64_A64_S, ATOMIC_RMW_XCHG_I64_A64 },
9133 { ATOMIC_RMW_XOR_I32_A32_S, ATOMIC_RMW_XOR_I32_A32 },
9134 { ATOMIC_RMW_XOR_I32_A64_S, ATOMIC_RMW_XOR_I32_A64 },
9135 { ATOMIC_RMW_XOR_I64_A32_S, ATOMIC_RMW_XOR_I64_A32 },
9136 { ATOMIC_RMW_XOR_I64_A64_S, ATOMIC_RMW_XOR_I64_A64 },
9137 { ATOMIC_STORE16_I32_A32_S, ATOMIC_STORE16_I32_A32 },
9138 { ATOMIC_STORE16_I32_A64_S, ATOMIC_STORE16_I32_A64 },
9139 { ATOMIC_STORE16_I64_A32_S, ATOMIC_STORE16_I64_A32 },
9140 { ATOMIC_STORE16_I64_A64_S, ATOMIC_STORE16_I64_A64 },
9141 { ATOMIC_STORE32_I64_A32_S, ATOMIC_STORE32_I64_A32 },
9142 { ATOMIC_STORE32_I64_A64_S, ATOMIC_STORE32_I64_A64 },
9143 { ATOMIC_STORE8_I32_A32_S, ATOMIC_STORE8_I32_A32 },
9144 { ATOMIC_STORE8_I32_A64_S, ATOMIC_STORE8_I32_A64 },
9145 { ATOMIC_STORE8_I64_A32_S, ATOMIC_STORE8_I64_A32 },
9146 { ATOMIC_STORE8_I64_A64_S, ATOMIC_STORE8_I64_A64 },
9147 { ATOMIC_STORE_I32_A32_S, ATOMIC_STORE_I32_A32 },
9148 { ATOMIC_STORE_I32_A64_S, ATOMIC_STORE_I32_A64 },
9149 { ATOMIC_STORE_I64_A32_S, ATOMIC_STORE_I64_A32 },
9150 { ATOMIC_STORE_I64_A64_S, ATOMIC_STORE_I64_A64 },
9151 { AVGR_U_I16x8_S, AVGR_U_I16x8 },
9152 { AVGR_U_I8x16_S, AVGR_U_I8x16 },
9153 { BITMASK_I16x8_S, BITMASK_I16x8 },
9154 { BITMASK_I32x4_S, BITMASK_I32x4 },
9155 { BITMASK_I64x2_S, BITMASK_I64x2 },
9156 { BITMASK_I8x16_S, BITMASK_I8x16 },
9157 { BITSELECT_S, BITSELECT },
9158 { BLOCK_S, BLOCK },
9159 { BR_IF_S, BR_IF },
9160 { BR_S, BR },
9161 { BR_TABLE_I32_S, BR_TABLE_I32 },
9162 { BR_TABLE_I64_S, BR_TABLE_I64 },
9163 { BR_UNLESS_S, BR_UNLESS },
9164 { CALL_INDIRECT_S, CALL_INDIRECT },
9165 { CALL_S, CALL },
9166 { CATCH_ALL_LEGACY_S, CATCH_ALL_LEGACY },
9167 { CATCH_ALL_REF_S, CATCH_ALL_REF },
9168 { CATCH_ALL_S, CATCH_ALL },
9169 { CATCH_LEGACY_S, CATCH_LEGACY },
9170 { CATCH_REF_S, CATCH_REF },
9171 { CATCH_S, CATCH },
9172 { CEIL_F16x8_S, CEIL_F16x8 },
9173 { CEIL_F32_S, CEIL_F32 },
9174 { CEIL_F32x4_S, CEIL_F32x4 },
9175 { CEIL_F64_S, CEIL_F64 },
9176 { CEIL_F64x2_S, CEIL_F64x2 },
9177 { CLZ_I32_S, CLZ_I32 },
9178 { CLZ_I64_S, CLZ_I64 },
9179 { CONST_F32_S, CONST_F32 },
9180 { CONST_F64_S, CONST_F64 },
9181 { CONST_I32_S, CONST_I32 },
9182 { CONST_I64_S, CONST_I64 },
9183 { CONST_V128_F32x4_S, CONST_V128_F32x4 },
9184 { CONST_V128_F64x2_S, CONST_V128_F64x2 },
9185 { CONST_V128_I16x8_S, CONST_V128_I16x8 },
9186 { CONST_V128_I32x4_S, CONST_V128_I32x4 },
9187 { CONST_V128_I64x2_S, CONST_V128_I64x2 },
9188 { CONST_V128_I8x16_S, CONST_V128_I8x16 },
9189 { COPYSIGN_F32_S, COPYSIGN_F32 },
9190 { COPYSIGN_F64_S, COPYSIGN_F64 },
9191 { COPY_EXNREF_S, COPY_EXNREF },
9192 { COPY_EXTERNREF_S, COPY_EXTERNREF },
9193 { COPY_F32_S, COPY_F32 },
9194 { COPY_F64_S, COPY_F64 },
9195 { COPY_FUNCREF_S, COPY_FUNCREF },
9196 { COPY_I32_S, COPY_I32 },
9197 { COPY_I64_S, COPY_I64 },
9198 { COPY_V128_S, COPY_V128 },
9199 { CTZ_I32_S, CTZ_I32 },
9200 { CTZ_I64_S, CTZ_I64 },
9201 { DATA_DROP_S, DATA_DROP },
9202 { DEBUG_UNREACHABLE_S, DEBUG_UNREACHABLE },
9203 { DELEGATE_S, DELEGATE },
9204 { DIV_F16x8_S, DIV_F16x8 },
9205 { DIV_F32_S, DIV_F32 },
9206 { DIV_F32x4_S, DIV_F32x4 },
9207 { DIV_F64_S, DIV_F64 },
9208 { DIV_F64x2_S, DIV_F64x2 },
9209 { DIV_S_I32_S, DIV_S_I32 },
9210 { DIV_S_I64_S, DIV_S_I64 },
9211 { DIV_U_I32_S, DIV_U_I32 },
9212 { DIV_U_I64_S, DIV_U_I64 },
9213 { DOT_S, DOT },
9214 { DROP_EXNREF_S, DROP_EXNREF },
9215 { DROP_EXTERNREF_S, DROP_EXTERNREF },
9216 { DROP_F32_S, DROP_F32 },
9217 { DROP_F64_S, DROP_F64 },
9218 { DROP_FUNCREF_S, DROP_FUNCREF },
9219 { DROP_I32_S, DROP_I32 },
9220 { DROP_I64_S, DROP_I64 },
9221 { DROP_V128_S, DROP_V128 },
9222 { ELSE_S, ELSE },
9223 { END_BLOCK_S, END_BLOCK },
9224 { END_FUNCTION_S, END_FUNCTION },
9225 { END_IF_S, END_IF },
9226 { END_LOOP_S, END_LOOP },
9227 { END_S, END },
9228 { END_TRY_S, END_TRY },
9229 { END_TRY_TABLE_S, END_TRY_TABLE },
9230 { EQZ_I32_S, EQZ_I32 },
9231 { EQZ_I64_S, EQZ_I64 },
9232 { EQ_F16x8_S, EQ_F16x8 },
9233 { EQ_F32_S, EQ_F32 },
9234 { EQ_F32x4_S, EQ_F32x4 },
9235 { EQ_F64_S, EQ_F64 },
9236 { EQ_F64x2_S, EQ_F64x2 },
9237 { EQ_I16x8_S, EQ_I16x8 },
9238 { EQ_I32_S, EQ_I32 },
9239 { EQ_I32x4_S, EQ_I32x4 },
9240 { EQ_I64_S, EQ_I64 },
9241 { EQ_I64x2_S, EQ_I64x2 },
9242 { EQ_I8x16_S, EQ_I8x16 },
9243 { EXTMUL_HIGH_S_I16x8_S, EXTMUL_HIGH_S_I16x8 },
9244 { EXTMUL_HIGH_S_I32x4_S, EXTMUL_HIGH_S_I32x4 },
9245 { EXTMUL_HIGH_S_I64x2_S, EXTMUL_HIGH_S_I64x2 },
9246 { EXTMUL_HIGH_U_I16x8_S, EXTMUL_HIGH_U_I16x8 },
9247 { EXTMUL_HIGH_U_I32x4_S, EXTMUL_HIGH_U_I32x4 },
9248 { EXTMUL_HIGH_U_I64x2_S, EXTMUL_HIGH_U_I64x2 },
9249 { EXTMUL_LOW_S_I16x8_S, EXTMUL_LOW_S_I16x8 },
9250 { EXTMUL_LOW_S_I32x4_S, EXTMUL_LOW_S_I32x4 },
9251 { EXTMUL_LOW_S_I64x2_S, EXTMUL_LOW_S_I64x2 },
9252 { EXTMUL_LOW_U_I16x8_S, EXTMUL_LOW_U_I16x8 },
9253 { EXTMUL_LOW_U_I32x4_S, EXTMUL_LOW_U_I32x4 },
9254 { EXTMUL_LOW_U_I64x2_S, EXTMUL_LOW_U_I64x2 },
9255 { EXTRACT_LANE_F16x8_S, EXTRACT_LANE_F16x8 },
9256 { EXTRACT_LANE_F32x4_S, EXTRACT_LANE_F32x4 },
9257 { EXTRACT_LANE_F64x2_S, EXTRACT_LANE_F64x2 },
9258 { EXTRACT_LANE_I16x8_s_S, EXTRACT_LANE_I16x8_s },
9259 { EXTRACT_LANE_I16x8_u_S, EXTRACT_LANE_I16x8_u },
9260 { EXTRACT_LANE_I32x4_S, EXTRACT_LANE_I32x4 },
9261 { EXTRACT_LANE_I64x2_S, EXTRACT_LANE_I64x2 },
9262 { EXTRACT_LANE_I8x16_s_S, EXTRACT_LANE_I8x16_s },
9263 { EXTRACT_LANE_I8x16_u_S, EXTRACT_LANE_I8x16_u },
9264 { F32_CONVERT_S_I32_S, F32_CONVERT_S_I32 },
9265 { F32_CONVERT_S_I64_S, F32_CONVERT_S_I64 },
9266 { F32_CONVERT_U_I32_S, F32_CONVERT_U_I32 },
9267 { F32_CONVERT_U_I64_S, F32_CONVERT_U_I64 },
9268 { F32_DEMOTE_F64_S, F32_DEMOTE_F64 },
9269 { F32_REINTERPRET_I32_S, F32_REINTERPRET_I32 },
9270 { F64_CONVERT_S_I32_S, F64_CONVERT_S_I32 },
9271 { F64_CONVERT_S_I64_S, F64_CONVERT_S_I64 },
9272 { F64_CONVERT_U_I32_S, F64_CONVERT_U_I32 },
9273 { F64_CONVERT_U_I64_S, F64_CONVERT_U_I64 },
9274 { F64_PROMOTE_F32_S, F64_PROMOTE_F32 },
9275 { F64_REINTERPRET_I64_S, F64_REINTERPRET_I64 },
9276 { FALLTHROUGH_RETURN_S, FALLTHROUGH_RETURN },
9277 { FLOOR_F16x8_S, FLOOR_F16x8 },
9278 { FLOOR_F32_S, FLOOR_F32 },
9279 { FLOOR_F32x4_S, FLOOR_F32x4 },
9280 { FLOOR_F64_S, FLOOR_F64 },
9281 { FLOOR_F64x2_S, FLOOR_F64x2 },
9282 { FP_TO_SINT_I32_F32_S, FP_TO_SINT_I32_F32 },
9283 { FP_TO_SINT_I32_F64_S, FP_TO_SINT_I32_F64 },
9284 { FP_TO_SINT_I64_F32_S, FP_TO_SINT_I64_F32 },
9285 { FP_TO_SINT_I64_F64_S, FP_TO_SINT_I64_F64 },
9286 { FP_TO_UINT_I32_F32_S, FP_TO_UINT_I32_F32 },
9287 { FP_TO_UINT_I32_F64_S, FP_TO_UINT_I32_F64 },
9288 { FP_TO_UINT_I64_F32_S, FP_TO_UINT_I64_F32 },
9289 { FP_TO_UINT_I64_F64_S, FP_TO_UINT_I64_F64 },
9290 { GE_F16x8_S, GE_F16x8 },
9291 { GE_F32_S, GE_F32 },
9292 { GE_F32x4_S, GE_F32x4 },
9293 { GE_F64_S, GE_F64 },
9294 { GE_F64x2_S, GE_F64x2 },
9295 { GE_S_I16x8_S, GE_S_I16x8 },
9296 { GE_S_I32_S, GE_S_I32 },
9297 { GE_S_I32x4_S, GE_S_I32x4 },
9298 { GE_S_I64_S, GE_S_I64 },
9299 { GE_S_I64x2_S, GE_S_I64x2 },
9300 { GE_S_I8x16_S, GE_S_I8x16 },
9301 { GE_U_I16x8_S, GE_U_I16x8 },
9302 { GE_U_I32_S, GE_U_I32 },
9303 { GE_U_I32x4_S, GE_U_I32x4 },
9304 { GE_U_I64_S, GE_U_I64 },
9305 { GE_U_I8x16_S, GE_U_I8x16 },
9306 { GLOBAL_GET_EXNREF_S, GLOBAL_GET_EXNREF },
9307 { GLOBAL_GET_EXTERNREF_S, GLOBAL_GET_EXTERNREF },
9308 { GLOBAL_GET_F32_S, GLOBAL_GET_F32 },
9309 { GLOBAL_GET_F64_S, GLOBAL_GET_F64 },
9310 { GLOBAL_GET_FUNCREF_S, GLOBAL_GET_FUNCREF },
9311 { GLOBAL_GET_I32_S, GLOBAL_GET_I32 },
9312 { GLOBAL_GET_I64_S, GLOBAL_GET_I64 },
9313 { GLOBAL_GET_V128_S, GLOBAL_GET_V128 },
9314 { GLOBAL_SET_EXNREF_S, GLOBAL_SET_EXNREF },
9315 { GLOBAL_SET_EXTERNREF_S, GLOBAL_SET_EXTERNREF },
9316 { GLOBAL_SET_F32_S, GLOBAL_SET_F32 },
9317 { GLOBAL_SET_F64_S, GLOBAL_SET_F64 },
9318 { GLOBAL_SET_FUNCREF_S, GLOBAL_SET_FUNCREF },
9319 { GLOBAL_SET_I32_S, GLOBAL_SET_I32 },
9320 { GLOBAL_SET_I64_S, GLOBAL_SET_I64 },
9321 { GLOBAL_SET_V128_S, GLOBAL_SET_V128 },
9322 { GT_F16x8_S, GT_F16x8 },
9323 { GT_F32_S, GT_F32 },
9324 { GT_F32x4_S, GT_F32x4 },
9325 { GT_F64_S, GT_F64 },
9326 { GT_F64x2_S, GT_F64x2 },
9327 { GT_S_I16x8_S, GT_S_I16x8 },
9328 { GT_S_I32_S, GT_S_I32 },
9329 { GT_S_I32x4_S, GT_S_I32x4 },
9330 { GT_S_I64_S, GT_S_I64 },
9331 { GT_S_I64x2_S, GT_S_I64x2 },
9332 { GT_S_I8x16_S, GT_S_I8x16 },
9333 { GT_U_I16x8_S, GT_U_I16x8 },
9334 { GT_U_I32_S, GT_U_I32 },
9335 { GT_U_I32x4_S, GT_U_I32x4 },
9336 { GT_U_I64_S, GT_U_I64 },
9337 { GT_U_I8x16_S, GT_U_I8x16 },
9338 { I32_EXTEND16_S_I32_S, I32_EXTEND16_S_I32 },
9339 { I32_EXTEND8_S_I32_S, I32_EXTEND8_S_I32 },
9340 { I32_REINTERPRET_F32_S, I32_REINTERPRET_F32 },
9341 { I32_TRUNC_S_F32_S, I32_TRUNC_S_F32 },
9342 { I32_TRUNC_S_F64_S, I32_TRUNC_S_F64 },
9343 { I32_TRUNC_S_SAT_F32_S, I32_TRUNC_S_SAT_F32 },
9344 { I32_TRUNC_S_SAT_F64_S, I32_TRUNC_S_SAT_F64 },
9345 { I32_TRUNC_U_F32_S, I32_TRUNC_U_F32 },
9346 { I32_TRUNC_U_F64_S, I32_TRUNC_U_F64 },
9347 { I32_TRUNC_U_SAT_F32_S, I32_TRUNC_U_SAT_F32 },
9348 { I32_TRUNC_U_SAT_F64_S, I32_TRUNC_U_SAT_F64 },
9349 { I32_WRAP_I64_S, I32_WRAP_I64 },
9350 { I64_ADD128_S, I64_ADD128 },
9351 { I64_EXTEND16_S_I64_S, I64_EXTEND16_S_I64 },
9352 { I64_EXTEND32_S_I64_S, I64_EXTEND32_S_I64 },
9353 { I64_EXTEND8_S_I64_S, I64_EXTEND8_S_I64 },
9354 { I64_EXTEND_S_I32_S, I64_EXTEND_S_I32 },
9355 { I64_EXTEND_U_I32_S, I64_EXTEND_U_I32 },
9356 { I64_MUL_WIDE_S_S, I64_MUL_WIDE_S },
9357 { I64_MUL_WIDE_U_S, I64_MUL_WIDE_U },
9358 { I64_REINTERPRET_F64_S, I64_REINTERPRET_F64 },
9359 { I64_SUB128_S, I64_SUB128 },
9360 { I64_TRUNC_S_F32_S, I64_TRUNC_S_F32 },
9361 { I64_TRUNC_S_F64_S, I64_TRUNC_S_F64 },
9362 { I64_TRUNC_S_SAT_F32_S, I64_TRUNC_S_SAT_F32 },
9363 { I64_TRUNC_S_SAT_F64_S, I64_TRUNC_S_SAT_F64 },
9364 { I64_TRUNC_U_F32_S, I64_TRUNC_U_F32 },
9365 { I64_TRUNC_U_F64_S, I64_TRUNC_U_F64 },
9366 { I64_TRUNC_U_SAT_F32_S, I64_TRUNC_U_SAT_F32 },
9367 { I64_TRUNC_U_SAT_F64_S, I64_TRUNC_U_SAT_F64 },
9368 { IF_S, IF },
9369 { LANESELECT_I16x8_S, LANESELECT_I16x8 },
9370 { LANESELECT_I32x4_S, LANESELECT_I32x4 },
9371 { LANESELECT_I64x2_S, LANESELECT_I64x2 },
9372 { LANESELECT_I8x16_S, LANESELECT_I8x16 },
9373 { LE_F16x8_S, LE_F16x8 },
9374 { LE_F32_S, LE_F32 },
9375 { LE_F32x4_S, LE_F32x4 },
9376 { LE_F64_S, LE_F64 },
9377 { LE_F64x2_S, LE_F64x2 },
9378 { LE_S_I16x8_S, LE_S_I16x8 },
9379 { LE_S_I32_S, LE_S_I32 },
9380 { LE_S_I32x4_S, LE_S_I32x4 },
9381 { LE_S_I64_S, LE_S_I64 },
9382 { LE_S_I64x2_S, LE_S_I64x2 },
9383 { LE_S_I8x16_S, LE_S_I8x16 },
9384 { LE_U_I16x8_S, LE_U_I16x8 },
9385 { LE_U_I32_S, LE_U_I32 },
9386 { LE_U_I32x4_S, LE_U_I32x4 },
9387 { LE_U_I64_S, LE_U_I64 },
9388 { LE_U_I8x16_S, LE_U_I8x16 },
9389 { LOAD16_SPLAT_A32_S, LOAD16_SPLAT_A32 },
9390 { LOAD16_SPLAT_A64_S, LOAD16_SPLAT_A64 },
9391 { LOAD16_S_I32_A32_S, LOAD16_S_I32_A32 },
9392 { LOAD16_S_I32_A64_S, LOAD16_S_I32_A64 },
9393 { LOAD16_S_I64_A32_S, LOAD16_S_I64_A32 },
9394 { LOAD16_S_I64_A64_S, LOAD16_S_I64_A64 },
9395 { LOAD16_U_I32_A32_S, LOAD16_U_I32_A32 },
9396 { LOAD16_U_I32_A64_S, LOAD16_U_I32_A64 },
9397 { LOAD16_U_I64_A32_S, LOAD16_U_I64_A32 },
9398 { LOAD16_U_I64_A64_S, LOAD16_U_I64_A64 },
9399 { LOAD32_SPLAT_A32_S, LOAD32_SPLAT_A32 },
9400 { LOAD32_SPLAT_A64_S, LOAD32_SPLAT_A64 },
9401 { LOAD32_S_I64_A32_S, LOAD32_S_I64_A32 },
9402 { LOAD32_S_I64_A64_S, LOAD32_S_I64_A64 },
9403 { LOAD32_U_I64_A32_S, LOAD32_U_I64_A32 },
9404 { LOAD32_U_I64_A64_S, LOAD32_U_I64_A64 },
9405 { LOAD64_SPLAT_A32_S, LOAD64_SPLAT_A32 },
9406 { LOAD64_SPLAT_A64_S, LOAD64_SPLAT_A64 },
9407 { LOAD8_SPLAT_A32_S, LOAD8_SPLAT_A32 },
9408 { LOAD8_SPLAT_A64_S, LOAD8_SPLAT_A64 },
9409 { LOAD8_S_I32_A32_S, LOAD8_S_I32_A32 },
9410 { LOAD8_S_I32_A64_S, LOAD8_S_I32_A64 },
9411 { LOAD8_S_I64_A32_S, LOAD8_S_I64_A32 },
9412 { LOAD8_S_I64_A64_S, LOAD8_S_I64_A64 },
9413 { LOAD8_U_I32_A32_S, LOAD8_U_I32_A32 },
9414 { LOAD8_U_I32_A64_S, LOAD8_U_I32_A64 },
9415 { LOAD8_U_I64_A32_S, LOAD8_U_I64_A32 },
9416 { LOAD8_U_I64_A64_S, LOAD8_U_I64_A64 },
9417 { LOAD_EXTEND_S_I16x8_A32_S, LOAD_EXTEND_S_I16x8_A32 },
9418 { LOAD_EXTEND_S_I16x8_A64_S, LOAD_EXTEND_S_I16x8_A64 },
9419 { LOAD_EXTEND_S_I32x4_A32_S, LOAD_EXTEND_S_I32x4_A32 },
9420 { LOAD_EXTEND_S_I32x4_A64_S, LOAD_EXTEND_S_I32x4_A64 },
9421 { LOAD_EXTEND_S_I64x2_A32_S, LOAD_EXTEND_S_I64x2_A32 },
9422 { LOAD_EXTEND_S_I64x2_A64_S, LOAD_EXTEND_S_I64x2_A64 },
9423 { LOAD_EXTEND_U_I16x8_A32_S, LOAD_EXTEND_U_I16x8_A32 },
9424 { LOAD_EXTEND_U_I16x8_A64_S, LOAD_EXTEND_U_I16x8_A64 },
9425 { LOAD_EXTEND_U_I32x4_A32_S, LOAD_EXTEND_U_I32x4_A32 },
9426 { LOAD_EXTEND_U_I32x4_A64_S, LOAD_EXTEND_U_I32x4_A64 },
9427 { LOAD_EXTEND_U_I64x2_A32_S, LOAD_EXTEND_U_I64x2_A32 },
9428 { LOAD_EXTEND_U_I64x2_A64_S, LOAD_EXTEND_U_I64x2_A64 },
9429 { LOAD_F16_F32_A32_S, LOAD_F16_F32_A32 },
9430 { LOAD_F16_F32_A64_S, LOAD_F16_F32_A64 },
9431 { LOAD_F32_A32_S, LOAD_F32_A32 },
9432 { LOAD_F32_A64_S, LOAD_F32_A64 },
9433 { LOAD_F64_A32_S, LOAD_F64_A32 },
9434 { LOAD_F64_A64_S, LOAD_F64_A64 },
9435 { LOAD_I32_A32_S, LOAD_I32_A32 },
9436 { LOAD_I32_A64_S, LOAD_I32_A64 },
9437 { LOAD_I64_A32_S, LOAD_I64_A32 },
9438 { LOAD_I64_A64_S, LOAD_I64_A64 },
9439 { LOAD_LANE_16_A32_S, LOAD_LANE_16_A32 },
9440 { LOAD_LANE_16_A64_S, LOAD_LANE_16_A64 },
9441 { LOAD_LANE_32_A32_S, LOAD_LANE_32_A32 },
9442 { LOAD_LANE_32_A64_S, LOAD_LANE_32_A64 },
9443 { LOAD_LANE_64_A32_S, LOAD_LANE_64_A32 },
9444 { LOAD_LANE_64_A64_S, LOAD_LANE_64_A64 },
9445 { LOAD_LANE_8_A32_S, LOAD_LANE_8_A32 },
9446 { LOAD_LANE_8_A64_S, LOAD_LANE_8_A64 },
9447 { LOAD_V128_A32_S, LOAD_V128_A32 },
9448 { LOAD_V128_A64_S, LOAD_V128_A64 },
9449 { LOAD_ZERO_32_A32_S, LOAD_ZERO_32_A32 },
9450 { LOAD_ZERO_32_A64_S, LOAD_ZERO_32_A64 },
9451 { LOAD_ZERO_64_A32_S, LOAD_ZERO_64_A32 },
9452 { LOAD_ZERO_64_A64_S, LOAD_ZERO_64_A64 },
9453 { LOCAL_GET_EXNREF_S, LOCAL_GET_EXNREF },
9454 { LOCAL_GET_EXTERNREF_S, LOCAL_GET_EXTERNREF },
9455 { LOCAL_GET_F32_S, LOCAL_GET_F32 },
9456 { LOCAL_GET_F64_S, LOCAL_GET_F64 },
9457 { LOCAL_GET_FUNCREF_S, LOCAL_GET_FUNCREF },
9458 { LOCAL_GET_I32_S, LOCAL_GET_I32 },
9459 { LOCAL_GET_I64_S, LOCAL_GET_I64 },
9460 { LOCAL_GET_V128_S, LOCAL_GET_V128 },
9461 { LOCAL_SET_EXNREF_S, LOCAL_SET_EXNREF },
9462 { LOCAL_SET_EXTERNREF_S, LOCAL_SET_EXTERNREF },
9463 { LOCAL_SET_F32_S, LOCAL_SET_F32 },
9464 { LOCAL_SET_F64_S, LOCAL_SET_F64 },
9465 { LOCAL_SET_FUNCREF_S, LOCAL_SET_FUNCREF },
9466 { LOCAL_SET_I32_S, LOCAL_SET_I32 },
9467 { LOCAL_SET_I64_S, LOCAL_SET_I64 },
9468 { LOCAL_SET_V128_S, LOCAL_SET_V128 },
9469 { LOCAL_TEE_EXNREF_S, LOCAL_TEE_EXNREF },
9470 { LOCAL_TEE_EXTERNREF_S, LOCAL_TEE_EXTERNREF },
9471 { LOCAL_TEE_F32_S, LOCAL_TEE_F32 },
9472 { LOCAL_TEE_F64_S, LOCAL_TEE_F64 },
9473 { LOCAL_TEE_FUNCREF_S, LOCAL_TEE_FUNCREF },
9474 { LOCAL_TEE_I32_S, LOCAL_TEE_I32 },
9475 { LOCAL_TEE_I64_S, LOCAL_TEE_I64 },
9476 { LOCAL_TEE_V128_S, LOCAL_TEE_V128 },
9477 { LOOP_S, LOOP },
9478 { LT_F16x8_S, LT_F16x8 },
9479 { LT_F32_S, LT_F32 },
9480 { LT_F32x4_S, LT_F32x4 },
9481 { LT_F64_S, LT_F64 },
9482 { LT_F64x2_S, LT_F64x2 },
9483 { LT_S_I16x8_S, LT_S_I16x8 },
9484 { LT_S_I32_S, LT_S_I32 },
9485 { LT_S_I32x4_S, LT_S_I32x4 },
9486 { LT_S_I64_S, LT_S_I64 },
9487 { LT_S_I64x2_S, LT_S_I64x2 },
9488 { LT_S_I8x16_S, LT_S_I8x16 },
9489 { LT_U_I16x8_S, LT_U_I16x8 },
9490 { LT_U_I32_S, LT_U_I32 },
9491 { LT_U_I32x4_S, LT_U_I32x4 },
9492 { LT_U_I64_S, LT_U_I64 },
9493 { LT_U_I8x16_S, LT_U_I8x16 },
9494 { MADD_F16x8_S, MADD_F16x8 },
9495 { MADD_F32x4_S, MADD_F32x4 },
9496 { MADD_F64x2_S, MADD_F64x2 },
9497 { MAX_F16x8_S, MAX_F16x8 },
9498 { MAX_F32_S, MAX_F32 },
9499 { MAX_F32x4_S, MAX_F32x4 },
9500 { MAX_F64_S, MAX_F64 },
9501 { MAX_F64x2_S, MAX_F64x2 },
9502 { MAX_S_I16x8_S, MAX_S_I16x8 },
9503 { MAX_S_I32x4_S, MAX_S_I32x4 },
9504 { MAX_S_I8x16_S, MAX_S_I8x16 },
9505 { MAX_U_I16x8_S, MAX_U_I16x8 },
9506 { MAX_U_I32x4_S, MAX_U_I32x4 },
9507 { MAX_U_I8x16_S, MAX_U_I8x16 },
9508 { MEMCPY_A32_S, MEMCPY_A32 },
9509 { MEMCPY_A64_S, MEMCPY_A64 },
9510 { MEMORY_ATOMIC_NOTIFY_A32_S, MEMORY_ATOMIC_NOTIFY_A32 },
9511 { MEMORY_ATOMIC_NOTIFY_A64_S, MEMORY_ATOMIC_NOTIFY_A64 },
9512 { MEMORY_ATOMIC_WAIT32_A32_S, MEMORY_ATOMIC_WAIT32_A32 },
9513 { MEMORY_ATOMIC_WAIT32_A64_S, MEMORY_ATOMIC_WAIT32_A64 },
9514 { MEMORY_ATOMIC_WAIT64_A32_S, MEMORY_ATOMIC_WAIT64_A32 },
9515 { MEMORY_ATOMIC_WAIT64_A64_S, MEMORY_ATOMIC_WAIT64_A64 },
9516 { MEMORY_COPY_A32_S, MEMORY_COPY_A32 },
9517 { MEMORY_COPY_A64_S, MEMORY_COPY_A64 },
9518 { MEMORY_FILL_A32_S, MEMORY_FILL_A32 },
9519 { MEMORY_FILL_A64_S, MEMORY_FILL_A64 },
9520 { MEMORY_INIT_A32_S, MEMORY_INIT_A32 },
9521 { MEMORY_INIT_A64_S, MEMORY_INIT_A64 },
9522 { MEMSET_A32_S, MEMSET_A32 },
9523 { MEMSET_A64_S, MEMSET_A64 },
9524 { MIN_F16x8_S, MIN_F16x8 },
9525 { MIN_F32_S, MIN_F32 },
9526 { MIN_F32x4_S, MIN_F32x4 },
9527 { MIN_F64_S, MIN_F64 },
9528 { MIN_F64x2_S, MIN_F64x2 },
9529 { MIN_S_I16x8_S, MIN_S_I16x8 },
9530 { MIN_S_I32x4_S, MIN_S_I32x4 },
9531 { MIN_S_I8x16_S, MIN_S_I8x16 },
9532 { MIN_U_I16x8_S, MIN_U_I16x8 },
9533 { MIN_U_I32x4_S, MIN_U_I32x4 },
9534 { MIN_U_I8x16_S, MIN_U_I8x16 },
9535 { MUL_F16x8_S, MUL_F16x8 },
9536 { MUL_F32_S, MUL_F32 },
9537 { MUL_F32x4_S, MUL_F32x4 },
9538 { MUL_F64_S, MUL_F64 },
9539 { MUL_F64x2_S, MUL_F64x2 },
9540 { MUL_I16x8_S, MUL_I16x8 },
9541 { MUL_I32_S, MUL_I32 },
9542 { MUL_I32x4_S, MUL_I32x4 },
9543 { MUL_I64_S, MUL_I64 },
9544 { MUL_I64x2_S, MUL_I64x2 },
9545 { NARROW_S_I16x8_S, NARROW_S_I16x8 },
9546 { NARROW_S_I8x16_S, NARROW_S_I8x16 },
9547 { NARROW_U_I16x8_S, NARROW_U_I16x8 },
9548 { NARROW_U_I8x16_S, NARROW_U_I8x16 },
9549 { NEAREST_F16x8_S, NEAREST_F16x8 },
9550 { NEAREST_F32_S, NEAREST_F32 },
9551 { NEAREST_F32x4_S, NEAREST_F32x4 },
9552 { NEAREST_F64_S, NEAREST_F64 },
9553 { NEAREST_F64x2_S, NEAREST_F64x2 },
9554 { NEG_F16x8_S, NEG_F16x8 },
9555 { NEG_F32_S, NEG_F32 },
9556 { NEG_F32x4_S, NEG_F32x4 },
9557 { NEG_F64_S, NEG_F64 },
9558 { NEG_F64x2_S, NEG_F64x2 },
9559 { NEG_I16x8_S, NEG_I16x8 },
9560 { NEG_I32x4_S, NEG_I32x4 },
9561 { NEG_I64x2_S, NEG_I64x2 },
9562 { NEG_I8x16_S, NEG_I8x16 },
9563 { NE_F16x8_S, NE_F16x8 },
9564 { NE_F32_S, NE_F32 },
9565 { NE_F32x4_S, NE_F32x4 },
9566 { NE_F64_S, NE_F64 },
9567 { NE_F64x2_S, NE_F64x2 },
9568 { NE_I16x8_S, NE_I16x8 },
9569 { NE_I32_S, NE_I32 },
9570 { NE_I32x4_S, NE_I32x4 },
9571 { NE_I64_S, NE_I64 },
9572 { NE_I64x2_S, NE_I64x2 },
9573 { NE_I8x16_S, NE_I8x16 },
9574 { NMADD_F16x8_S, NMADD_F16x8 },
9575 { NMADD_F32x4_S, NMADD_F32x4 },
9576 { NMADD_F64x2_S, NMADD_F64x2 },
9577 { NOP_S, NOP },
9578 { NOT_S, NOT },
9579 { OR_I32_S, OR_I32 },
9580 { OR_I64_S, OR_I64 },
9581 { OR_S, OR },
9582 { PMAX_F16x8_S, PMAX_F16x8 },
9583 { PMAX_F32x4_S, PMAX_F32x4 },
9584 { PMAX_F64x2_S, PMAX_F64x2 },
9585 { PMIN_F16x8_S, PMIN_F16x8 },
9586 { PMIN_F32x4_S, PMIN_F32x4 },
9587 { PMIN_F64x2_S, PMIN_F64x2 },
9588 { POPCNT_I32_S, POPCNT_I32 },
9589 { POPCNT_I64_S, POPCNT_I64 },
9590 { POPCNT_I8x16_S, POPCNT_I8x16 },
9591 { Q15MULR_SAT_S_I16x8_S, Q15MULR_SAT_S_I16x8 },
9592 { REF_IS_NULL_EXNREF_S, REF_IS_NULL_EXNREF },
9593 { REF_IS_NULL_EXTERNREF_S, REF_IS_NULL_EXTERNREF },
9594 { REF_IS_NULL_FUNCREF_S, REF_IS_NULL_FUNCREF },
9595 { REF_NULL_EXNREF_S, REF_NULL_EXNREF },
9596 { REF_NULL_EXTERNREF_S, REF_NULL_EXTERNREF },
9597 { REF_NULL_FUNCREF_S, REF_NULL_FUNCREF },
9598 { RELAXED_DOT_ADD_S, RELAXED_DOT_ADD },
9599 { RELAXED_DOT_BFLOAT_S, RELAXED_DOT_BFLOAT },
9600 { RELAXED_DOT_S, RELAXED_DOT },
9601 { RELAXED_Q15MULR_S_I16x8_S, RELAXED_Q15MULR_S_I16x8 },
9602 { RELAXED_SWIZZLE_S, RELAXED_SWIZZLE },
9603 { REM_S_I32_S, REM_S_I32 },
9604 { REM_S_I64_S, REM_S_I64 },
9605 { REM_U_I32_S, REM_U_I32 },
9606 { REM_U_I64_S, REM_U_I64 },
9607 { REPLACE_LANE_F16x8_S, REPLACE_LANE_F16x8 },
9608 { REPLACE_LANE_F32x4_S, REPLACE_LANE_F32x4 },
9609 { REPLACE_LANE_F64x2_S, REPLACE_LANE_F64x2 },
9610 { REPLACE_LANE_I16x8_S, REPLACE_LANE_I16x8 },
9611 { REPLACE_LANE_I32x4_S, REPLACE_LANE_I32x4 },
9612 { REPLACE_LANE_I64x2_S, REPLACE_LANE_I64x2 },
9613 { REPLACE_LANE_I8x16_S, REPLACE_LANE_I8x16 },
9614 { RETHROW_S, RETHROW },
9615 { RETURN_S, RETURN },
9616 { RET_CALL_INDIRECT_S, RET_CALL_INDIRECT },
9617 { RET_CALL_S, RET_CALL },
9618 { ROTL_I32_S, ROTL_I32 },
9619 { ROTL_I64_S, ROTL_I64 },
9620 { ROTR_I32_S, ROTR_I32 },
9621 { ROTR_I64_S, ROTR_I64 },
9622 { SELECT_EXNREF_S, SELECT_EXNREF },
9623 { SELECT_EXTERNREF_S, SELECT_EXTERNREF },
9624 { SELECT_F32_S, SELECT_F32 },
9625 { SELECT_F64_S, SELECT_F64 },
9626 { SELECT_FUNCREF_S, SELECT_FUNCREF },
9627 { SELECT_I32_S, SELECT_I32 },
9628 { SELECT_I64_S, SELECT_I64 },
9629 { SELECT_V128_S, SELECT_V128 },
9630 { SHL_I16x8_S, SHL_I16x8 },
9631 { SHL_I32_S, SHL_I32 },
9632 { SHL_I32x4_S, SHL_I32x4 },
9633 { SHL_I64_S, SHL_I64 },
9634 { SHL_I64x2_S, SHL_I64x2 },
9635 { SHL_I8x16_S, SHL_I8x16 },
9636 { SHR_S_I16x8_S, SHR_S_I16x8 },
9637 { SHR_S_I32_S, SHR_S_I32 },
9638 { SHR_S_I32x4_S, SHR_S_I32x4 },
9639 { SHR_S_I64_S, SHR_S_I64 },
9640 { SHR_S_I64x2_S, SHR_S_I64x2 },
9641 { SHR_S_I8x16_S, SHR_S_I8x16 },
9642 { SHR_U_I16x8_S, SHR_U_I16x8 },
9643 { SHR_U_I32_S, SHR_U_I32 },
9644 { SHR_U_I32x4_S, SHR_U_I32x4 },
9645 { SHR_U_I64_S, SHR_U_I64 },
9646 { SHR_U_I64x2_S, SHR_U_I64x2 },
9647 { SHR_U_I8x16_S, SHR_U_I8x16 },
9648 { SHUFFLE_S, SHUFFLE },
9649 { SIMD_RELAXED_FMAX_F32x4_S, SIMD_RELAXED_FMAX_F32x4 },
9650 { SIMD_RELAXED_FMAX_F64x2_S, SIMD_RELAXED_FMAX_F64x2 },
9651 { SIMD_RELAXED_FMIN_F32x4_S, SIMD_RELAXED_FMIN_F32x4 },
9652 { SIMD_RELAXED_FMIN_F64x2_S, SIMD_RELAXED_FMIN_F64x2 },
9653 { SPLAT_F16x8_S, SPLAT_F16x8 },
9654 { SPLAT_F32x4_S, SPLAT_F32x4 },
9655 { SPLAT_F64x2_S, SPLAT_F64x2 },
9656 { SPLAT_I16x8_S, SPLAT_I16x8 },
9657 { SPLAT_I32x4_S, SPLAT_I32x4 },
9658 { SPLAT_I64x2_S, SPLAT_I64x2 },
9659 { SPLAT_I8x16_S, SPLAT_I8x16 },
9660 { SQRT_F16x8_S, SQRT_F16x8 },
9661 { SQRT_F32_S, SQRT_F32 },
9662 { SQRT_F32x4_S, SQRT_F32x4 },
9663 { SQRT_F64_S, SQRT_F64 },
9664 { SQRT_F64x2_S, SQRT_F64x2 },
9665 { STORE16_I32_A32_S, STORE16_I32_A32 },
9666 { STORE16_I32_A64_S, STORE16_I32_A64 },
9667 { STORE16_I64_A32_S, STORE16_I64_A32 },
9668 { STORE16_I64_A64_S, STORE16_I64_A64 },
9669 { STORE32_I64_A32_S, STORE32_I64_A32 },
9670 { STORE32_I64_A64_S, STORE32_I64_A64 },
9671 { STORE8_I32_A32_S, STORE8_I32_A32 },
9672 { STORE8_I32_A64_S, STORE8_I32_A64 },
9673 { STORE8_I64_A32_S, STORE8_I64_A32 },
9674 { STORE8_I64_A64_S, STORE8_I64_A64 },
9675 { STORE_F16_F32_A32_S, STORE_F16_F32_A32 },
9676 { STORE_F16_F32_A64_S, STORE_F16_F32_A64 },
9677 { STORE_F32_A32_S, STORE_F32_A32 },
9678 { STORE_F32_A64_S, STORE_F32_A64 },
9679 { STORE_F64_A32_S, STORE_F64_A32 },
9680 { STORE_F64_A64_S, STORE_F64_A64 },
9681 { STORE_I32_A32_S, STORE_I32_A32 },
9682 { STORE_I32_A64_S, STORE_I32_A64 },
9683 { STORE_I64_A32_S, STORE_I64_A32 },
9684 { STORE_I64_A64_S, STORE_I64_A64 },
9685 { STORE_LANE_I16x8_A32_S, STORE_LANE_I16x8_A32 },
9686 { STORE_LANE_I16x8_A64_S, STORE_LANE_I16x8_A64 },
9687 { STORE_LANE_I32x4_A32_S, STORE_LANE_I32x4_A32 },
9688 { STORE_LANE_I32x4_A64_S, STORE_LANE_I32x4_A64 },
9689 { STORE_LANE_I64x2_A32_S, STORE_LANE_I64x2_A32 },
9690 { STORE_LANE_I64x2_A64_S, STORE_LANE_I64x2_A64 },
9691 { STORE_LANE_I8x16_A32_S, STORE_LANE_I8x16_A32 },
9692 { STORE_LANE_I8x16_A64_S, STORE_LANE_I8x16_A64 },
9693 { STORE_V128_A32_S, STORE_V128_A32 },
9694 { STORE_V128_A64_S, STORE_V128_A64 },
9695 { SUB_F16x8_S, SUB_F16x8 },
9696 { SUB_F32_S, SUB_F32 },
9697 { SUB_F32x4_S, SUB_F32x4 },
9698 { SUB_F64_S, SUB_F64 },
9699 { SUB_F64x2_S, SUB_F64x2 },
9700 { SUB_I16x8_S, SUB_I16x8 },
9701 { SUB_I32_S, SUB_I32 },
9702 { SUB_I32x4_S, SUB_I32x4 },
9703 { SUB_I64_S, SUB_I64 },
9704 { SUB_I64x2_S, SUB_I64x2 },
9705 { SUB_I8x16_S, SUB_I8x16 },
9706 { SUB_SAT_S_I16x8_S, SUB_SAT_S_I16x8 },
9707 { SUB_SAT_S_I8x16_S, SUB_SAT_S_I8x16 },
9708 { SUB_SAT_U_I16x8_S, SUB_SAT_U_I16x8 },
9709 { SUB_SAT_U_I8x16_S, SUB_SAT_U_I8x16 },
9710 { SWIZZLE_S, SWIZZLE },
9711 { TABLE_COPY_S, TABLE_COPY },
9712 { TABLE_FILL_EXNREF_S, TABLE_FILL_EXNREF },
9713 { TABLE_FILL_EXTERNREF_S, TABLE_FILL_EXTERNREF },
9714 { TABLE_FILL_FUNCREF_S, TABLE_FILL_FUNCREF },
9715 { TABLE_GET_EXNREF_S, TABLE_GET_EXNREF },
9716 { TABLE_GET_EXTERNREF_S, TABLE_GET_EXTERNREF },
9717 { TABLE_GET_FUNCREF_S, TABLE_GET_FUNCREF },
9718 { TABLE_GROW_EXNREF_S, TABLE_GROW_EXNREF },
9719 { TABLE_GROW_EXTERNREF_S, TABLE_GROW_EXTERNREF },
9720 { TABLE_GROW_FUNCREF_S, TABLE_GROW_FUNCREF },
9721 { TABLE_SET_EXNREF_S, TABLE_SET_EXNREF },
9722 { TABLE_SET_EXTERNREF_S, TABLE_SET_EXTERNREF },
9723 { TABLE_SET_FUNCREF_S, TABLE_SET_FUNCREF },
9724 { TABLE_SIZE_S, TABLE_SIZE },
9725 { TEE_EXNREF_S, TEE_EXNREF },
9726 { TEE_EXTERNREF_S, TEE_EXTERNREF },
9727 { TEE_F32_S, TEE_F32 },
9728 { TEE_F64_S, TEE_F64 },
9729 { TEE_FUNCREF_S, TEE_FUNCREF },
9730 { TEE_I32_S, TEE_I32 },
9731 { TEE_I64_S, TEE_I64 },
9732 { TEE_V128_S, TEE_V128 },
9733 { THROW_REF_S, THROW_REF },
9734 { THROW_S, THROW },
9735 { TRUNC_F16x8_S, TRUNC_F16x8 },
9736 { TRUNC_F32_S, TRUNC_F32 },
9737 { TRUNC_F32x4_S, TRUNC_F32x4 },
9738 { TRUNC_F64_S, TRUNC_F64 },
9739 { TRUNC_F64x2_S, TRUNC_F64x2 },
9740 { TRY_S, TRY },
9741 { TRY_TABLE_S, TRY_TABLE },
9742 { UNREACHABLE_S, UNREACHABLE },
9743 { XOR_I32_S, XOR_I32 },
9744 { XOR_I64_S, XOR_I64 },
9745 { XOR_S, XOR },
9746 { anonymous_8818MEMORY_GROW_A32_S, anonymous_8818MEMORY_GROW_A32 },
9747 { anonymous_8818MEMORY_SIZE_A32_S, anonymous_8818MEMORY_SIZE_A32 },
9748 { anonymous_8819MEMORY_GROW_A64_S, anonymous_8819MEMORY_GROW_A64 },
9749 { anonymous_8819MEMORY_SIZE_A64_S, anonymous_8819MEMORY_SIZE_A64 },
9750 { convert_low_s_F64x2_S, convert_low_s_F64x2 },
9751 { convert_low_u_F64x2_S, convert_low_u_F64x2 },
9752 { demote_zero_F32x4_S, demote_zero_F32x4 },
9753 { extend_high_s_I16x8_S, extend_high_s_I16x8 },
9754 { extend_high_s_I32x4_S, extend_high_s_I32x4 },
9755 { extend_high_s_I64x2_S, extend_high_s_I64x2 },
9756 { extend_high_u_I16x8_S, extend_high_u_I16x8 },
9757 { extend_high_u_I32x4_S, extend_high_u_I32x4 },
9758 { extend_high_u_I64x2_S, extend_high_u_I64x2 },
9759 { extend_low_s_I16x8_S, extend_low_s_I16x8 },
9760 { extend_low_s_I32x4_S, extend_low_s_I32x4 },
9761 { extend_low_s_I64x2_S, extend_low_s_I64x2 },
9762 { extend_low_u_I16x8_S, extend_low_u_I16x8 },
9763 { extend_low_u_I32x4_S, extend_low_u_I32x4 },
9764 { extend_low_u_I64x2_S, extend_low_u_I64x2 },
9765 { fp_to_sint_I16x8_S, fp_to_sint_I16x8 },
9766 { fp_to_sint_I32x4_S, fp_to_sint_I32x4 },
9767 { fp_to_uint_I16x8_S, fp_to_uint_I16x8 },
9768 { fp_to_uint_I32x4_S, fp_to_uint_I32x4 },
9769 { int_wasm_extadd_pairwise_signed_I16x8_S, int_wasm_extadd_pairwise_signed_I16x8 },
9770 { int_wasm_extadd_pairwise_signed_I32x4_S, int_wasm_extadd_pairwise_signed_I32x4 },
9771 { int_wasm_extadd_pairwise_unsigned_I16x8_S, int_wasm_extadd_pairwise_unsigned_I16x8 },
9772 { int_wasm_extadd_pairwise_unsigned_I32x4_S, int_wasm_extadd_pairwise_unsigned_I32x4 },
9773 { int_wasm_relaxed_trunc_signed_I32x4_S, int_wasm_relaxed_trunc_signed_I32x4 },
9774 { int_wasm_relaxed_trunc_signed_zero_I32x4_S, int_wasm_relaxed_trunc_signed_zero_I32x4 },
9775 { int_wasm_relaxed_trunc_unsigned_I32x4_S, int_wasm_relaxed_trunc_unsigned_I32x4 },
9776 { int_wasm_relaxed_trunc_unsigned_zero_I32x4_S, int_wasm_relaxed_trunc_unsigned_zero_I32x4 },
9777 { promote_low_F64x2_S, promote_low_F64x2 },
9778 { sint_to_fp_F16x8_S, sint_to_fp_F16x8 },
9779 { sint_to_fp_F32x4_S, sint_to_fp_F32x4 },
9780 { trunc_sat_zero_s_I32x4_S, trunc_sat_zero_s_I32x4 },
9781 { trunc_sat_zero_u_I32x4_S, trunc_sat_zero_u_I32x4 },
9782 { uint_to_fp_F16x8_S, uint_to_fp_F16x8 },
9783 { uint_to_fp_F32x4_S, uint_to_fp_F32x4 },
9784 }; // End of Table
9785
9786 unsigned mid;
9787 unsigned start = 0;
9788 unsigned end = 815;
9789 while (start < end) {
9790 mid = start + (end - start) / 2;
9791 if (Opcode == Table[mid][0])
9792 break;
9793 if (Opcode < Table[mid][0])
9794 end = mid;
9795 else
9796 start = mid + 1;
9797 }
9798 if (start == end)
9799 return -1; // Instruction doesn't exist in this table.
9800
9801 return Table[mid][1];
9802}
9803
9804// getStackOpcode
9805LLVM_READONLY
9806int getStackOpcode(uint16_t Opcode) {
9807 using namespace WebAssembly;
9808 static constexpr uint16_t Table[][2] = {
9809 { CALL_PARAMS, CALL_PARAMS_S },
9810 { CALL_RESULTS, CALL_RESULTS_S },
9811 { CATCHRET, CATCHRET_S },
9812 { CLEANUPRET, CLEANUPRET_S },
9813 { COMPILER_FENCE, COMPILER_FENCE_S },
9814 { RET_CALL_RESULTS, RET_CALL_RESULTS_S },
9815 { ABS_F16x8, ABS_F16x8_S },
9816 { ABS_F32, ABS_F32_S },
9817 { ABS_F32x4, ABS_F32x4_S },
9818 { ABS_F64, ABS_F64_S },
9819 { ABS_F64x2, ABS_F64x2_S },
9820 { ABS_I16x8, ABS_I16x8_S },
9821 { ABS_I32x4, ABS_I32x4_S },
9822 { ABS_I64x2, ABS_I64x2_S },
9823 { ABS_I8x16, ABS_I8x16_S },
9824 { ADD_F16x8, ADD_F16x8_S },
9825 { ADD_F32, ADD_F32_S },
9826 { ADD_F32x4, ADD_F32x4_S },
9827 { ADD_F64, ADD_F64_S },
9828 { ADD_F64x2, ADD_F64x2_S },
9829 { ADD_I16x8, ADD_I16x8_S },
9830 { ADD_I32, ADD_I32_S },
9831 { ADD_I32x4, ADD_I32x4_S },
9832 { ADD_I64, ADD_I64_S },
9833 { ADD_I64x2, ADD_I64x2_S },
9834 { ADD_I8x16, ADD_I8x16_S },
9835 { ADD_SAT_S_I16x8, ADD_SAT_S_I16x8_S },
9836 { ADD_SAT_S_I8x16, ADD_SAT_S_I8x16_S },
9837 { ADD_SAT_U_I16x8, ADD_SAT_U_I16x8_S },
9838 { ADD_SAT_U_I8x16, ADD_SAT_U_I8x16_S },
9839 { ADJCALLSTACKDOWN, ADJCALLSTACKDOWN_S },
9840 { ADJCALLSTACKUP, ADJCALLSTACKUP_S },
9841 { ALLTRUE_I16x8, ALLTRUE_I16x8_S },
9842 { ALLTRUE_I32x4, ALLTRUE_I32x4_S },
9843 { ALLTRUE_I64x2, ALLTRUE_I64x2_S },
9844 { ALLTRUE_I8x16, ALLTRUE_I8x16_S },
9845 { AND, AND_S },
9846 { ANDNOT, ANDNOT_S },
9847 { AND_I32, AND_I32_S },
9848 { AND_I64, AND_I64_S },
9849 { ANYTRUE, ANYTRUE_S },
9850 { ARGUMENT_exnref, ARGUMENT_exnref_S },
9851 { ARGUMENT_externref, ARGUMENT_externref_S },
9852 { ARGUMENT_f32, ARGUMENT_f32_S },
9853 { ARGUMENT_f64, ARGUMENT_f64_S },
9854 { ARGUMENT_funcref, ARGUMENT_funcref_S },
9855 { ARGUMENT_i32, ARGUMENT_i32_S },
9856 { ARGUMENT_i64, ARGUMENT_i64_S },
9857 { ARGUMENT_v16i8, ARGUMENT_v16i8_S },
9858 { ARGUMENT_v2f64, ARGUMENT_v2f64_S },
9859 { ARGUMENT_v2i64, ARGUMENT_v2i64_S },
9860 { ARGUMENT_v4f32, ARGUMENT_v4f32_S },
9861 { ARGUMENT_v4i32, ARGUMENT_v4i32_S },
9862 { ARGUMENT_v8f16, ARGUMENT_v8f16_S },
9863 { ARGUMENT_v8i16, ARGUMENT_v8i16_S },
9864 { ATOMIC_FENCE, ATOMIC_FENCE_S },
9865 { ATOMIC_LOAD16_U_I32_A32, ATOMIC_LOAD16_U_I32_A32_S },
9866 { ATOMIC_LOAD16_U_I32_A64, ATOMIC_LOAD16_U_I32_A64_S },
9867 { ATOMIC_LOAD16_U_I64_A32, ATOMIC_LOAD16_U_I64_A32_S },
9868 { ATOMIC_LOAD16_U_I64_A64, ATOMIC_LOAD16_U_I64_A64_S },
9869 { ATOMIC_LOAD32_U_I64_A32, ATOMIC_LOAD32_U_I64_A32_S },
9870 { ATOMIC_LOAD32_U_I64_A64, ATOMIC_LOAD32_U_I64_A64_S },
9871 { ATOMIC_LOAD8_U_I32_A32, ATOMIC_LOAD8_U_I32_A32_S },
9872 { ATOMIC_LOAD8_U_I32_A64, ATOMIC_LOAD8_U_I32_A64_S },
9873 { ATOMIC_LOAD8_U_I64_A32, ATOMIC_LOAD8_U_I64_A32_S },
9874 { ATOMIC_LOAD8_U_I64_A64, ATOMIC_LOAD8_U_I64_A64_S },
9875 { ATOMIC_LOAD_I32_A32, ATOMIC_LOAD_I32_A32_S },
9876 { ATOMIC_LOAD_I32_A64, ATOMIC_LOAD_I32_A64_S },
9877 { ATOMIC_LOAD_I64_A32, ATOMIC_LOAD_I64_A32_S },
9878 { ATOMIC_LOAD_I64_A64, ATOMIC_LOAD_I64_A64_S },
9879 { ATOMIC_RMW16_U_ADD_I32_A32, ATOMIC_RMW16_U_ADD_I32_A32_S },
9880 { ATOMIC_RMW16_U_ADD_I32_A64, ATOMIC_RMW16_U_ADD_I32_A64_S },
9881 { ATOMIC_RMW16_U_ADD_I64_A32, ATOMIC_RMW16_U_ADD_I64_A32_S },
9882 { ATOMIC_RMW16_U_ADD_I64_A64, ATOMIC_RMW16_U_ADD_I64_A64_S },
9883 { ATOMIC_RMW16_U_AND_I32_A32, ATOMIC_RMW16_U_AND_I32_A32_S },
9884 { ATOMIC_RMW16_U_AND_I32_A64, ATOMIC_RMW16_U_AND_I32_A64_S },
9885 { ATOMIC_RMW16_U_AND_I64_A32, ATOMIC_RMW16_U_AND_I64_A32_S },
9886 { ATOMIC_RMW16_U_AND_I64_A64, ATOMIC_RMW16_U_AND_I64_A64_S },
9887 { ATOMIC_RMW16_U_CMPXCHG_I32_A32, ATOMIC_RMW16_U_CMPXCHG_I32_A32_S },
9888 { ATOMIC_RMW16_U_CMPXCHG_I32_A64, ATOMIC_RMW16_U_CMPXCHG_I32_A64_S },
9889 { ATOMIC_RMW16_U_CMPXCHG_I64_A32, ATOMIC_RMW16_U_CMPXCHG_I64_A32_S },
9890 { ATOMIC_RMW16_U_CMPXCHG_I64_A64, ATOMIC_RMW16_U_CMPXCHG_I64_A64_S },
9891 { ATOMIC_RMW16_U_OR_I32_A32, ATOMIC_RMW16_U_OR_I32_A32_S },
9892 { ATOMIC_RMW16_U_OR_I32_A64, ATOMIC_RMW16_U_OR_I32_A64_S },
9893 { ATOMIC_RMW16_U_OR_I64_A32, ATOMIC_RMW16_U_OR_I64_A32_S },
9894 { ATOMIC_RMW16_U_OR_I64_A64, ATOMIC_RMW16_U_OR_I64_A64_S },
9895 { ATOMIC_RMW16_U_SUB_I32_A32, ATOMIC_RMW16_U_SUB_I32_A32_S },
9896 { ATOMIC_RMW16_U_SUB_I32_A64, ATOMIC_RMW16_U_SUB_I32_A64_S },
9897 { ATOMIC_RMW16_U_SUB_I64_A32, ATOMIC_RMW16_U_SUB_I64_A32_S },
9898 { ATOMIC_RMW16_U_SUB_I64_A64, ATOMIC_RMW16_U_SUB_I64_A64_S },
9899 { ATOMIC_RMW16_U_XCHG_I32_A32, ATOMIC_RMW16_U_XCHG_I32_A32_S },
9900 { ATOMIC_RMW16_U_XCHG_I32_A64, ATOMIC_RMW16_U_XCHG_I32_A64_S },
9901 { ATOMIC_RMW16_U_XCHG_I64_A32, ATOMIC_RMW16_U_XCHG_I64_A32_S },
9902 { ATOMIC_RMW16_U_XCHG_I64_A64, ATOMIC_RMW16_U_XCHG_I64_A64_S },
9903 { ATOMIC_RMW16_U_XOR_I32_A32, ATOMIC_RMW16_U_XOR_I32_A32_S },
9904 { ATOMIC_RMW16_U_XOR_I32_A64, ATOMIC_RMW16_U_XOR_I32_A64_S },
9905 { ATOMIC_RMW16_U_XOR_I64_A32, ATOMIC_RMW16_U_XOR_I64_A32_S },
9906 { ATOMIC_RMW16_U_XOR_I64_A64, ATOMIC_RMW16_U_XOR_I64_A64_S },
9907 { ATOMIC_RMW32_U_ADD_I64_A32, ATOMIC_RMW32_U_ADD_I64_A32_S },
9908 { ATOMIC_RMW32_U_ADD_I64_A64, ATOMIC_RMW32_U_ADD_I64_A64_S },
9909 { ATOMIC_RMW32_U_AND_I64_A32, ATOMIC_RMW32_U_AND_I64_A32_S },
9910 { ATOMIC_RMW32_U_AND_I64_A64, ATOMIC_RMW32_U_AND_I64_A64_S },
9911 { ATOMIC_RMW32_U_CMPXCHG_I64_A32, ATOMIC_RMW32_U_CMPXCHG_I64_A32_S },
9912 { ATOMIC_RMW32_U_CMPXCHG_I64_A64, ATOMIC_RMW32_U_CMPXCHG_I64_A64_S },
9913 { ATOMIC_RMW32_U_OR_I64_A32, ATOMIC_RMW32_U_OR_I64_A32_S },
9914 { ATOMIC_RMW32_U_OR_I64_A64, ATOMIC_RMW32_U_OR_I64_A64_S },
9915 { ATOMIC_RMW32_U_SUB_I64_A32, ATOMIC_RMW32_U_SUB_I64_A32_S },
9916 { ATOMIC_RMW32_U_SUB_I64_A64, ATOMIC_RMW32_U_SUB_I64_A64_S },
9917 { ATOMIC_RMW32_U_XCHG_I64_A32, ATOMIC_RMW32_U_XCHG_I64_A32_S },
9918 { ATOMIC_RMW32_U_XCHG_I64_A64, ATOMIC_RMW32_U_XCHG_I64_A64_S },
9919 { ATOMIC_RMW32_U_XOR_I64_A32, ATOMIC_RMW32_U_XOR_I64_A32_S },
9920 { ATOMIC_RMW32_U_XOR_I64_A64, ATOMIC_RMW32_U_XOR_I64_A64_S },
9921 { ATOMIC_RMW8_U_ADD_I32_A32, ATOMIC_RMW8_U_ADD_I32_A32_S },
9922 { ATOMIC_RMW8_U_ADD_I32_A64, ATOMIC_RMW8_U_ADD_I32_A64_S },
9923 { ATOMIC_RMW8_U_ADD_I64_A32, ATOMIC_RMW8_U_ADD_I64_A32_S },
9924 { ATOMIC_RMW8_U_ADD_I64_A64, ATOMIC_RMW8_U_ADD_I64_A64_S },
9925 { ATOMIC_RMW8_U_AND_I32_A32, ATOMIC_RMW8_U_AND_I32_A32_S },
9926 { ATOMIC_RMW8_U_AND_I32_A64, ATOMIC_RMW8_U_AND_I32_A64_S },
9927 { ATOMIC_RMW8_U_AND_I64_A32, ATOMIC_RMW8_U_AND_I64_A32_S },
9928 { ATOMIC_RMW8_U_AND_I64_A64, ATOMIC_RMW8_U_AND_I64_A64_S },
9929 { ATOMIC_RMW8_U_CMPXCHG_I32_A32, ATOMIC_RMW8_U_CMPXCHG_I32_A32_S },
9930 { ATOMIC_RMW8_U_CMPXCHG_I32_A64, ATOMIC_RMW8_U_CMPXCHG_I32_A64_S },
9931 { ATOMIC_RMW8_U_CMPXCHG_I64_A32, ATOMIC_RMW8_U_CMPXCHG_I64_A32_S },
9932 { ATOMIC_RMW8_U_CMPXCHG_I64_A64, ATOMIC_RMW8_U_CMPXCHG_I64_A64_S },
9933 { ATOMIC_RMW8_U_OR_I32_A32, ATOMIC_RMW8_U_OR_I32_A32_S },
9934 { ATOMIC_RMW8_U_OR_I32_A64, ATOMIC_RMW8_U_OR_I32_A64_S },
9935 { ATOMIC_RMW8_U_OR_I64_A32, ATOMIC_RMW8_U_OR_I64_A32_S },
9936 { ATOMIC_RMW8_U_OR_I64_A64, ATOMIC_RMW8_U_OR_I64_A64_S },
9937 { ATOMIC_RMW8_U_SUB_I32_A32, ATOMIC_RMW8_U_SUB_I32_A32_S },
9938 { ATOMIC_RMW8_U_SUB_I32_A64, ATOMIC_RMW8_U_SUB_I32_A64_S },
9939 { ATOMIC_RMW8_U_SUB_I64_A32, ATOMIC_RMW8_U_SUB_I64_A32_S },
9940 { ATOMIC_RMW8_U_SUB_I64_A64, ATOMIC_RMW8_U_SUB_I64_A64_S },
9941 { ATOMIC_RMW8_U_XCHG_I32_A32, ATOMIC_RMW8_U_XCHG_I32_A32_S },
9942 { ATOMIC_RMW8_U_XCHG_I32_A64, ATOMIC_RMW8_U_XCHG_I32_A64_S },
9943 { ATOMIC_RMW8_U_XCHG_I64_A32, ATOMIC_RMW8_U_XCHG_I64_A32_S },
9944 { ATOMIC_RMW8_U_XCHG_I64_A64, ATOMIC_RMW8_U_XCHG_I64_A64_S },
9945 { ATOMIC_RMW8_U_XOR_I32_A32, ATOMIC_RMW8_U_XOR_I32_A32_S },
9946 { ATOMIC_RMW8_U_XOR_I32_A64, ATOMIC_RMW8_U_XOR_I32_A64_S },
9947 { ATOMIC_RMW8_U_XOR_I64_A32, ATOMIC_RMW8_U_XOR_I64_A32_S },
9948 { ATOMIC_RMW8_U_XOR_I64_A64, ATOMIC_RMW8_U_XOR_I64_A64_S },
9949 { ATOMIC_RMW_ADD_I32_A32, ATOMIC_RMW_ADD_I32_A32_S },
9950 { ATOMIC_RMW_ADD_I32_A64, ATOMIC_RMW_ADD_I32_A64_S },
9951 { ATOMIC_RMW_ADD_I64_A32, ATOMIC_RMW_ADD_I64_A32_S },
9952 { ATOMIC_RMW_ADD_I64_A64, ATOMIC_RMW_ADD_I64_A64_S },
9953 { ATOMIC_RMW_AND_I32_A32, ATOMIC_RMW_AND_I32_A32_S },
9954 { ATOMIC_RMW_AND_I32_A64, ATOMIC_RMW_AND_I32_A64_S },
9955 { ATOMIC_RMW_AND_I64_A32, ATOMIC_RMW_AND_I64_A32_S },
9956 { ATOMIC_RMW_AND_I64_A64, ATOMIC_RMW_AND_I64_A64_S },
9957 { ATOMIC_RMW_CMPXCHG_I32_A32, ATOMIC_RMW_CMPXCHG_I32_A32_S },
9958 { ATOMIC_RMW_CMPXCHG_I32_A64, ATOMIC_RMW_CMPXCHG_I32_A64_S },
9959 { ATOMIC_RMW_CMPXCHG_I64_A32, ATOMIC_RMW_CMPXCHG_I64_A32_S },
9960 { ATOMIC_RMW_CMPXCHG_I64_A64, ATOMIC_RMW_CMPXCHG_I64_A64_S },
9961 { ATOMIC_RMW_OR_I32_A32, ATOMIC_RMW_OR_I32_A32_S },
9962 { ATOMIC_RMW_OR_I32_A64, ATOMIC_RMW_OR_I32_A64_S },
9963 { ATOMIC_RMW_OR_I64_A32, ATOMIC_RMW_OR_I64_A32_S },
9964 { ATOMIC_RMW_OR_I64_A64, ATOMIC_RMW_OR_I64_A64_S },
9965 { ATOMIC_RMW_SUB_I32_A32, ATOMIC_RMW_SUB_I32_A32_S },
9966 { ATOMIC_RMW_SUB_I32_A64, ATOMIC_RMW_SUB_I32_A64_S },
9967 { ATOMIC_RMW_SUB_I64_A32, ATOMIC_RMW_SUB_I64_A32_S },
9968 { ATOMIC_RMW_SUB_I64_A64, ATOMIC_RMW_SUB_I64_A64_S },
9969 { ATOMIC_RMW_XCHG_I32_A32, ATOMIC_RMW_XCHG_I32_A32_S },
9970 { ATOMIC_RMW_XCHG_I32_A64, ATOMIC_RMW_XCHG_I32_A64_S },
9971 { ATOMIC_RMW_XCHG_I64_A32, ATOMIC_RMW_XCHG_I64_A32_S },
9972 { ATOMIC_RMW_XCHG_I64_A64, ATOMIC_RMW_XCHG_I64_A64_S },
9973 { ATOMIC_RMW_XOR_I32_A32, ATOMIC_RMW_XOR_I32_A32_S },
9974 { ATOMIC_RMW_XOR_I32_A64, ATOMIC_RMW_XOR_I32_A64_S },
9975 { ATOMIC_RMW_XOR_I64_A32, ATOMIC_RMW_XOR_I64_A32_S },
9976 { ATOMIC_RMW_XOR_I64_A64, ATOMIC_RMW_XOR_I64_A64_S },
9977 { ATOMIC_STORE16_I32_A32, ATOMIC_STORE16_I32_A32_S },
9978 { ATOMIC_STORE16_I32_A64, ATOMIC_STORE16_I32_A64_S },
9979 { ATOMIC_STORE16_I64_A32, ATOMIC_STORE16_I64_A32_S },
9980 { ATOMIC_STORE16_I64_A64, ATOMIC_STORE16_I64_A64_S },
9981 { ATOMIC_STORE32_I64_A32, ATOMIC_STORE32_I64_A32_S },
9982 { ATOMIC_STORE32_I64_A64, ATOMIC_STORE32_I64_A64_S },
9983 { ATOMIC_STORE8_I32_A32, ATOMIC_STORE8_I32_A32_S },
9984 { ATOMIC_STORE8_I32_A64, ATOMIC_STORE8_I32_A64_S },
9985 { ATOMIC_STORE8_I64_A32, ATOMIC_STORE8_I64_A32_S },
9986 { ATOMIC_STORE8_I64_A64, ATOMIC_STORE8_I64_A64_S },
9987 { ATOMIC_STORE_I32_A32, ATOMIC_STORE_I32_A32_S },
9988 { ATOMIC_STORE_I32_A64, ATOMIC_STORE_I32_A64_S },
9989 { ATOMIC_STORE_I64_A32, ATOMIC_STORE_I64_A32_S },
9990 { ATOMIC_STORE_I64_A64, ATOMIC_STORE_I64_A64_S },
9991 { AVGR_U_I16x8, AVGR_U_I16x8_S },
9992 { AVGR_U_I8x16, AVGR_U_I8x16_S },
9993 { BITMASK_I16x8, BITMASK_I16x8_S },
9994 { BITMASK_I32x4, BITMASK_I32x4_S },
9995 { BITMASK_I64x2, BITMASK_I64x2_S },
9996 { BITMASK_I8x16, BITMASK_I8x16_S },
9997 { BITSELECT, BITSELECT_S },
9998 { BLOCK, BLOCK_S },
9999 { BR, BR_S },
10000 { BR_IF, BR_IF_S },
10001 { BR_TABLE_I32, BR_TABLE_I32_S },
10002 { BR_TABLE_I64, BR_TABLE_I64_S },
10003 { BR_UNLESS, BR_UNLESS_S },
10004 { CALL, CALL_S },
10005 { CALL_INDIRECT, CALL_INDIRECT_S },
10006 { CATCH, CATCH_S },
10007 { CATCH_ALL, CATCH_ALL_S },
10008 { CATCH_ALL_LEGACY, CATCH_ALL_LEGACY_S },
10009 { CATCH_ALL_REF, CATCH_ALL_REF_S },
10010 { CATCH_LEGACY, CATCH_LEGACY_S },
10011 { CATCH_REF, CATCH_REF_S },
10012 { CEIL_F16x8, CEIL_F16x8_S },
10013 { CEIL_F32, CEIL_F32_S },
10014 { CEIL_F32x4, CEIL_F32x4_S },
10015 { CEIL_F64, CEIL_F64_S },
10016 { CEIL_F64x2, CEIL_F64x2_S },
10017 { CLZ_I32, CLZ_I32_S },
10018 { CLZ_I64, CLZ_I64_S },
10019 { CONST_F32, CONST_F32_S },
10020 { CONST_F64, CONST_F64_S },
10021 { CONST_I32, CONST_I32_S },
10022 { CONST_I64, CONST_I64_S },
10023 { CONST_V128_F32x4, CONST_V128_F32x4_S },
10024 { CONST_V128_F64x2, CONST_V128_F64x2_S },
10025 { CONST_V128_I16x8, CONST_V128_I16x8_S },
10026 { CONST_V128_I32x4, CONST_V128_I32x4_S },
10027 { CONST_V128_I64x2, CONST_V128_I64x2_S },
10028 { CONST_V128_I8x16, CONST_V128_I8x16_S },
10029 { COPYSIGN_F32, COPYSIGN_F32_S },
10030 { COPYSIGN_F64, COPYSIGN_F64_S },
10031 { COPY_EXNREF, COPY_EXNREF_S },
10032 { COPY_EXTERNREF, COPY_EXTERNREF_S },
10033 { COPY_F32, COPY_F32_S },
10034 { COPY_F64, COPY_F64_S },
10035 { COPY_FUNCREF, COPY_FUNCREF_S },
10036 { COPY_I32, COPY_I32_S },
10037 { COPY_I64, COPY_I64_S },
10038 { COPY_V128, COPY_V128_S },
10039 { CTZ_I32, CTZ_I32_S },
10040 { CTZ_I64, CTZ_I64_S },
10041 { DATA_DROP, DATA_DROP_S },
10042 { DEBUG_UNREACHABLE, DEBUG_UNREACHABLE_S },
10043 { DELEGATE, DELEGATE_S },
10044 { DIV_F16x8, DIV_F16x8_S },
10045 { DIV_F32, DIV_F32_S },
10046 { DIV_F32x4, DIV_F32x4_S },
10047 { DIV_F64, DIV_F64_S },
10048 { DIV_F64x2, DIV_F64x2_S },
10049 { DIV_S_I32, DIV_S_I32_S },
10050 { DIV_S_I64, DIV_S_I64_S },
10051 { DIV_U_I32, DIV_U_I32_S },
10052 { DIV_U_I64, DIV_U_I64_S },
10053 { DOT, DOT_S },
10054 { DROP_EXNREF, DROP_EXNREF_S },
10055 { DROP_EXTERNREF, DROP_EXTERNREF_S },
10056 { DROP_F32, DROP_F32_S },
10057 { DROP_F64, DROP_F64_S },
10058 { DROP_FUNCREF, DROP_FUNCREF_S },
10059 { DROP_I32, DROP_I32_S },
10060 { DROP_I64, DROP_I64_S },
10061 { DROP_V128, DROP_V128_S },
10062 { ELSE, ELSE_S },
10063 { END, END_S },
10064 { END_BLOCK, END_BLOCK_S },
10065 { END_FUNCTION, END_FUNCTION_S },
10066 { END_IF, END_IF_S },
10067 { END_LOOP, END_LOOP_S },
10068 { END_TRY, END_TRY_S },
10069 { END_TRY_TABLE, END_TRY_TABLE_S },
10070 { EQZ_I32, EQZ_I32_S },
10071 { EQZ_I64, EQZ_I64_S },
10072 { EQ_F16x8, EQ_F16x8_S },
10073 { EQ_F32, EQ_F32_S },
10074 { EQ_F32x4, EQ_F32x4_S },
10075 { EQ_F64, EQ_F64_S },
10076 { EQ_F64x2, EQ_F64x2_S },
10077 { EQ_I16x8, EQ_I16x8_S },
10078 { EQ_I32, EQ_I32_S },
10079 { EQ_I32x4, EQ_I32x4_S },
10080 { EQ_I64, EQ_I64_S },
10081 { EQ_I64x2, EQ_I64x2_S },
10082 { EQ_I8x16, EQ_I8x16_S },
10083 { EXTMUL_HIGH_S_I16x8, EXTMUL_HIGH_S_I16x8_S },
10084 { EXTMUL_HIGH_S_I32x4, EXTMUL_HIGH_S_I32x4_S },
10085 { EXTMUL_HIGH_S_I64x2, EXTMUL_HIGH_S_I64x2_S },
10086 { EXTMUL_HIGH_U_I16x8, EXTMUL_HIGH_U_I16x8_S },
10087 { EXTMUL_HIGH_U_I32x4, EXTMUL_HIGH_U_I32x4_S },
10088 { EXTMUL_HIGH_U_I64x2, EXTMUL_HIGH_U_I64x2_S },
10089 { EXTMUL_LOW_S_I16x8, EXTMUL_LOW_S_I16x8_S },
10090 { EXTMUL_LOW_S_I32x4, EXTMUL_LOW_S_I32x4_S },
10091 { EXTMUL_LOW_S_I64x2, EXTMUL_LOW_S_I64x2_S },
10092 { EXTMUL_LOW_U_I16x8, EXTMUL_LOW_U_I16x8_S },
10093 { EXTMUL_LOW_U_I32x4, EXTMUL_LOW_U_I32x4_S },
10094 { EXTMUL_LOW_U_I64x2, EXTMUL_LOW_U_I64x2_S },
10095 { EXTRACT_LANE_F16x8, EXTRACT_LANE_F16x8_S },
10096 { EXTRACT_LANE_F32x4, EXTRACT_LANE_F32x4_S },
10097 { EXTRACT_LANE_F64x2, EXTRACT_LANE_F64x2_S },
10098 { EXTRACT_LANE_I16x8_s, EXTRACT_LANE_I16x8_s_S },
10099 { EXTRACT_LANE_I16x8_u, EXTRACT_LANE_I16x8_u_S },
10100 { EXTRACT_LANE_I32x4, EXTRACT_LANE_I32x4_S },
10101 { EXTRACT_LANE_I64x2, EXTRACT_LANE_I64x2_S },
10102 { EXTRACT_LANE_I8x16_s, EXTRACT_LANE_I8x16_s_S },
10103 { EXTRACT_LANE_I8x16_u, EXTRACT_LANE_I8x16_u_S },
10104 { F32_CONVERT_S_I32, F32_CONVERT_S_I32_S },
10105 { F32_CONVERT_S_I64, F32_CONVERT_S_I64_S },
10106 { F32_CONVERT_U_I32, F32_CONVERT_U_I32_S },
10107 { F32_CONVERT_U_I64, F32_CONVERT_U_I64_S },
10108 { F32_DEMOTE_F64, F32_DEMOTE_F64_S },
10109 { F32_REINTERPRET_I32, F32_REINTERPRET_I32_S },
10110 { F64_CONVERT_S_I32, F64_CONVERT_S_I32_S },
10111 { F64_CONVERT_S_I64, F64_CONVERT_S_I64_S },
10112 { F64_CONVERT_U_I32, F64_CONVERT_U_I32_S },
10113 { F64_CONVERT_U_I64, F64_CONVERT_U_I64_S },
10114 { F64_PROMOTE_F32, F64_PROMOTE_F32_S },
10115 { F64_REINTERPRET_I64, F64_REINTERPRET_I64_S },
10116 { FALLTHROUGH_RETURN, FALLTHROUGH_RETURN_S },
10117 { FLOOR_F16x8, FLOOR_F16x8_S },
10118 { FLOOR_F32, FLOOR_F32_S },
10119 { FLOOR_F32x4, FLOOR_F32x4_S },
10120 { FLOOR_F64, FLOOR_F64_S },
10121 { FLOOR_F64x2, FLOOR_F64x2_S },
10122 { FP_TO_SINT_I32_F32, FP_TO_SINT_I32_F32_S },
10123 { FP_TO_SINT_I32_F64, FP_TO_SINT_I32_F64_S },
10124 { FP_TO_SINT_I64_F32, FP_TO_SINT_I64_F32_S },
10125 { FP_TO_SINT_I64_F64, FP_TO_SINT_I64_F64_S },
10126 { FP_TO_UINT_I32_F32, FP_TO_UINT_I32_F32_S },
10127 { FP_TO_UINT_I32_F64, FP_TO_UINT_I32_F64_S },
10128 { FP_TO_UINT_I64_F32, FP_TO_UINT_I64_F32_S },
10129 { FP_TO_UINT_I64_F64, FP_TO_UINT_I64_F64_S },
10130 { GE_F16x8, GE_F16x8_S },
10131 { GE_F32, GE_F32_S },
10132 { GE_F32x4, GE_F32x4_S },
10133 { GE_F64, GE_F64_S },
10134 { GE_F64x2, GE_F64x2_S },
10135 { GE_S_I16x8, GE_S_I16x8_S },
10136 { GE_S_I32, GE_S_I32_S },
10137 { GE_S_I32x4, GE_S_I32x4_S },
10138 { GE_S_I64, GE_S_I64_S },
10139 { GE_S_I64x2, GE_S_I64x2_S },
10140 { GE_S_I8x16, GE_S_I8x16_S },
10141 { GE_U_I16x8, GE_U_I16x8_S },
10142 { GE_U_I32, GE_U_I32_S },
10143 { GE_U_I32x4, GE_U_I32x4_S },
10144 { GE_U_I64, GE_U_I64_S },
10145 { GE_U_I8x16, GE_U_I8x16_S },
10146 { GLOBAL_GET_EXNREF, GLOBAL_GET_EXNREF_S },
10147 { GLOBAL_GET_EXTERNREF, GLOBAL_GET_EXTERNREF_S },
10148 { GLOBAL_GET_F32, GLOBAL_GET_F32_S },
10149 { GLOBAL_GET_F64, GLOBAL_GET_F64_S },
10150 { GLOBAL_GET_FUNCREF, GLOBAL_GET_FUNCREF_S },
10151 { GLOBAL_GET_I32, GLOBAL_GET_I32_S },
10152 { GLOBAL_GET_I64, GLOBAL_GET_I64_S },
10153 { GLOBAL_GET_V128, GLOBAL_GET_V128_S },
10154 { GLOBAL_SET_EXNREF, GLOBAL_SET_EXNREF_S },
10155 { GLOBAL_SET_EXTERNREF, GLOBAL_SET_EXTERNREF_S },
10156 { GLOBAL_SET_F32, GLOBAL_SET_F32_S },
10157 { GLOBAL_SET_F64, GLOBAL_SET_F64_S },
10158 { GLOBAL_SET_FUNCREF, GLOBAL_SET_FUNCREF_S },
10159 { GLOBAL_SET_I32, GLOBAL_SET_I32_S },
10160 { GLOBAL_SET_I64, GLOBAL_SET_I64_S },
10161 { GLOBAL_SET_V128, GLOBAL_SET_V128_S },
10162 { GT_F16x8, GT_F16x8_S },
10163 { GT_F32, GT_F32_S },
10164 { GT_F32x4, GT_F32x4_S },
10165 { GT_F64, GT_F64_S },
10166 { GT_F64x2, GT_F64x2_S },
10167 { GT_S_I16x8, GT_S_I16x8_S },
10168 { GT_S_I32, GT_S_I32_S },
10169 { GT_S_I32x4, GT_S_I32x4_S },
10170 { GT_S_I64, GT_S_I64_S },
10171 { GT_S_I64x2, GT_S_I64x2_S },
10172 { GT_S_I8x16, GT_S_I8x16_S },
10173 { GT_U_I16x8, GT_U_I16x8_S },
10174 { GT_U_I32, GT_U_I32_S },
10175 { GT_U_I32x4, GT_U_I32x4_S },
10176 { GT_U_I64, GT_U_I64_S },
10177 { GT_U_I8x16, GT_U_I8x16_S },
10178 { I32_EXTEND16_S_I32, I32_EXTEND16_S_I32_S },
10179 { I32_EXTEND8_S_I32, I32_EXTEND8_S_I32_S },
10180 { I32_REINTERPRET_F32, I32_REINTERPRET_F32_S },
10181 { I32_TRUNC_S_F32, I32_TRUNC_S_F32_S },
10182 { I32_TRUNC_S_F64, I32_TRUNC_S_F64_S },
10183 { I32_TRUNC_S_SAT_F32, I32_TRUNC_S_SAT_F32_S },
10184 { I32_TRUNC_S_SAT_F64, I32_TRUNC_S_SAT_F64_S },
10185 { I32_TRUNC_U_F32, I32_TRUNC_U_F32_S },
10186 { I32_TRUNC_U_F64, I32_TRUNC_U_F64_S },
10187 { I32_TRUNC_U_SAT_F32, I32_TRUNC_U_SAT_F32_S },
10188 { I32_TRUNC_U_SAT_F64, I32_TRUNC_U_SAT_F64_S },
10189 { I32_WRAP_I64, I32_WRAP_I64_S },
10190 { I64_ADD128, I64_ADD128_S },
10191 { I64_EXTEND16_S_I64, I64_EXTEND16_S_I64_S },
10192 { I64_EXTEND32_S_I64, I64_EXTEND32_S_I64_S },
10193 { I64_EXTEND8_S_I64, I64_EXTEND8_S_I64_S },
10194 { I64_EXTEND_S_I32, I64_EXTEND_S_I32_S },
10195 { I64_EXTEND_U_I32, I64_EXTEND_U_I32_S },
10196 { I64_MUL_WIDE_S, I64_MUL_WIDE_S_S },
10197 { I64_MUL_WIDE_U, I64_MUL_WIDE_U_S },
10198 { I64_REINTERPRET_F64, I64_REINTERPRET_F64_S },
10199 { I64_SUB128, I64_SUB128_S },
10200 { I64_TRUNC_S_F32, I64_TRUNC_S_F32_S },
10201 { I64_TRUNC_S_F64, I64_TRUNC_S_F64_S },
10202 { I64_TRUNC_S_SAT_F32, I64_TRUNC_S_SAT_F32_S },
10203 { I64_TRUNC_S_SAT_F64, I64_TRUNC_S_SAT_F64_S },
10204 { I64_TRUNC_U_F32, I64_TRUNC_U_F32_S },
10205 { I64_TRUNC_U_F64, I64_TRUNC_U_F64_S },
10206 { I64_TRUNC_U_SAT_F32, I64_TRUNC_U_SAT_F32_S },
10207 { I64_TRUNC_U_SAT_F64, I64_TRUNC_U_SAT_F64_S },
10208 { IF, IF_S },
10209 { LANESELECT_I16x8, LANESELECT_I16x8_S },
10210 { LANESELECT_I32x4, LANESELECT_I32x4_S },
10211 { LANESELECT_I64x2, LANESELECT_I64x2_S },
10212 { LANESELECT_I8x16, LANESELECT_I8x16_S },
10213 { LE_F16x8, LE_F16x8_S },
10214 { LE_F32, LE_F32_S },
10215 { LE_F32x4, LE_F32x4_S },
10216 { LE_F64, LE_F64_S },
10217 { LE_F64x2, LE_F64x2_S },
10218 { LE_S_I16x8, LE_S_I16x8_S },
10219 { LE_S_I32, LE_S_I32_S },
10220 { LE_S_I32x4, LE_S_I32x4_S },
10221 { LE_S_I64, LE_S_I64_S },
10222 { LE_S_I64x2, LE_S_I64x2_S },
10223 { LE_S_I8x16, LE_S_I8x16_S },
10224 { LE_U_I16x8, LE_U_I16x8_S },
10225 { LE_U_I32, LE_U_I32_S },
10226 { LE_U_I32x4, LE_U_I32x4_S },
10227 { LE_U_I64, LE_U_I64_S },
10228 { LE_U_I8x16, LE_U_I8x16_S },
10229 { LOAD16_SPLAT_A32, LOAD16_SPLAT_A32_S },
10230 { LOAD16_SPLAT_A64, LOAD16_SPLAT_A64_S },
10231 { LOAD16_S_I32_A32, LOAD16_S_I32_A32_S },
10232 { LOAD16_S_I32_A64, LOAD16_S_I32_A64_S },
10233 { LOAD16_S_I64_A32, LOAD16_S_I64_A32_S },
10234 { LOAD16_S_I64_A64, LOAD16_S_I64_A64_S },
10235 { LOAD16_U_I32_A32, LOAD16_U_I32_A32_S },
10236 { LOAD16_U_I32_A64, LOAD16_U_I32_A64_S },
10237 { LOAD16_U_I64_A32, LOAD16_U_I64_A32_S },
10238 { LOAD16_U_I64_A64, LOAD16_U_I64_A64_S },
10239 { LOAD32_SPLAT_A32, LOAD32_SPLAT_A32_S },
10240 { LOAD32_SPLAT_A64, LOAD32_SPLAT_A64_S },
10241 { LOAD32_S_I64_A32, LOAD32_S_I64_A32_S },
10242 { LOAD32_S_I64_A64, LOAD32_S_I64_A64_S },
10243 { LOAD32_U_I64_A32, LOAD32_U_I64_A32_S },
10244 { LOAD32_U_I64_A64, LOAD32_U_I64_A64_S },
10245 { LOAD64_SPLAT_A32, LOAD64_SPLAT_A32_S },
10246 { LOAD64_SPLAT_A64, LOAD64_SPLAT_A64_S },
10247 { LOAD8_SPLAT_A32, LOAD8_SPLAT_A32_S },
10248 { LOAD8_SPLAT_A64, LOAD8_SPLAT_A64_S },
10249 { LOAD8_S_I32_A32, LOAD8_S_I32_A32_S },
10250 { LOAD8_S_I32_A64, LOAD8_S_I32_A64_S },
10251 { LOAD8_S_I64_A32, LOAD8_S_I64_A32_S },
10252 { LOAD8_S_I64_A64, LOAD8_S_I64_A64_S },
10253 { LOAD8_U_I32_A32, LOAD8_U_I32_A32_S },
10254 { LOAD8_U_I32_A64, LOAD8_U_I32_A64_S },
10255 { LOAD8_U_I64_A32, LOAD8_U_I64_A32_S },
10256 { LOAD8_U_I64_A64, LOAD8_U_I64_A64_S },
10257 { LOAD_EXTEND_S_I16x8_A32, LOAD_EXTEND_S_I16x8_A32_S },
10258 { LOAD_EXTEND_S_I16x8_A64, LOAD_EXTEND_S_I16x8_A64_S },
10259 { LOAD_EXTEND_S_I32x4_A32, LOAD_EXTEND_S_I32x4_A32_S },
10260 { LOAD_EXTEND_S_I32x4_A64, LOAD_EXTEND_S_I32x4_A64_S },
10261 { LOAD_EXTEND_S_I64x2_A32, LOAD_EXTEND_S_I64x2_A32_S },
10262 { LOAD_EXTEND_S_I64x2_A64, LOAD_EXTEND_S_I64x2_A64_S },
10263 { LOAD_EXTEND_U_I16x8_A32, LOAD_EXTEND_U_I16x8_A32_S },
10264 { LOAD_EXTEND_U_I16x8_A64, LOAD_EXTEND_U_I16x8_A64_S },
10265 { LOAD_EXTEND_U_I32x4_A32, LOAD_EXTEND_U_I32x4_A32_S },
10266 { LOAD_EXTEND_U_I32x4_A64, LOAD_EXTEND_U_I32x4_A64_S },
10267 { LOAD_EXTEND_U_I64x2_A32, LOAD_EXTEND_U_I64x2_A32_S },
10268 { LOAD_EXTEND_U_I64x2_A64, LOAD_EXTEND_U_I64x2_A64_S },
10269 { LOAD_F16_F32_A32, LOAD_F16_F32_A32_S },
10270 { LOAD_F16_F32_A64, LOAD_F16_F32_A64_S },
10271 { LOAD_F32_A32, LOAD_F32_A32_S },
10272 { LOAD_F32_A64, LOAD_F32_A64_S },
10273 { LOAD_F64_A32, LOAD_F64_A32_S },
10274 { LOAD_F64_A64, LOAD_F64_A64_S },
10275 { LOAD_I32_A32, LOAD_I32_A32_S },
10276 { LOAD_I32_A64, LOAD_I32_A64_S },
10277 { LOAD_I64_A32, LOAD_I64_A32_S },
10278 { LOAD_I64_A64, LOAD_I64_A64_S },
10279 { LOAD_LANE_16_A32, LOAD_LANE_16_A32_S },
10280 { LOAD_LANE_16_A64, LOAD_LANE_16_A64_S },
10281 { LOAD_LANE_32_A32, LOAD_LANE_32_A32_S },
10282 { LOAD_LANE_32_A64, LOAD_LANE_32_A64_S },
10283 { LOAD_LANE_64_A32, LOAD_LANE_64_A32_S },
10284 { LOAD_LANE_64_A64, LOAD_LANE_64_A64_S },
10285 { LOAD_LANE_8_A32, LOAD_LANE_8_A32_S },
10286 { LOAD_LANE_8_A64, LOAD_LANE_8_A64_S },
10287 { LOAD_V128_A32, LOAD_V128_A32_S },
10288 { LOAD_V128_A64, LOAD_V128_A64_S },
10289 { LOAD_ZERO_32_A32, LOAD_ZERO_32_A32_S },
10290 { LOAD_ZERO_32_A64, LOAD_ZERO_32_A64_S },
10291 { LOAD_ZERO_64_A32, LOAD_ZERO_64_A32_S },
10292 { LOAD_ZERO_64_A64, LOAD_ZERO_64_A64_S },
10293 { LOCAL_GET_EXNREF, LOCAL_GET_EXNREF_S },
10294 { LOCAL_GET_EXTERNREF, LOCAL_GET_EXTERNREF_S },
10295 { LOCAL_GET_F32, LOCAL_GET_F32_S },
10296 { LOCAL_GET_F64, LOCAL_GET_F64_S },
10297 { LOCAL_GET_FUNCREF, LOCAL_GET_FUNCREF_S },
10298 { LOCAL_GET_I32, LOCAL_GET_I32_S },
10299 { LOCAL_GET_I64, LOCAL_GET_I64_S },
10300 { LOCAL_GET_V128, LOCAL_GET_V128_S },
10301 { LOCAL_SET_EXNREF, LOCAL_SET_EXNREF_S },
10302 { LOCAL_SET_EXTERNREF, LOCAL_SET_EXTERNREF_S },
10303 { LOCAL_SET_F32, LOCAL_SET_F32_S },
10304 { LOCAL_SET_F64, LOCAL_SET_F64_S },
10305 { LOCAL_SET_FUNCREF, LOCAL_SET_FUNCREF_S },
10306 { LOCAL_SET_I32, LOCAL_SET_I32_S },
10307 { LOCAL_SET_I64, LOCAL_SET_I64_S },
10308 { LOCAL_SET_V128, LOCAL_SET_V128_S },
10309 { LOCAL_TEE_EXNREF, LOCAL_TEE_EXNREF_S },
10310 { LOCAL_TEE_EXTERNREF, LOCAL_TEE_EXTERNREF_S },
10311 { LOCAL_TEE_F32, LOCAL_TEE_F32_S },
10312 { LOCAL_TEE_F64, LOCAL_TEE_F64_S },
10313 { LOCAL_TEE_FUNCREF, LOCAL_TEE_FUNCREF_S },
10314 { LOCAL_TEE_I32, LOCAL_TEE_I32_S },
10315 { LOCAL_TEE_I64, LOCAL_TEE_I64_S },
10316 { LOCAL_TEE_V128, LOCAL_TEE_V128_S },
10317 { LOOP, LOOP_S },
10318 { LT_F16x8, LT_F16x8_S },
10319 { LT_F32, LT_F32_S },
10320 { LT_F32x4, LT_F32x4_S },
10321 { LT_F64, LT_F64_S },
10322 { LT_F64x2, LT_F64x2_S },
10323 { LT_S_I16x8, LT_S_I16x8_S },
10324 { LT_S_I32, LT_S_I32_S },
10325 { LT_S_I32x4, LT_S_I32x4_S },
10326 { LT_S_I64, LT_S_I64_S },
10327 { LT_S_I64x2, LT_S_I64x2_S },
10328 { LT_S_I8x16, LT_S_I8x16_S },
10329 { LT_U_I16x8, LT_U_I16x8_S },
10330 { LT_U_I32, LT_U_I32_S },
10331 { LT_U_I32x4, LT_U_I32x4_S },
10332 { LT_U_I64, LT_U_I64_S },
10333 { LT_U_I8x16, LT_U_I8x16_S },
10334 { MADD_F16x8, MADD_F16x8_S },
10335 { MADD_F32x4, MADD_F32x4_S },
10336 { MADD_F64x2, MADD_F64x2_S },
10337 { MAX_F16x8, MAX_F16x8_S },
10338 { MAX_F32, MAX_F32_S },
10339 { MAX_F32x4, MAX_F32x4_S },
10340 { MAX_F64, MAX_F64_S },
10341 { MAX_F64x2, MAX_F64x2_S },
10342 { MAX_S_I16x8, MAX_S_I16x8_S },
10343 { MAX_S_I32x4, MAX_S_I32x4_S },
10344 { MAX_S_I8x16, MAX_S_I8x16_S },
10345 { MAX_U_I16x8, MAX_U_I16x8_S },
10346 { MAX_U_I32x4, MAX_U_I32x4_S },
10347 { MAX_U_I8x16, MAX_U_I8x16_S },
10348 { MEMCPY_A32, MEMCPY_A32_S },
10349 { MEMCPY_A64, MEMCPY_A64_S },
10350 { MEMORY_ATOMIC_NOTIFY_A32, MEMORY_ATOMIC_NOTIFY_A32_S },
10351 { MEMORY_ATOMIC_NOTIFY_A64, MEMORY_ATOMIC_NOTIFY_A64_S },
10352 { MEMORY_ATOMIC_WAIT32_A32, MEMORY_ATOMIC_WAIT32_A32_S },
10353 { MEMORY_ATOMIC_WAIT32_A64, MEMORY_ATOMIC_WAIT32_A64_S },
10354 { MEMORY_ATOMIC_WAIT64_A32, MEMORY_ATOMIC_WAIT64_A32_S },
10355 { MEMORY_ATOMIC_WAIT64_A64, MEMORY_ATOMIC_WAIT64_A64_S },
10356 { MEMORY_COPY_A32, MEMORY_COPY_A32_S },
10357 { MEMORY_COPY_A64, MEMORY_COPY_A64_S },
10358 { MEMORY_FILL_A32, MEMORY_FILL_A32_S },
10359 { MEMORY_FILL_A64, MEMORY_FILL_A64_S },
10360 { MEMORY_INIT_A32, MEMORY_INIT_A32_S },
10361 { MEMORY_INIT_A64, MEMORY_INIT_A64_S },
10362 { MEMSET_A32, MEMSET_A32_S },
10363 { MEMSET_A64, MEMSET_A64_S },
10364 { MIN_F16x8, MIN_F16x8_S },
10365 { MIN_F32, MIN_F32_S },
10366 { MIN_F32x4, MIN_F32x4_S },
10367 { MIN_F64, MIN_F64_S },
10368 { MIN_F64x2, MIN_F64x2_S },
10369 { MIN_S_I16x8, MIN_S_I16x8_S },
10370 { MIN_S_I32x4, MIN_S_I32x4_S },
10371 { MIN_S_I8x16, MIN_S_I8x16_S },
10372 { MIN_U_I16x8, MIN_U_I16x8_S },
10373 { MIN_U_I32x4, MIN_U_I32x4_S },
10374 { MIN_U_I8x16, MIN_U_I8x16_S },
10375 { MUL_F16x8, MUL_F16x8_S },
10376 { MUL_F32, MUL_F32_S },
10377 { MUL_F32x4, MUL_F32x4_S },
10378 { MUL_F64, MUL_F64_S },
10379 { MUL_F64x2, MUL_F64x2_S },
10380 { MUL_I16x8, MUL_I16x8_S },
10381 { MUL_I32, MUL_I32_S },
10382 { MUL_I32x4, MUL_I32x4_S },
10383 { MUL_I64, MUL_I64_S },
10384 { MUL_I64x2, MUL_I64x2_S },
10385 { NARROW_S_I16x8, NARROW_S_I16x8_S },
10386 { NARROW_S_I8x16, NARROW_S_I8x16_S },
10387 { NARROW_U_I16x8, NARROW_U_I16x8_S },
10388 { NARROW_U_I8x16, NARROW_U_I8x16_S },
10389 { NEAREST_F16x8, NEAREST_F16x8_S },
10390 { NEAREST_F32, NEAREST_F32_S },
10391 { NEAREST_F32x4, NEAREST_F32x4_S },
10392 { NEAREST_F64, NEAREST_F64_S },
10393 { NEAREST_F64x2, NEAREST_F64x2_S },
10394 { NEG_F16x8, NEG_F16x8_S },
10395 { NEG_F32, NEG_F32_S },
10396 { NEG_F32x4, NEG_F32x4_S },
10397 { NEG_F64, NEG_F64_S },
10398 { NEG_F64x2, NEG_F64x2_S },
10399 { NEG_I16x8, NEG_I16x8_S },
10400 { NEG_I32x4, NEG_I32x4_S },
10401 { NEG_I64x2, NEG_I64x2_S },
10402 { NEG_I8x16, NEG_I8x16_S },
10403 { NE_F16x8, NE_F16x8_S },
10404 { NE_F32, NE_F32_S },
10405 { NE_F32x4, NE_F32x4_S },
10406 { NE_F64, NE_F64_S },
10407 { NE_F64x2, NE_F64x2_S },
10408 { NE_I16x8, NE_I16x8_S },
10409 { NE_I32, NE_I32_S },
10410 { NE_I32x4, NE_I32x4_S },
10411 { NE_I64, NE_I64_S },
10412 { NE_I64x2, NE_I64x2_S },
10413 { NE_I8x16, NE_I8x16_S },
10414 { NMADD_F16x8, NMADD_F16x8_S },
10415 { NMADD_F32x4, NMADD_F32x4_S },
10416 { NMADD_F64x2, NMADD_F64x2_S },
10417 { NOP, NOP_S },
10418 { NOT, NOT_S },
10419 { OR, OR_S },
10420 { OR_I32, OR_I32_S },
10421 { OR_I64, OR_I64_S },
10422 { PMAX_F16x8, PMAX_F16x8_S },
10423 { PMAX_F32x4, PMAX_F32x4_S },
10424 { PMAX_F64x2, PMAX_F64x2_S },
10425 { PMIN_F16x8, PMIN_F16x8_S },
10426 { PMIN_F32x4, PMIN_F32x4_S },
10427 { PMIN_F64x2, PMIN_F64x2_S },
10428 { POPCNT_I32, POPCNT_I32_S },
10429 { POPCNT_I64, POPCNT_I64_S },
10430 { POPCNT_I8x16, POPCNT_I8x16_S },
10431 { Q15MULR_SAT_S_I16x8, Q15MULR_SAT_S_I16x8_S },
10432 { REF_IS_NULL_EXNREF, REF_IS_NULL_EXNREF_S },
10433 { REF_IS_NULL_EXTERNREF, REF_IS_NULL_EXTERNREF_S },
10434 { REF_IS_NULL_FUNCREF, REF_IS_NULL_FUNCREF_S },
10435 { REF_NULL_EXNREF, REF_NULL_EXNREF_S },
10436 { REF_NULL_EXTERNREF, REF_NULL_EXTERNREF_S },
10437 { REF_NULL_FUNCREF, REF_NULL_FUNCREF_S },
10438 { RELAXED_DOT, RELAXED_DOT_S },
10439 { RELAXED_DOT_ADD, RELAXED_DOT_ADD_S },
10440 { RELAXED_DOT_BFLOAT, RELAXED_DOT_BFLOAT_S },
10441 { RELAXED_Q15MULR_S_I16x8, RELAXED_Q15MULR_S_I16x8_S },
10442 { RELAXED_SWIZZLE, RELAXED_SWIZZLE_S },
10443 { REM_S_I32, REM_S_I32_S },
10444 { REM_S_I64, REM_S_I64_S },
10445 { REM_U_I32, REM_U_I32_S },
10446 { REM_U_I64, REM_U_I64_S },
10447 { REPLACE_LANE_F16x8, REPLACE_LANE_F16x8_S },
10448 { REPLACE_LANE_F32x4, REPLACE_LANE_F32x4_S },
10449 { REPLACE_LANE_F64x2, REPLACE_LANE_F64x2_S },
10450 { REPLACE_LANE_I16x8, REPLACE_LANE_I16x8_S },
10451 { REPLACE_LANE_I32x4, REPLACE_LANE_I32x4_S },
10452 { REPLACE_LANE_I64x2, REPLACE_LANE_I64x2_S },
10453 { REPLACE_LANE_I8x16, REPLACE_LANE_I8x16_S },
10454 { RETHROW, RETHROW_S },
10455 { RETURN, RETURN_S },
10456 { RET_CALL, RET_CALL_S },
10457 { RET_CALL_INDIRECT, RET_CALL_INDIRECT_S },
10458 { ROTL_I32, ROTL_I32_S },
10459 { ROTL_I64, ROTL_I64_S },
10460 { ROTR_I32, ROTR_I32_S },
10461 { ROTR_I64, ROTR_I64_S },
10462 { SELECT_EXNREF, SELECT_EXNREF_S },
10463 { SELECT_EXTERNREF, SELECT_EXTERNREF_S },
10464 { SELECT_F32, SELECT_F32_S },
10465 { SELECT_F64, SELECT_F64_S },
10466 { SELECT_FUNCREF, SELECT_FUNCREF_S },
10467 { SELECT_I32, SELECT_I32_S },
10468 { SELECT_I64, SELECT_I64_S },
10469 { SELECT_V128, SELECT_V128_S },
10470 { SHL_I16x8, SHL_I16x8_S },
10471 { SHL_I32, SHL_I32_S },
10472 { SHL_I32x4, SHL_I32x4_S },
10473 { SHL_I64, SHL_I64_S },
10474 { SHL_I64x2, SHL_I64x2_S },
10475 { SHL_I8x16, SHL_I8x16_S },
10476 { SHR_S_I16x8, SHR_S_I16x8_S },
10477 { SHR_S_I32, SHR_S_I32_S },
10478 { SHR_S_I32x4, SHR_S_I32x4_S },
10479 { SHR_S_I64, SHR_S_I64_S },
10480 { SHR_S_I64x2, SHR_S_I64x2_S },
10481 { SHR_S_I8x16, SHR_S_I8x16_S },
10482 { SHR_U_I16x8, SHR_U_I16x8_S },
10483 { SHR_U_I32, SHR_U_I32_S },
10484 { SHR_U_I32x4, SHR_U_I32x4_S },
10485 { SHR_U_I64, SHR_U_I64_S },
10486 { SHR_U_I64x2, SHR_U_I64x2_S },
10487 { SHR_U_I8x16, SHR_U_I8x16_S },
10488 { SHUFFLE, SHUFFLE_S },
10489 { SIMD_RELAXED_FMAX_F32x4, SIMD_RELAXED_FMAX_F32x4_S },
10490 { SIMD_RELAXED_FMAX_F64x2, SIMD_RELAXED_FMAX_F64x2_S },
10491 { SIMD_RELAXED_FMIN_F32x4, SIMD_RELAXED_FMIN_F32x4_S },
10492 { SIMD_RELAXED_FMIN_F64x2, SIMD_RELAXED_FMIN_F64x2_S },
10493 { SPLAT_F16x8, SPLAT_F16x8_S },
10494 { SPLAT_F32x4, SPLAT_F32x4_S },
10495 { SPLAT_F64x2, SPLAT_F64x2_S },
10496 { SPLAT_I16x8, SPLAT_I16x8_S },
10497 { SPLAT_I32x4, SPLAT_I32x4_S },
10498 { SPLAT_I64x2, SPLAT_I64x2_S },
10499 { SPLAT_I8x16, SPLAT_I8x16_S },
10500 { SQRT_F16x8, SQRT_F16x8_S },
10501 { SQRT_F32, SQRT_F32_S },
10502 { SQRT_F32x4, SQRT_F32x4_S },
10503 { SQRT_F64, SQRT_F64_S },
10504 { SQRT_F64x2, SQRT_F64x2_S },
10505 { STORE16_I32_A32, STORE16_I32_A32_S },
10506 { STORE16_I32_A64, STORE16_I32_A64_S },
10507 { STORE16_I64_A32, STORE16_I64_A32_S },
10508 { STORE16_I64_A64, STORE16_I64_A64_S },
10509 { STORE32_I64_A32, STORE32_I64_A32_S },
10510 { STORE32_I64_A64, STORE32_I64_A64_S },
10511 { STORE8_I32_A32, STORE8_I32_A32_S },
10512 { STORE8_I32_A64, STORE8_I32_A64_S },
10513 { STORE8_I64_A32, STORE8_I64_A32_S },
10514 { STORE8_I64_A64, STORE8_I64_A64_S },
10515 { STORE_F16_F32_A32, STORE_F16_F32_A32_S },
10516 { STORE_F16_F32_A64, STORE_F16_F32_A64_S },
10517 { STORE_F32_A32, STORE_F32_A32_S },
10518 { STORE_F32_A64, STORE_F32_A64_S },
10519 { STORE_F64_A32, STORE_F64_A32_S },
10520 { STORE_F64_A64, STORE_F64_A64_S },
10521 { STORE_I32_A32, STORE_I32_A32_S },
10522 { STORE_I32_A64, STORE_I32_A64_S },
10523 { STORE_I64_A32, STORE_I64_A32_S },
10524 { STORE_I64_A64, STORE_I64_A64_S },
10525 { STORE_LANE_I16x8_A32, STORE_LANE_I16x8_A32_S },
10526 { STORE_LANE_I16x8_A64, STORE_LANE_I16x8_A64_S },
10527 { STORE_LANE_I32x4_A32, STORE_LANE_I32x4_A32_S },
10528 { STORE_LANE_I32x4_A64, STORE_LANE_I32x4_A64_S },
10529 { STORE_LANE_I64x2_A32, STORE_LANE_I64x2_A32_S },
10530 { STORE_LANE_I64x2_A64, STORE_LANE_I64x2_A64_S },
10531 { STORE_LANE_I8x16_A32, STORE_LANE_I8x16_A32_S },
10532 { STORE_LANE_I8x16_A64, STORE_LANE_I8x16_A64_S },
10533 { STORE_V128_A32, STORE_V128_A32_S },
10534 { STORE_V128_A64, STORE_V128_A64_S },
10535 { SUB_F16x8, SUB_F16x8_S },
10536 { SUB_F32, SUB_F32_S },
10537 { SUB_F32x4, SUB_F32x4_S },
10538 { SUB_F64, SUB_F64_S },
10539 { SUB_F64x2, SUB_F64x2_S },
10540 { SUB_I16x8, SUB_I16x8_S },
10541 { SUB_I32, SUB_I32_S },
10542 { SUB_I32x4, SUB_I32x4_S },
10543 { SUB_I64, SUB_I64_S },
10544 { SUB_I64x2, SUB_I64x2_S },
10545 { SUB_I8x16, SUB_I8x16_S },
10546 { SUB_SAT_S_I16x8, SUB_SAT_S_I16x8_S },
10547 { SUB_SAT_S_I8x16, SUB_SAT_S_I8x16_S },
10548 { SUB_SAT_U_I16x8, SUB_SAT_U_I16x8_S },
10549 { SUB_SAT_U_I8x16, SUB_SAT_U_I8x16_S },
10550 { SWIZZLE, SWIZZLE_S },
10551 { TABLE_COPY, TABLE_COPY_S },
10552 { TABLE_FILL_EXNREF, TABLE_FILL_EXNREF_S },
10553 { TABLE_FILL_EXTERNREF, TABLE_FILL_EXTERNREF_S },
10554 { TABLE_FILL_FUNCREF, TABLE_FILL_FUNCREF_S },
10555 { TABLE_GET_EXNREF, TABLE_GET_EXNREF_S },
10556 { TABLE_GET_EXTERNREF, TABLE_GET_EXTERNREF_S },
10557 { TABLE_GET_FUNCREF, TABLE_GET_FUNCREF_S },
10558 { TABLE_GROW_EXNREF, TABLE_GROW_EXNREF_S },
10559 { TABLE_GROW_EXTERNREF, TABLE_GROW_EXTERNREF_S },
10560 { TABLE_GROW_FUNCREF, TABLE_GROW_FUNCREF_S },
10561 { TABLE_SET_EXNREF, TABLE_SET_EXNREF_S },
10562 { TABLE_SET_EXTERNREF, TABLE_SET_EXTERNREF_S },
10563 { TABLE_SET_FUNCREF, TABLE_SET_FUNCREF_S },
10564 { TABLE_SIZE, TABLE_SIZE_S },
10565 { TEE_EXNREF, TEE_EXNREF_S },
10566 { TEE_EXTERNREF, TEE_EXTERNREF_S },
10567 { TEE_F32, TEE_F32_S },
10568 { TEE_F64, TEE_F64_S },
10569 { TEE_FUNCREF, TEE_FUNCREF_S },
10570 { TEE_I32, TEE_I32_S },
10571 { TEE_I64, TEE_I64_S },
10572 { TEE_V128, TEE_V128_S },
10573 { THROW, THROW_S },
10574 { THROW_REF, THROW_REF_S },
10575 { TRUNC_F16x8, TRUNC_F16x8_S },
10576 { TRUNC_F32, TRUNC_F32_S },
10577 { TRUNC_F32x4, TRUNC_F32x4_S },
10578 { TRUNC_F64, TRUNC_F64_S },
10579 { TRUNC_F64x2, TRUNC_F64x2_S },
10580 { TRY, TRY_S },
10581 { TRY_TABLE, TRY_TABLE_S },
10582 { UNREACHABLE, UNREACHABLE_S },
10583 { XOR, XOR_S },
10584 { XOR_I32, XOR_I32_S },
10585 { XOR_I64, XOR_I64_S },
10586 { anonymous_8818MEMORY_GROW_A32, anonymous_8818MEMORY_GROW_A32_S },
10587 { anonymous_8818MEMORY_SIZE_A32, anonymous_8818MEMORY_SIZE_A32_S },
10588 { anonymous_8819MEMORY_GROW_A64, anonymous_8819MEMORY_GROW_A64_S },
10589 { anonymous_8819MEMORY_SIZE_A64, anonymous_8819MEMORY_SIZE_A64_S },
10590 { convert_low_s_F64x2, convert_low_s_F64x2_S },
10591 { convert_low_u_F64x2, convert_low_u_F64x2_S },
10592 { demote_zero_F32x4, demote_zero_F32x4_S },
10593 { extend_high_s_I16x8, extend_high_s_I16x8_S },
10594 { extend_high_s_I32x4, extend_high_s_I32x4_S },
10595 { extend_high_s_I64x2, extend_high_s_I64x2_S },
10596 { extend_high_u_I16x8, extend_high_u_I16x8_S },
10597 { extend_high_u_I32x4, extend_high_u_I32x4_S },
10598 { extend_high_u_I64x2, extend_high_u_I64x2_S },
10599 { extend_low_s_I16x8, extend_low_s_I16x8_S },
10600 { extend_low_s_I32x4, extend_low_s_I32x4_S },
10601 { extend_low_s_I64x2, extend_low_s_I64x2_S },
10602 { extend_low_u_I16x8, extend_low_u_I16x8_S },
10603 { extend_low_u_I32x4, extend_low_u_I32x4_S },
10604 { extend_low_u_I64x2, extend_low_u_I64x2_S },
10605 { fp_to_sint_I16x8, fp_to_sint_I16x8_S },
10606 { fp_to_sint_I32x4, fp_to_sint_I32x4_S },
10607 { fp_to_uint_I16x8, fp_to_uint_I16x8_S },
10608 { fp_to_uint_I32x4, fp_to_uint_I32x4_S },
10609 { int_wasm_extadd_pairwise_signed_I16x8, int_wasm_extadd_pairwise_signed_I16x8_S },
10610 { int_wasm_extadd_pairwise_signed_I32x4, int_wasm_extadd_pairwise_signed_I32x4_S },
10611 { int_wasm_extadd_pairwise_unsigned_I16x8, int_wasm_extadd_pairwise_unsigned_I16x8_S },
10612 { int_wasm_extadd_pairwise_unsigned_I32x4, int_wasm_extadd_pairwise_unsigned_I32x4_S },
10613 { int_wasm_relaxed_trunc_signed_I32x4, int_wasm_relaxed_trunc_signed_I32x4_S },
10614 { int_wasm_relaxed_trunc_signed_zero_I32x4, int_wasm_relaxed_trunc_signed_zero_I32x4_S },
10615 { int_wasm_relaxed_trunc_unsigned_I32x4, int_wasm_relaxed_trunc_unsigned_I32x4_S },
10616 { int_wasm_relaxed_trunc_unsigned_zero_I32x4, int_wasm_relaxed_trunc_unsigned_zero_I32x4_S },
10617 { promote_low_F64x2, promote_low_F64x2_S },
10618 { sint_to_fp_F16x8, sint_to_fp_F16x8_S },
10619 { sint_to_fp_F32x4, sint_to_fp_F32x4_S },
10620 { trunc_sat_zero_s_I32x4, trunc_sat_zero_s_I32x4_S },
10621 { trunc_sat_zero_u_I32x4, trunc_sat_zero_u_I32x4_S },
10622 { uint_to_fp_F16x8, uint_to_fp_F16x8_S },
10623 { uint_to_fp_F32x4, uint_to_fp_F32x4_S },
10624 }; // End of Table
10625
10626 unsigned mid;
10627 unsigned start = 0;
10628 unsigned end = 815;
10629 while (start < end) {
10630 mid = start + (end - start) / 2;
10631 if (Opcode == Table[mid][0])
10632 break;
10633 if (Opcode < Table[mid][0])
10634 end = mid;
10635 else
10636 start = mid + 1;
10637 }
10638 if (start == end)
10639 return -1; // Instruction doesn't exist in this table.
10640
10641 return Table[mid][1];
10642}
10643
10644// getWasm64Opcode
10645LLVM_READONLY
10646int getWasm64Opcode(uint16_t Opcode) {
10647 using namespace WebAssembly;
10648 static constexpr uint16_t Table[][2] = {
10649 { ATOMIC_LOAD16_U_I32_A32, ATOMIC_LOAD16_U_I32_A64 },
10650 { ATOMIC_LOAD16_U_I32_A32_S, ATOMIC_LOAD16_U_I32_A64_S },
10651 { ATOMIC_LOAD16_U_I64_A32, ATOMIC_LOAD16_U_I64_A64 },
10652 { ATOMIC_LOAD16_U_I64_A32_S, ATOMIC_LOAD16_U_I64_A64_S },
10653 { ATOMIC_LOAD32_U_I64_A32, ATOMIC_LOAD32_U_I64_A64 },
10654 { ATOMIC_LOAD32_U_I64_A32_S, ATOMIC_LOAD32_U_I64_A64_S },
10655 { ATOMIC_LOAD8_U_I32_A32, ATOMIC_LOAD8_U_I32_A64 },
10656 { ATOMIC_LOAD8_U_I32_A32_S, ATOMIC_LOAD8_U_I32_A64_S },
10657 { ATOMIC_LOAD8_U_I64_A32, ATOMIC_LOAD8_U_I64_A64 },
10658 { ATOMIC_LOAD8_U_I64_A32_S, ATOMIC_LOAD8_U_I64_A64_S },
10659 { ATOMIC_LOAD_I32_A32, ATOMIC_LOAD_I32_A64 },
10660 { ATOMIC_LOAD_I32_A32_S, ATOMIC_LOAD_I32_A64_S },
10661 { ATOMIC_LOAD_I64_A32, ATOMIC_LOAD_I64_A64 },
10662 { ATOMIC_LOAD_I64_A32_S, ATOMIC_LOAD_I64_A64_S },
10663 { ATOMIC_RMW16_U_ADD_I32_A32, ATOMIC_RMW16_U_ADD_I32_A64 },
10664 { ATOMIC_RMW16_U_ADD_I32_A32_S, ATOMIC_RMW16_U_ADD_I32_A64_S },
10665 { ATOMIC_RMW16_U_ADD_I64_A32, ATOMIC_RMW16_U_ADD_I64_A64 },
10666 { ATOMIC_RMW16_U_ADD_I64_A32_S, ATOMIC_RMW16_U_ADD_I64_A64_S },
10667 { ATOMIC_RMW16_U_AND_I32_A32, ATOMIC_RMW16_U_AND_I32_A64 },
10668 { ATOMIC_RMW16_U_AND_I32_A32_S, ATOMIC_RMW16_U_AND_I32_A64_S },
10669 { ATOMIC_RMW16_U_AND_I64_A32, ATOMIC_RMW16_U_AND_I64_A64 },
10670 { ATOMIC_RMW16_U_AND_I64_A32_S, ATOMIC_RMW16_U_AND_I64_A64_S },
10671 { ATOMIC_RMW16_U_CMPXCHG_I32_A32, ATOMIC_RMW16_U_CMPXCHG_I32_A64 },
10672 { ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, ATOMIC_RMW16_U_CMPXCHG_I32_A64_S },
10673 { ATOMIC_RMW16_U_CMPXCHG_I64_A32, ATOMIC_RMW16_U_CMPXCHG_I64_A64 },
10674 { ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, ATOMIC_RMW16_U_CMPXCHG_I64_A64_S },
10675 { ATOMIC_RMW16_U_OR_I32_A32, ATOMIC_RMW16_U_OR_I32_A64 },
10676 { ATOMIC_RMW16_U_OR_I32_A32_S, ATOMIC_RMW16_U_OR_I32_A64_S },
10677 { ATOMIC_RMW16_U_OR_I64_A32, ATOMIC_RMW16_U_OR_I64_A64 },
10678 { ATOMIC_RMW16_U_OR_I64_A32_S, ATOMIC_RMW16_U_OR_I64_A64_S },
10679 { ATOMIC_RMW16_U_SUB_I32_A32, ATOMIC_RMW16_U_SUB_I32_A64 },
10680 { ATOMIC_RMW16_U_SUB_I32_A32_S, ATOMIC_RMW16_U_SUB_I32_A64_S },
10681 { ATOMIC_RMW16_U_SUB_I64_A32, ATOMIC_RMW16_U_SUB_I64_A64 },
10682 { ATOMIC_RMW16_U_SUB_I64_A32_S, ATOMIC_RMW16_U_SUB_I64_A64_S },
10683 { ATOMIC_RMW16_U_XCHG_I32_A32, ATOMIC_RMW16_U_XCHG_I32_A64 },
10684 { ATOMIC_RMW16_U_XCHG_I32_A32_S, ATOMIC_RMW16_U_XCHG_I32_A64_S },
10685 { ATOMIC_RMW16_U_XCHG_I64_A32, ATOMIC_RMW16_U_XCHG_I64_A64 },
10686 { ATOMIC_RMW16_U_XCHG_I64_A32_S, ATOMIC_RMW16_U_XCHG_I64_A64_S },
10687 { ATOMIC_RMW16_U_XOR_I32_A32, ATOMIC_RMW16_U_XOR_I32_A64 },
10688 { ATOMIC_RMW16_U_XOR_I32_A32_S, ATOMIC_RMW16_U_XOR_I32_A64_S },
10689 { ATOMIC_RMW16_U_XOR_I64_A32, ATOMIC_RMW16_U_XOR_I64_A64 },
10690 { ATOMIC_RMW16_U_XOR_I64_A32_S, ATOMIC_RMW16_U_XOR_I64_A64_S },
10691 { ATOMIC_RMW32_U_ADD_I64_A32, ATOMIC_RMW32_U_ADD_I64_A64 },
10692 { ATOMIC_RMW32_U_ADD_I64_A32_S, ATOMIC_RMW32_U_ADD_I64_A64_S },
10693 { ATOMIC_RMW32_U_AND_I64_A32, ATOMIC_RMW32_U_AND_I64_A64 },
10694 { ATOMIC_RMW32_U_AND_I64_A32_S, ATOMIC_RMW32_U_AND_I64_A64_S },
10695 { ATOMIC_RMW32_U_CMPXCHG_I64_A32, ATOMIC_RMW32_U_CMPXCHG_I64_A64 },
10696 { ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, ATOMIC_RMW32_U_CMPXCHG_I64_A64_S },
10697 { ATOMIC_RMW32_U_OR_I64_A32, ATOMIC_RMW32_U_OR_I64_A64 },
10698 { ATOMIC_RMW32_U_OR_I64_A32_S, ATOMIC_RMW32_U_OR_I64_A64_S },
10699 { ATOMIC_RMW32_U_SUB_I64_A32, ATOMIC_RMW32_U_SUB_I64_A64 },
10700 { ATOMIC_RMW32_U_SUB_I64_A32_S, ATOMIC_RMW32_U_SUB_I64_A64_S },
10701 { ATOMIC_RMW32_U_XCHG_I64_A32, ATOMIC_RMW32_U_XCHG_I64_A64 },
10702 { ATOMIC_RMW32_U_XCHG_I64_A32_S, ATOMIC_RMW32_U_XCHG_I64_A64_S },
10703 { ATOMIC_RMW32_U_XOR_I64_A32, ATOMIC_RMW32_U_XOR_I64_A64 },
10704 { ATOMIC_RMW32_U_XOR_I64_A32_S, ATOMIC_RMW32_U_XOR_I64_A64_S },
10705 { ATOMIC_RMW8_U_ADD_I32_A32, ATOMIC_RMW8_U_ADD_I32_A64 },
10706 { ATOMIC_RMW8_U_ADD_I32_A32_S, ATOMIC_RMW8_U_ADD_I32_A64_S },
10707 { ATOMIC_RMW8_U_ADD_I64_A32, ATOMIC_RMW8_U_ADD_I64_A64 },
10708 { ATOMIC_RMW8_U_ADD_I64_A32_S, ATOMIC_RMW8_U_ADD_I64_A64_S },
10709 { ATOMIC_RMW8_U_AND_I32_A32, ATOMIC_RMW8_U_AND_I32_A64 },
10710 { ATOMIC_RMW8_U_AND_I32_A32_S, ATOMIC_RMW8_U_AND_I32_A64_S },
10711 { ATOMIC_RMW8_U_AND_I64_A32, ATOMIC_RMW8_U_AND_I64_A64 },
10712 { ATOMIC_RMW8_U_AND_I64_A32_S, ATOMIC_RMW8_U_AND_I64_A64_S },
10713 { ATOMIC_RMW8_U_CMPXCHG_I32_A32, ATOMIC_RMW8_U_CMPXCHG_I32_A64 },
10714 { ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, ATOMIC_RMW8_U_CMPXCHG_I32_A64_S },
10715 { ATOMIC_RMW8_U_CMPXCHG_I64_A32, ATOMIC_RMW8_U_CMPXCHG_I64_A64 },
10716 { ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, ATOMIC_RMW8_U_CMPXCHG_I64_A64_S },
10717 { ATOMIC_RMW8_U_OR_I32_A32, ATOMIC_RMW8_U_OR_I32_A64 },
10718 { ATOMIC_RMW8_U_OR_I32_A32_S, ATOMIC_RMW8_U_OR_I32_A64_S },
10719 { ATOMIC_RMW8_U_OR_I64_A32, ATOMIC_RMW8_U_OR_I64_A64 },
10720 { ATOMIC_RMW8_U_OR_I64_A32_S, ATOMIC_RMW8_U_OR_I64_A64_S },
10721 { ATOMIC_RMW8_U_SUB_I32_A32, ATOMIC_RMW8_U_SUB_I32_A64 },
10722 { ATOMIC_RMW8_U_SUB_I32_A32_S, ATOMIC_RMW8_U_SUB_I32_A64_S },
10723 { ATOMIC_RMW8_U_SUB_I64_A32, ATOMIC_RMW8_U_SUB_I64_A64 },
10724 { ATOMIC_RMW8_U_SUB_I64_A32_S, ATOMIC_RMW8_U_SUB_I64_A64_S },
10725 { ATOMIC_RMW8_U_XCHG_I32_A32, ATOMIC_RMW8_U_XCHG_I32_A64 },
10726 { ATOMIC_RMW8_U_XCHG_I32_A32_S, ATOMIC_RMW8_U_XCHG_I32_A64_S },
10727 { ATOMIC_RMW8_U_XCHG_I64_A32, ATOMIC_RMW8_U_XCHG_I64_A64 },
10728 { ATOMIC_RMW8_U_XCHG_I64_A32_S, ATOMIC_RMW8_U_XCHG_I64_A64_S },
10729 { ATOMIC_RMW8_U_XOR_I32_A32, ATOMIC_RMW8_U_XOR_I32_A64 },
10730 { ATOMIC_RMW8_U_XOR_I32_A32_S, ATOMIC_RMW8_U_XOR_I32_A64_S },
10731 { ATOMIC_RMW8_U_XOR_I64_A32, ATOMIC_RMW8_U_XOR_I64_A64 },
10732 { ATOMIC_RMW8_U_XOR_I64_A32_S, ATOMIC_RMW8_U_XOR_I64_A64_S },
10733 { ATOMIC_RMW_ADD_I32_A32, ATOMIC_RMW_ADD_I32_A64 },
10734 { ATOMIC_RMW_ADD_I32_A32_S, ATOMIC_RMW_ADD_I32_A64_S },
10735 { ATOMIC_RMW_ADD_I64_A32, ATOMIC_RMW_ADD_I64_A64 },
10736 { ATOMIC_RMW_ADD_I64_A32_S, ATOMIC_RMW_ADD_I64_A64_S },
10737 { ATOMIC_RMW_AND_I32_A32, ATOMIC_RMW_AND_I32_A64 },
10738 { ATOMIC_RMW_AND_I32_A32_S, ATOMIC_RMW_AND_I32_A64_S },
10739 { ATOMIC_RMW_AND_I64_A32, ATOMIC_RMW_AND_I64_A64 },
10740 { ATOMIC_RMW_AND_I64_A32_S, ATOMIC_RMW_AND_I64_A64_S },
10741 { ATOMIC_RMW_CMPXCHG_I32_A32, ATOMIC_RMW_CMPXCHG_I32_A64 },
10742 { ATOMIC_RMW_CMPXCHG_I32_A32_S, ATOMIC_RMW_CMPXCHG_I32_A64_S },
10743 { ATOMIC_RMW_CMPXCHG_I64_A32, ATOMIC_RMW_CMPXCHG_I64_A64 },
10744 { ATOMIC_RMW_CMPXCHG_I64_A32_S, ATOMIC_RMW_CMPXCHG_I64_A64_S },
10745 { ATOMIC_RMW_OR_I32_A32, ATOMIC_RMW_OR_I32_A64 },
10746 { ATOMIC_RMW_OR_I32_A32_S, ATOMIC_RMW_OR_I32_A64_S },
10747 { ATOMIC_RMW_OR_I64_A32, ATOMIC_RMW_OR_I64_A64 },
10748 { ATOMIC_RMW_OR_I64_A32_S, ATOMIC_RMW_OR_I64_A64_S },
10749 { ATOMIC_RMW_SUB_I32_A32, ATOMIC_RMW_SUB_I32_A64 },
10750 { ATOMIC_RMW_SUB_I32_A32_S, ATOMIC_RMW_SUB_I32_A64_S },
10751 { ATOMIC_RMW_SUB_I64_A32, ATOMIC_RMW_SUB_I64_A64 },
10752 { ATOMIC_RMW_SUB_I64_A32_S, ATOMIC_RMW_SUB_I64_A64_S },
10753 { ATOMIC_RMW_XCHG_I32_A32, ATOMIC_RMW_XCHG_I32_A64 },
10754 { ATOMIC_RMW_XCHG_I32_A32_S, ATOMIC_RMW_XCHG_I32_A64_S },
10755 { ATOMIC_RMW_XCHG_I64_A32, ATOMIC_RMW_XCHG_I64_A64 },
10756 { ATOMIC_RMW_XCHG_I64_A32_S, ATOMIC_RMW_XCHG_I64_A64_S },
10757 { ATOMIC_RMW_XOR_I32_A32, ATOMIC_RMW_XOR_I32_A64 },
10758 { ATOMIC_RMW_XOR_I32_A32_S, ATOMIC_RMW_XOR_I32_A64_S },
10759 { ATOMIC_RMW_XOR_I64_A32, ATOMIC_RMW_XOR_I64_A64 },
10760 { ATOMIC_RMW_XOR_I64_A32_S, ATOMIC_RMW_XOR_I64_A64_S },
10761 { ATOMIC_STORE16_I32_A32, ATOMIC_STORE16_I32_A64 },
10762 { ATOMIC_STORE16_I32_A32_S, ATOMIC_STORE16_I32_A64_S },
10763 { ATOMIC_STORE16_I64_A32, ATOMIC_STORE16_I64_A64 },
10764 { ATOMIC_STORE16_I64_A32_S, ATOMIC_STORE16_I64_A64_S },
10765 { ATOMIC_STORE32_I64_A32, ATOMIC_STORE32_I64_A64 },
10766 { ATOMIC_STORE32_I64_A32_S, ATOMIC_STORE32_I64_A64_S },
10767 { ATOMIC_STORE8_I32_A32, ATOMIC_STORE8_I32_A64 },
10768 { ATOMIC_STORE8_I32_A32_S, ATOMIC_STORE8_I32_A64_S },
10769 { ATOMIC_STORE8_I64_A32, ATOMIC_STORE8_I64_A64 },
10770 { ATOMIC_STORE8_I64_A32_S, ATOMIC_STORE8_I64_A64_S },
10771 { ATOMIC_STORE_I32_A32, ATOMIC_STORE_I32_A64 },
10772 { ATOMIC_STORE_I32_A32_S, ATOMIC_STORE_I32_A64_S },
10773 { ATOMIC_STORE_I64_A32, ATOMIC_STORE_I64_A64 },
10774 { ATOMIC_STORE_I64_A32_S, ATOMIC_STORE_I64_A64_S },
10775 { LOAD16_S_I32_A32, LOAD16_S_I32_A64 },
10776 { LOAD16_S_I32_A32_S, LOAD16_S_I32_A64_S },
10777 { LOAD16_S_I64_A32, LOAD16_S_I64_A64 },
10778 { LOAD16_S_I64_A32_S, LOAD16_S_I64_A64_S },
10779 { LOAD16_U_I32_A32, LOAD16_U_I32_A64 },
10780 { LOAD16_U_I32_A32_S, LOAD16_U_I32_A64_S },
10781 { LOAD16_U_I64_A32, LOAD16_U_I64_A64 },
10782 { LOAD16_U_I64_A32_S, LOAD16_U_I64_A64_S },
10783 { LOAD32_S_I64_A32, LOAD32_S_I64_A64 },
10784 { LOAD32_S_I64_A32_S, LOAD32_S_I64_A64_S },
10785 { LOAD32_U_I64_A32, LOAD32_U_I64_A64 },
10786 { LOAD32_U_I64_A32_S, LOAD32_U_I64_A64_S },
10787 { LOAD8_S_I32_A32, LOAD8_S_I32_A64 },
10788 { LOAD8_S_I32_A32_S, LOAD8_S_I32_A64_S },
10789 { LOAD8_S_I64_A32, LOAD8_S_I64_A64 },
10790 { LOAD8_S_I64_A32_S, LOAD8_S_I64_A64_S },
10791 { LOAD8_U_I32_A32, LOAD8_U_I32_A64 },
10792 { LOAD8_U_I32_A32_S, LOAD8_U_I32_A64_S },
10793 { LOAD8_U_I64_A32, LOAD8_U_I64_A64 },
10794 { LOAD8_U_I64_A32_S, LOAD8_U_I64_A64_S },
10795 { LOAD_F16_F32_A32, LOAD_F16_F32_A64 },
10796 { LOAD_F16_F32_A32_S, LOAD_F16_F32_A64_S },
10797 { LOAD_F32_A32, LOAD_F32_A64 },
10798 { LOAD_F32_A32_S, LOAD_F32_A64_S },
10799 { LOAD_F64_A32, LOAD_F64_A64 },
10800 { LOAD_F64_A32_S, LOAD_F64_A64_S },
10801 { LOAD_I32_A32, LOAD_I32_A64 },
10802 { LOAD_I32_A32_S, LOAD_I32_A64_S },
10803 { LOAD_I64_A32, LOAD_I64_A64 },
10804 { LOAD_I64_A32_S, LOAD_I64_A64_S },
10805 { MEMORY_ATOMIC_NOTIFY_A32, MEMORY_ATOMIC_NOTIFY_A64 },
10806 { MEMORY_ATOMIC_NOTIFY_A32_S, MEMORY_ATOMIC_NOTIFY_A64_S },
10807 { MEMORY_ATOMIC_WAIT32_A32, MEMORY_ATOMIC_WAIT32_A64 },
10808 { MEMORY_ATOMIC_WAIT32_A32_S, MEMORY_ATOMIC_WAIT32_A64_S },
10809 { MEMORY_ATOMIC_WAIT64_A32, MEMORY_ATOMIC_WAIT64_A64 },
10810 { MEMORY_ATOMIC_WAIT64_A32_S, MEMORY_ATOMIC_WAIT64_A64_S },
10811 { STORE16_I32_A32, STORE16_I32_A64 },
10812 { STORE16_I32_A32_S, STORE16_I32_A64_S },
10813 { STORE16_I64_A32, STORE16_I64_A64 },
10814 { STORE16_I64_A32_S, STORE16_I64_A64_S },
10815 { STORE32_I64_A32, STORE32_I64_A64 },
10816 { STORE32_I64_A32_S, STORE32_I64_A64_S },
10817 { STORE8_I32_A32, STORE8_I32_A64 },
10818 { STORE8_I32_A32_S, STORE8_I32_A64_S },
10819 { STORE8_I64_A32, STORE8_I64_A64 },
10820 { STORE8_I64_A32_S, STORE8_I64_A64_S },
10821 { STORE_F16_F32_A32, STORE_F16_F32_A64 },
10822 { STORE_F16_F32_A32_S, STORE_F16_F32_A64_S },
10823 { STORE_F32_A32, STORE_F32_A64 },
10824 { STORE_F32_A32_S, STORE_F32_A64_S },
10825 { STORE_F64_A32, STORE_F64_A64 },
10826 { STORE_F64_A32_S, STORE_F64_A64_S },
10827 { STORE_I32_A32, STORE_I32_A64 },
10828 { STORE_I32_A32_S, STORE_I32_A64_S },
10829 { STORE_I64_A32, STORE_I64_A64 },
10830 { STORE_I64_A32_S, STORE_I64_A64_S },
10831 }; // End of Table
10832
10833 unsigned mid;
10834 unsigned start = 0;
10835 unsigned end = 182;
10836 while (start < end) {
10837 mid = start + (end - start) / 2;
10838 if (Opcode == Table[mid][0])
10839 break;
10840 if (Opcode < Table[mid][0])
10841 end = mid;
10842 else
10843 start = mid + 1;
10844 }
10845 if (start == end)
10846 return -1; // Instruction doesn't exist in this table.
10847
10848 return Table[mid][1];
10849}
10850
10851} // end namespace llvm::WebAssembly
10852#endif // GET_INSTRMAP_INFO
10853
10854