1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass WebAssemblyMCRegisterClasses[];
17
18namespace WebAssembly {
19enum : unsigned {
20 NoRegister,
21 ARGUMENTS = 1,
22 VALUE_STACK = 2,
23 EXNREF_0 = 3,
24 EXTERNREF_0 = 4,
25 FP32 = 5,
26 FP64 = 6,
27 FUNCREF_0 = 7,
28 SP32 = 8,
29 SP64 = 9,
30 F32_0 = 10,
31 F64_0 = 11,
32 I32_0 = 12,
33 I64_0 = 13,
34 V128_0 = 14,
35 NUM_TARGET_REGS // 15
36};
37} // end namespace WebAssembly
38
39// Register classes
40
41namespace WebAssembly {
42enum {
43 EXNREFRegClassID = 0,
44 EXTERNREFRegClassID = 1,
45 FUNCREFRegClassID = 2,
46 I32RegClassID = 3,
47 F32RegClassID = 4,
48 I64RegClassID = 5,
49 F64RegClassID = 6,
50 V128RegClassID = 7,
51
52};
53} // end namespace WebAssembly
54
55// Register pressure sets enum.
56namespace WebAssembly {
57enum RegisterPressureSets {
58 EXNREF = 0,
59 EXTERNREF = 1,
60 FUNCREF = 2,
61 F32 = 3,
62 F64 = 4,
63 V128 = 5,
64 I32 = 6,
65 I64 = 7,
66};
67} // end namespace WebAssembly
68
69} // end namespace llvm
70
71#endif // GET_REGINFO_ENUM
72
73/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
74|* *|
75|* MC Register Information *|
76|* *|
77|* Automatically generated file, do not edit! *|
78|* *|
79\*===----------------------------------------------------------------------===*/
80
81
82#ifdef GET_REGINFO_MC_DESC
83#undef GET_REGINFO_MC_DESC
84
85namespace llvm {
86
87extern const int16_t WebAssemblyRegDiffLists[] = {
88 /* 0 */ 0,
89};
90
91extern const LaneBitmask WebAssemblyLaneMaskLists[] = {
92 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
93};
94
95extern const uint16_t WebAssemblySubRegIdxLists[] = {
96 /* 0 */
97 /* dummy */ 0
98};
99
100
101#ifdef __GNUC__
102#pragma GCC diagnostic push
103#pragma GCC diagnostic ignored "-Woverlength-strings"
104#endif
105extern const char WebAssemblyRegStrings[] = {
106 /* 0 */ "F32_0\000"
107 /* 6 */ "I32_0\000"
108 /* 12 */ "F64_0\000"
109 /* 18 */ "I64_0\000"
110 /* 24 */ "V128_0\000"
111 /* 31 */ "FUNCREF_0\000"
112 /* 41 */ "EXTERNREF_0\000"
113 /* 53 */ "EXNREF_0\000"
114 /* 62 */ "FP32\000"
115 /* 67 */ "SP32\000"
116 /* 72 */ "FP64\000"
117 /* 77 */ "SP64\000"
118 /* 82 */ "VALUE_STACK\000"
119 /* 94 */ "ARGUMENTS\000"
120};
121#ifdef __GNUC__
122#pragma GCC diagnostic pop
123#endif
124
125extern const MCRegisterDesc WebAssemblyRegDesc[] = { // Descriptors
126 { 5, 0, 0, 0, 0, 0, 0, 0 },
127 { 94, 0, 0, 0, 0, 0, 0, 0 },
128 { 82, 0, 0, 0, 1, 0, 0, 0 },
129 { 53, 0, 0, 0, 2, 0, 0, 0 },
130 { 41, 0, 0, 0, 3, 0, 0, 0 },
131 { 62, 0, 0, 0, 4, 0, 0, 0 },
132 { 72, 0, 0, 0, 5, 0, 0, 0 },
133 { 31, 0, 0, 0, 6, 0, 0, 0 },
134 { 67, 0, 0, 0, 7, 0, 0, 0 },
135 { 77, 0, 0, 0, 8, 0, 0, 0 },
136 { 0, 0, 0, 0, 9, 0, 0, 0 },
137 { 12, 0, 0, 0, 10, 0, 0, 0 },
138 { 6, 0, 0, 0, 11, 0, 0, 0 },
139 { 18, 0, 0, 0, 12, 0, 0, 0 },
140 { 24, 0, 0, 0, 13, 0, 0, 0 },
141};
142
143extern const MCPhysReg WebAssemblyRegUnitRoots[][2] = {
144 { WebAssembly::ARGUMENTS },
145 { WebAssembly::VALUE_STACK },
146 { WebAssembly::EXNREF_0 },
147 { WebAssembly::EXTERNREF_0 },
148 { WebAssembly::FP32 },
149 { WebAssembly::FP64 },
150 { WebAssembly::FUNCREF_0 },
151 { WebAssembly::SP32 },
152 { WebAssembly::SP64 },
153 { WebAssembly::F32_0 },
154 { WebAssembly::F64_0 },
155 { WebAssembly::I32_0 },
156 { WebAssembly::I64_0 },
157 { WebAssembly::V128_0 },
158};
159
160namespace { // Register classes...
161 // EXNREF Register Class...
162 const MCPhysReg EXNREF[] = {
163 WebAssembly::EXNREF_0,
164 };
165
166 // EXNREF Bit set.
167 const uint8_t EXNREFBits[] = {
168 0x08,
169 };
170
171 // EXTERNREF Register Class...
172 const MCPhysReg EXTERNREF[] = {
173 WebAssembly::EXTERNREF_0,
174 };
175
176 // EXTERNREF Bit set.
177 const uint8_t EXTERNREFBits[] = {
178 0x10,
179 };
180
181 // FUNCREF Register Class...
182 const MCPhysReg FUNCREF[] = {
183 WebAssembly::FUNCREF_0,
184 };
185
186 // FUNCREF Bit set.
187 const uint8_t FUNCREFBits[] = {
188 0x80,
189 };
190
191 // I32 Register Class...
192 const MCPhysReg I32[] = {
193 WebAssembly::FP32, WebAssembly::SP32, WebAssembly::I32_0,
194 };
195
196 // I32 Bit set.
197 const uint8_t I32Bits[] = {
198 0x20, 0x11,
199 };
200
201 // F32 Register Class...
202 const MCPhysReg F32[] = {
203 WebAssembly::F32_0,
204 };
205
206 // F32 Bit set.
207 const uint8_t F32Bits[] = {
208 0x00, 0x04,
209 };
210
211 // I64 Register Class...
212 const MCPhysReg I64[] = {
213 WebAssembly::FP64, WebAssembly::SP64, WebAssembly::I64_0,
214 };
215
216 // I64 Bit set.
217 const uint8_t I64Bits[] = {
218 0x40, 0x22,
219 };
220
221 // F64 Register Class...
222 const MCPhysReg F64[] = {
223 WebAssembly::F64_0,
224 };
225
226 // F64 Bit set.
227 const uint8_t F64Bits[] = {
228 0x00, 0x08,
229 };
230
231 // V128 Register Class...
232 const MCPhysReg V128[] = {
233 WebAssembly::V128_0,
234 };
235
236 // V128 Bit set.
237 const uint8_t V128Bits[] = {
238 0x00, 0x40,
239 };
240
241} // end anonymous namespace
242
243
244#ifdef __GNUC__
245#pragma GCC diagnostic push
246#pragma GCC diagnostic ignored "-Woverlength-strings"
247#endif
248extern const char WebAssemblyRegClassStrings[] = {
249 /* 0 */ "F32\000"
250 /* 4 */ "I32\000"
251 /* 8 */ "F64\000"
252 /* 12 */ "I64\000"
253 /* 16 */ "V128\000"
254 /* 21 */ "FUNCREF\000"
255 /* 29 */ "EXTERNREF\000"
256 /* 39 */ "EXNREF\000"
257};
258#ifdef __GNUC__
259#pragma GCC diagnostic pop
260#endif
261
262extern const MCRegisterClass WebAssemblyMCRegisterClasses[] = {
263 { EXNREF, EXNREFBits, 39, 1, sizeof(EXNREFBits), WebAssembly::EXNREFRegClassID, 0, 1, true, false },
264 { EXTERNREF, EXTERNREFBits, 29, 1, sizeof(EXTERNREFBits), WebAssembly::EXTERNREFRegClassID, 0, 1, true, false },
265 { FUNCREF, FUNCREFBits, 21, 1, sizeof(FUNCREFBits), WebAssembly::FUNCREFRegClassID, 0, 1, true, false },
266 { I32, I32Bits, 4, 3, sizeof(I32Bits), WebAssembly::I32RegClassID, 32, 1, true, false },
267 { F32, F32Bits, 0, 1, sizeof(F32Bits), WebAssembly::F32RegClassID, 32, 1, true, false },
268 { I64, I64Bits, 12, 3, sizeof(I64Bits), WebAssembly::I64RegClassID, 64, 1, true, false },
269 { F64, F64Bits, 8, 1, sizeof(F64Bits), WebAssembly::F64RegClassID, 64, 1, true, false },
270 { V128, V128Bits, 16, 1, sizeof(V128Bits), WebAssembly::V128RegClassID, 128, 1, true, false },
271};
272
273extern const uint16_t WebAssemblyRegEncodingTable[] = {
274 0,
275 0,
276 0,
277 0,
278 0,
279 0,
280 0,
281 0,
282 0,
283 0,
284 0,
285 0,
286 0,
287 0,
288 0,
289};
290static inline void InitWebAssemblyMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
291 RI->InitMCRegisterInfo(WebAssemblyRegDesc, 15, RA, PC, WebAssemblyMCRegisterClasses, 8, WebAssemblyRegUnitRoots, 14, WebAssemblyRegDiffLists, WebAssemblyLaneMaskLists, WebAssemblyRegStrings, WebAssemblyRegClassStrings, WebAssemblySubRegIdxLists, 1,
292WebAssemblyRegEncodingTable);
293
294}
295
296} // end namespace llvm
297
298#endif // GET_REGINFO_MC_DESC
299
300/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
301|* *|
302|* Register Information Header Fragment *|
303|* *|
304|* Automatically generated file, do not edit! *|
305|* *|
306\*===----------------------------------------------------------------------===*/
307
308
309#ifdef GET_REGINFO_HEADER
310#undef GET_REGINFO_HEADER
311
312#include "llvm/CodeGen/TargetRegisterInfo.h"
313
314namespace llvm {
315
316class WebAssemblyFrameLowering;
317
318struct WebAssemblyGenRegisterInfo : public TargetRegisterInfo {
319 explicit WebAssemblyGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
320 unsigned PC = 0, unsigned HwMode = 0);
321 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
322 unsigned getRegUnitWeight(unsigned RegUnit) const override;
323 unsigned getNumRegPressureSets() const override;
324 const char *getRegPressureSetName(unsigned Idx) const override;
325 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
326 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
327 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
328 ArrayRef<const char *> getRegMaskNames() const override;
329 ArrayRef<const uint32_t *> getRegMasks() const override;
330 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
331 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
332 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
333 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
334 bool isConstantPhysReg(MCRegister PhysReg) const override final;
335 /// Devirtualized TargetFrameLowering.
336 static const WebAssemblyFrameLowering *getFrameLowering(
337 const MachineFunction &MF);
338};
339
340namespace WebAssembly { // Register classes
341 extern const TargetRegisterClass EXNREFRegClass;
342 extern const TargetRegisterClass EXTERNREFRegClass;
343 extern const TargetRegisterClass FUNCREFRegClass;
344 extern const TargetRegisterClass I32RegClass;
345 extern const TargetRegisterClass F32RegClass;
346 extern const TargetRegisterClass I64RegClass;
347 extern const TargetRegisterClass F64RegClass;
348 extern const TargetRegisterClass V128RegClass;
349} // end namespace WebAssembly
350
351} // end namespace llvm
352
353#endif // GET_REGINFO_HEADER
354
355/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
356|* *|
357|* Target Register and Register Classes Information *|
358|* *|
359|* Automatically generated file, do not edit! *|
360|* *|
361\*===----------------------------------------------------------------------===*/
362
363
364#ifdef GET_REGINFO_TARGET_DESC
365#undef GET_REGINFO_TARGET_DESC
366
367namespace llvm {
368
369extern const MCRegisterClass WebAssemblyMCRegisterClasses[];
370
371static const MVT::SimpleValueType VTLists[] = {
372 /* 0 */ MVT::i32, MVT::Other,
373 /* 2 */ MVT::i64, MVT::Other,
374 /* 4 */ MVT::f32, MVT::Other,
375 /* 6 */ MVT::f64, MVT::Other,
376 /* 8 */ MVT::v2i64, MVT::v4i32, MVT::v16i8, MVT::v8i16, MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::Other,
377 /* 16 */ MVT::funcref, MVT::Other,
378 /* 18 */ MVT::externref, MVT::Other,
379 /* 20 */ MVT::exnref, MVT::Other,
380};
381
382static const char *SubRegIndexNameTable[] = { "" };
383
384static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
385 { 65535, 65535 },
386};
387
388
389static const LaneBitmask SubRegIndexLaneMaskTable[] = {
390 LaneBitmask::getAll(),
391 };
392
393
394
395static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
396 // Mode = 0 (Default)
397 { 0, 0, 0, /*VTLists+*/20 }, // EXNREF
398 { 0, 0, 0, /*VTLists+*/18 }, // EXTERNREF
399 { 0, 0, 0, /*VTLists+*/16 }, // FUNCREF
400 { 32, 32, 32, /*VTLists+*/0 }, // I32
401 { 32, 32, 32, /*VTLists+*/4 }, // F32
402 { 64, 64, 64, /*VTLists+*/2 }, // I64
403 { 64, 64, 64, /*VTLists+*/6 }, // F64
404 { 128, 128, 128, /*VTLists+*/8 }, // V128
405};
406static const uint32_t EXNREFSubClassMask[] = {
407 0x00000001,
408};
409
410static const uint32_t EXTERNREFSubClassMask[] = {
411 0x00000002,
412};
413
414static const uint32_t FUNCREFSubClassMask[] = {
415 0x00000004,
416};
417
418static const uint32_t I32SubClassMask[] = {
419 0x00000008,
420};
421
422static const uint32_t F32SubClassMask[] = {
423 0x00000010,
424};
425
426static const uint32_t I64SubClassMask[] = {
427 0x00000020,
428};
429
430static const uint32_t F64SubClassMask[] = {
431 0x00000040,
432};
433
434static const uint32_t V128SubClassMask[] = {
435 0x00000080,
436};
437
438static const uint16_t SuperRegIdxSeqs[] = {
439 /* 0 */ 0,
440};
441
442
443namespace WebAssembly { // Register class instances
444 extern const TargetRegisterClass EXNREFRegClass = {
445 &WebAssemblyMCRegisterClasses[EXNREFRegClassID],
446 EXNREFSubClassMask,
447 SuperRegIdxSeqs + 0,
448 LaneBitmask(0x0000000000000001),
449 0,
450 false,
451 0x00, /* TSFlags */
452 false, /* HasDisjunctSubRegs */
453 false, /* CoveredBySubRegs */
454 nullptr, 0,
455 nullptr
456 };
457
458 extern const TargetRegisterClass EXTERNREFRegClass = {
459 &WebAssemblyMCRegisterClasses[EXTERNREFRegClassID],
460 EXTERNREFSubClassMask,
461 SuperRegIdxSeqs + 0,
462 LaneBitmask(0x0000000000000001),
463 0,
464 false,
465 0x00, /* TSFlags */
466 false, /* HasDisjunctSubRegs */
467 false, /* CoveredBySubRegs */
468 nullptr, 0,
469 nullptr
470 };
471
472 extern const TargetRegisterClass FUNCREFRegClass = {
473 &WebAssemblyMCRegisterClasses[FUNCREFRegClassID],
474 FUNCREFSubClassMask,
475 SuperRegIdxSeqs + 0,
476 LaneBitmask(0x0000000000000001),
477 0,
478 false,
479 0x00, /* TSFlags */
480 false, /* HasDisjunctSubRegs */
481 false, /* CoveredBySubRegs */
482 nullptr, 0,
483 nullptr
484 };
485
486 extern const TargetRegisterClass I32RegClass = {
487 &WebAssemblyMCRegisterClasses[I32RegClassID],
488 I32SubClassMask,
489 SuperRegIdxSeqs + 0,
490 LaneBitmask(0x0000000000000001),
491 0,
492 false,
493 0x00, /* TSFlags */
494 false, /* HasDisjunctSubRegs */
495 false, /* CoveredBySubRegs */
496 nullptr, 0,
497 nullptr
498 };
499
500 extern const TargetRegisterClass F32RegClass = {
501 &WebAssemblyMCRegisterClasses[F32RegClassID],
502 F32SubClassMask,
503 SuperRegIdxSeqs + 0,
504 LaneBitmask(0x0000000000000001),
505 0,
506 false,
507 0x00, /* TSFlags */
508 false, /* HasDisjunctSubRegs */
509 false, /* CoveredBySubRegs */
510 nullptr, 0,
511 nullptr
512 };
513
514 extern const TargetRegisterClass I64RegClass = {
515 &WebAssemblyMCRegisterClasses[I64RegClassID],
516 I64SubClassMask,
517 SuperRegIdxSeqs + 0,
518 LaneBitmask(0x0000000000000001),
519 0,
520 false,
521 0x00, /* TSFlags */
522 false, /* HasDisjunctSubRegs */
523 false, /* CoveredBySubRegs */
524 nullptr, 0,
525 nullptr
526 };
527
528 extern const TargetRegisterClass F64RegClass = {
529 &WebAssemblyMCRegisterClasses[F64RegClassID],
530 F64SubClassMask,
531 SuperRegIdxSeqs + 0,
532 LaneBitmask(0x0000000000000001),
533 0,
534 false,
535 0x00, /* TSFlags */
536 false, /* HasDisjunctSubRegs */
537 false, /* CoveredBySubRegs */
538 nullptr, 0,
539 nullptr
540 };
541
542 extern const TargetRegisterClass V128RegClass = {
543 &WebAssemblyMCRegisterClasses[V128RegClassID],
544 V128SubClassMask,
545 SuperRegIdxSeqs + 0,
546 LaneBitmask(0x0000000000000001),
547 0,
548 false,
549 0x00, /* TSFlags */
550 false, /* HasDisjunctSubRegs */
551 false, /* CoveredBySubRegs */
552 nullptr, 0,
553 nullptr
554 };
555
556} // end namespace WebAssembly
557
558namespace {
559 const TargetRegisterClass *const RegisterClasses[] = {
560 &WebAssembly::EXNREFRegClass,
561 &WebAssembly::EXTERNREFRegClass,
562 &WebAssembly::FUNCREFRegClass,
563 &WebAssembly::I32RegClass,
564 &WebAssembly::F32RegClass,
565 &WebAssembly::I64RegClass,
566 &WebAssembly::F64RegClass,
567 &WebAssembly::V128RegClass,
568 };
569} // end anonymous namespace
570
571static const uint8_t CostPerUseTable[] = {
5720, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
573
574
575static const bool InAllocatableClassTable[] = {
576false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
577
578
579static const TargetRegisterInfoDesc WebAssemblyRegInfoDesc = { // Extra Descriptors
580CostPerUseTable, 1, InAllocatableClassTable};
581
582/// Get the weight in units of pressure for this register class.
583const RegClassWeight &WebAssemblyGenRegisterInfo::
584getRegClassWeight(const TargetRegisterClass *RC) const {
585 static const RegClassWeight RCWeightTable[] = {
586 {1, 1}, // EXNREF
587 {1, 1}, // EXTERNREF
588 {1, 1}, // FUNCREF
589 {1, 3}, // I32
590 {1, 1}, // F32
591 {1, 3}, // I64
592 {1, 1}, // F64
593 {1, 1}, // V128
594 };
595 return RCWeightTable[RC->getID()];
596}
597
598/// Get the weight in units of pressure for this register unit.
599unsigned WebAssemblyGenRegisterInfo::
600getRegUnitWeight(unsigned RegUnit) const {
601 assert(RegUnit < 14 && "invalid register unit");
602 // All register units have unit weight.
603 return 1;
604}
605
606
607// Get the number of dimensions of register pressure.
608unsigned WebAssemblyGenRegisterInfo::getNumRegPressureSets() const {
609 return 8;
610}
611
612// Get the name of this register unit pressure set.
613const char *WebAssemblyGenRegisterInfo::
614getRegPressureSetName(unsigned Idx) const {
615 static const char *PressureNameTable[] = {
616 "EXNREF",
617 "EXTERNREF",
618 "FUNCREF",
619 "F32",
620 "F64",
621 "V128",
622 "I32",
623 "I64",
624 };
625 return PressureNameTable[Idx];
626}
627
628// Get the register unit pressure limit for this dimension.
629// This limit must be adjusted dynamically for reserved registers.
630unsigned WebAssemblyGenRegisterInfo::
631getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
632 static const uint8_t PressureLimitTable[] = {
633 1, // 0: EXNREF
634 1, // 1: EXTERNREF
635 1, // 2: FUNCREF
636 1, // 3: F32
637 1, // 4: F64
638 1, // 5: V128
639 3, // 6: I32
640 3, // 7: I64
641 };
642 return PressureLimitTable[Idx];
643}
644
645/// Table of pressure sets per register class or unit.
646static const int RCSetsTable[] = {
647 /* 0 */ 0, -1,
648 /* 2 */ 1, -1,
649 /* 4 */ 2, -1,
650 /* 6 */ 3, -1,
651 /* 8 */ 4, -1,
652 /* 10 */ 5, -1,
653 /* 12 */ 6, -1,
654 /* 14 */ 7, -1,
655};
656
657/// Get the dimensions of register pressure impacted by this register class.
658/// Returns a -1 terminated array of pressure set IDs
659const int *WebAssemblyGenRegisterInfo::
660getRegClassPressureSets(const TargetRegisterClass *RC) const {
661 static const uint8_t RCSetStartTable[] = {
662 0,2,4,12,6,14,8,10,};
663 return &RCSetsTable[RCSetStartTable[RC->getID()]];
664}
665
666/// Get the dimensions of register pressure impacted by this register unit.
667/// Returns a -1 terminated array of pressure set IDs
668const int *WebAssemblyGenRegisterInfo::
669getRegUnitPressureSets(unsigned RegUnit) const {
670 assert(RegUnit < 14 && "invalid register unit");
671 static const uint8_t RUSetStartTable[] = {
672 1,1,0,2,12,14,4,12,14,6,8,12,14,10,};
673 return &RCSetsTable[RUSetStartTable[RegUnit]];
674}
675
676extern const MCRegisterDesc WebAssemblyRegDesc[];
677extern const int16_t WebAssemblyRegDiffLists[];
678extern const LaneBitmask WebAssemblyLaneMaskLists[];
679extern const char WebAssemblyRegStrings[];
680extern const char WebAssemblyRegClassStrings[];
681extern const MCPhysReg WebAssemblyRegUnitRoots[][2];
682extern const uint16_t WebAssemblySubRegIdxLists[];
683extern const uint16_t WebAssemblyRegEncodingTable[];
684WebAssemblyGenRegisterInfo::
685WebAssemblyGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
686 unsigned PC, unsigned HwMode)
687 : TargetRegisterInfo(&WebAssemblyRegInfoDesc, RegisterClasses, RegisterClasses+8,
688 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
689 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
690 InitMCRegisterInfo(WebAssemblyRegDesc, 15, RA, PC,
691 WebAssemblyMCRegisterClasses, 8,
692 WebAssemblyRegUnitRoots,
693 14,
694 WebAssemblyRegDiffLists,
695 WebAssemblyLaneMaskLists,
696 WebAssemblyRegStrings,
697 WebAssemblyRegClassStrings,
698 WebAssemblySubRegIdxLists,
699 1,
700 WebAssemblyRegEncodingTable);
701
702}
703
704
705
706ArrayRef<const uint32_t *> WebAssemblyGenRegisterInfo::getRegMasks() const {
707 return {};
708}
709
710bool WebAssemblyGenRegisterInfo::
711isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
712 return
713 false;
714}
715
716bool WebAssemblyGenRegisterInfo::
717isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
718 return
719 false;
720}
721
722bool WebAssemblyGenRegisterInfo::
723isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
724 return
725 false;
726}
727
728bool WebAssemblyGenRegisterInfo::
729isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
730 return
731 false;
732}
733
734bool WebAssemblyGenRegisterInfo::
735isConstantPhysReg(MCRegister PhysReg) const {
736 return
737 false;
738}
739
740ArrayRef<const char *> WebAssemblyGenRegisterInfo::getRegMaskNames() const {
741 return {};
742}
743
744const WebAssemblyFrameLowering *
745WebAssemblyGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
746 return static_cast<const WebAssemblyFrameLowering *>(
747 MF.getSubtarget().getFrameLowering());
748}
749
750} // end namespace llvm
751
752#endif // GET_REGINFO_TARGET_DESC
753
754