1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace WebAssembly {
15enum {
16 FeatureAtomics = 0,
17 FeatureBulkMemory = 1,
18 FeatureBulkMemoryOpt = 2,
19 FeatureCallIndirectOverlong = 3,
20 FeatureExceptionHandling = 4,
21 FeatureExtendedConst = 5,
22 FeatureFP16 = 6,
23 FeatureMultiMemory = 7,
24 FeatureMultivalue = 8,
25 FeatureMutableGlobals = 9,
26 FeatureNontrappingFPToInt = 10,
27 FeatureReferenceTypes = 11,
28 FeatureRelaxedSIMD = 12,
29 FeatureSIMD128 = 13,
30 FeatureSignExt = 14,
31 FeatureTailCall = 15,
32 FeatureWideArithmetic = 16,
33 NumSubtargetFeatures = 17
34};
35} // end namespace WebAssembly
36} // end namespace llvm
37
38#endif // GET_SUBTARGETINFO_ENUM
39
40
41#ifdef GET_SUBTARGETINFO_MACRO
42GET_SUBTARGETINFO_MACRO(HasAtomics, false, hasAtomics)
43GET_SUBTARGETINFO_MACRO(HasBulkMemory, false, hasBulkMemory)
44GET_SUBTARGETINFO_MACRO(HasBulkMemoryOpt, false, hasBulkMemoryOpt)
45GET_SUBTARGETINFO_MACRO(HasCallIndirectOverlong, false, hasCallIndirectOverlong)
46GET_SUBTARGETINFO_MACRO(HasExceptionHandling, false, hasExceptionHandling)
47GET_SUBTARGETINFO_MACRO(HasExtendedConst, false, hasExtendedConst)
48GET_SUBTARGETINFO_MACRO(HasFP16, false, hasFP16)
49GET_SUBTARGETINFO_MACRO(HasMultiMemory, false, hasMultiMemory)
50GET_SUBTARGETINFO_MACRO(HasMultivalue, false, hasMultivalue)
51GET_SUBTARGETINFO_MACRO(HasMutableGlobals, false, hasMutableGlobals)
52GET_SUBTARGETINFO_MACRO(HasNontrappingFPToInt, false, hasNontrappingFPToInt)
53GET_SUBTARGETINFO_MACRO(HasReferenceTypes, false, hasReferenceTypes)
54GET_SUBTARGETINFO_MACRO(HasSignExt, false, hasSignExt)
55GET_SUBTARGETINFO_MACRO(HasTailCall, false, hasTailCall)
56GET_SUBTARGETINFO_MACRO(HasWideArithmetic, false, hasWideArithmetic)
57#undef GET_SUBTARGETINFO_MACRO
58#endif // GET_SUBTARGETINFO_MACRO
59
60
61#ifdef GET_SUBTARGETINFO_MC_DESC
62#undef GET_SUBTARGETINFO_MC_DESC
63
64namespace llvm {
65// Sorted (by key) array of values for CPU features.
66extern const llvm::SubtargetFeatureKV WebAssemblyFeatureKV[] = {
67 { "atomics", "Enable Atomics", WebAssembly::FeatureAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
68 { "bulk-memory", "Enable bulk memory operations", WebAssembly::FeatureBulkMemory, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
69 { "bulk-memory-opt", "Enable bulk memory optimization operations", WebAssembly::FeatureBulkMemoryOpt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
70 { "call-indirect-overlong", "Enable overlong encoding for call_indirect immediates", WebAssembly::FeatureCallIndirectOverlong, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
71 { "exception-handling", "Enable Wasm exception handling", WebAssembly::FeatureExceptionHandling, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
72 { "extended-const", "Enable extended const expressions", WebAssembly::FeatureExtendedConst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
73 { "fp16", "Enable FP16 instructions", WebAssembly::FeatureFP16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
74 { "multimemory", "Enable multiple memories", WebAssembly::FeatureMultiMemory, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
75 { "multivalue", "Enable multivalue blocks, instructions, and functions", WebAssembly::FeatureMultivalue, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
76 { "mutable-globals", "Enable mutable globals", WebAssembly::FeatureMutableGlobals, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
77 { "nontrapping-fptoint", "Enable non-trapping float-to-int conversion operators", WebAssembly::FeatureNontrappingFPToInt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78 { "reference-types", "Enable reference types", WebAssembly::FeatureReferenceTypes, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
79 { "relaxed-simd", "Enable relaxed-simd instructions", WebAssembly::FeatureRelaxedSIMD, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
80 { "sign-ext", "Enable sign extension operators", WebAssembly::FeatureSignExt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
81 { "simd128", "Enable 128-bit SIMD", WebAssembly::FeatureSIMD128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
82 { "tail-call", "Enable tail call instructions", WebAssembly::FeatureTailCall, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
83 { "wide-arithmetic", "Enable wide-arithmetic instructions", WebAssembly::FeatureWideArithmetic, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84};
85
86#ifdef DBGFIELD
87#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
88#endif
89#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
90#define DBGFIELD(x) x,
91#define DBGVAL_OR_NULLPTR(x) x
92#else
93#define DBGFIELD(x)
94#define DBGVAL_OR_NULLPTR(x) nullptr
95#endif
96
97// ===============================================================
98// Data tables for the new per-operand machine model.
99
100// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
101extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[] = {
102 { 0, 0, 0 }, // Invalid
103}; // WebAssemblyWriteProcResTable
104
105// {Cycles, WriteResourceID}
106extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[] = {
107 { 0, 0}, // Invalid
108}; // WebAssemblyWriteLatencyTable
109
110// {UseIdx, WriteResourceID, Cycles}
111extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[] = {
112 {0, 0, 0}, // Invalid
113}; // WebAssemblyReadAdvanceTable
114
115#ifdef __GNUC__
116#pragma GCC diagnostic push
117#pragma GCC diagnostic ignored "-Woverlength-strings"
118#endif
119static constexpr char WebAssemblySchedClassNamesStorage[] =
120 "\0"
121 "InvalidSchedClass\0"
122 ;
123#ifdef __GNUC__
124#pragma GCC diagnostic pop
125#endif
126
127static constexpr llvm::StringTable WebAssemblySchedClassNames =
128 WebAssemblySchedClassNamesStorage;
129
130static const llvm::MCSchedModel NoSchedModel = {
131 MCSchedModel::DefaultIssueWidth,
132 MCSchedModel::DefaultMicroOpBufferSize,
133 MCSchedModel::DefaultLoopMicroOpBufferSize,
134 MCSchedModel::DefaultLoadLatency,
135 MCSchedModel::DefaultHighLatency,
136 MCSchedModel::DefaultMispredictPenalty,
137 false, // PostRAScheduler
138 false, // CompleteModel
139 false, // EnableIntervals
140 0, // Processor ID
141 nullptr, nullptr, 0, 0, // No instruction-level machine model.
142 DBGVAL_OR_NULLPTR(&WebAssemblySchedClassNames), // SchedClassNames
143 nullptr, // No Itinerary
144 nullptr // No extra processor descriptor
145};
146
147#undef DBGFIELD
148
149#undef DBGVAL_OR_NULLPTR
150
151// Sorted (by key) array of values for CPU subtype.
152extern const llvm::SubtargetSubTypeKV WebAssemblySubTypeKV[] = {
153 { "bleeding-edge", { { { 0xffffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
154 { "generic", { { { 0x4f0eULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
155 { "lime1", { { { 0x472cULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
156 { "mvp", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
157};
158
159// Sorted array of names of CPU subtypes, including aliases.
160extern const llvm::StringRef WebAssemblyNames[] = {
161"bleeding-edge",
162"generic",
163"lime1",
164"mvp"};
165
166namespace WebAssembly_MC {
167unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
168 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
169 // Don't know how to resolve this scheduling class.
170 return 0;
171}
172} // end namespace WebAssembly_MC
173
174struct WebAssemblyGenMCSubtargetInfo : public MCSubtargetInfo {
175 WebAssemblyGenMCSubtargetInfo(const Triple &TT,
176 StringRef CPU, StringRef TuneCPU, StringRef FS,
177 ArrayRef<StringRef> PN,
178 ArrayRef<SubtargetFeatureKV> PF,
179 ArrayRef<SubtargetSubTypeKV> PD,
180 const MCWriteProcResEntry *WPR,
181 const MCWriteLatencyEntry *WL,
182 const MCReadAdvanceEntry *RA, const InstrStage *IS,
183 const unsigned *OC, const unsigned *FP) :
184 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
185 WPR, WL, RA, IS, OC, FP) { }
186
187 unsigned resolveVariantSchedClass(unsigned SchedClass,
188 const MCInst *MI, const MCInstrInfo *MCII,
189 unsigned CPUID) const override {
190 return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
191 }
192};
193
194static inline MCSubtargetInfo *createWebAssemblyMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
195 return new WebAssemblyGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, WebAssemblyNames, WebAssemblyFeatureKV, WebAssemblySubTypeKV,
196 WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
197 nullptr, nullptr, nullptr);
198}
199
200} // end namespace llvm
201
202#endif // GET_SUBTARGETINFO_MC_DESC
203
204
205#ifdef GET_SUBTARGETINFO_TARGET_DESC
206#undef GET_SUBTARGETINFO_TARGET_DESC
207
208#include "llvm/ADT/BitmaskEnum.h"
209#include "llvm/Support/Debug.h"
210#include "llvm/Support/raw_ostream.h"
211
212// ParseSubtargetFeatures - Parses features string setting specified
213// subtarget options.
214void llvm::WebAssemblySubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
215 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
216 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
217 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
218 InitMCProcessorInfo(CPU, TuneCPU, FS);
219 const FeatureBitset &Bits = getFeatureBits();
220 if (Bits[WebAssembly::FeatureAtomics]) HasAtomics = true;
221 if (Bits[WebAssembly::FeatureBulkMemory]) HasBulkMemory = true;
222 if (Bits[WebAssembly::FeatureBulkMemoryOpt]) HasBulkMemoryOpt = true;
223 if (Bits[WebAssembly::FeatureCallIndirectOverlong]) HasCallIndirectOverlong = true;
224 if (Bits[WebAssembly::FeatureExceptionHandling]) HasExceptionHandling = true;
225 if (Bits[WebAssembly::FeatureExtendedConst]) HasExtendedConst = true;
226 if (Bits[WebAssembly::FeatureFP16]) HasFP16 = true;
227 if (Bits[WebAssembly::FeatureMultiMemory]) HasMultiMemory = true;
228 if (Bits[WebAssembly::FeatureMultivalue]) HasMultivalue = true;
229 if (Bits[WebAssembly::FeatureMutableGlobals]) HasMutableGlobals = true;
230 if (Bits[WebAssembly::FeatureNontrappingFPToInt]) HasNontrappingFPToInt = true;
231 if (Bits[WebAssembly::FeatureReferenceTypes]) HasReferenceTypes = true;
232 if (Bits[WebAssembly::FeatureRelaxedSIMD] && SIMDLevel < RelaxedSIMD) SIMDLevel = RelaxedSIMD;
233 if (Bits[WebAssembly::FeatureSIMD128] && SIMDLevel < SIMD128) SIMDLevel = SIMD128;
234 if (Bits[WebAssembly::FeatureSignExt]) HasSignExt = true;
235 if (Bits[WebAssembly::FeatureTailCall]) HasTailCall = true;
236 if (Bits[WebAssembly::FeatureWideArithmetic]) HasWideArithmetic = true;
237}
238#endif // GET_SUBTARGETINFO_TARGET_DESC
239
240
241#ifdef GET_SUBTARGETINFO_HEADER
242#undef GET_SUBTARGETINFO_HEADER
243
244namespace llvm {
245class DFAPacketizer;
246namespace WebAssembly_MC {
247unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
248} // end namespace WebAssembly_MC
249
250struct WebAssemblyGenSubtargetInfo : public TargetSubtargetInfo {
251 explicit WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
252public:
253 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
254 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
255 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
256};
257} // end namespace llvm
258
259#endif // GET_SUBTARGETINFO_HEADER
260
261
262#ifdef GET_SUBTARGETINFO_CTOR
263#undef GET_SUBTARGETINFO_CTOR
264
265#include "llvm/CodeGen/TargetSchedule.h"
266
267namespace llvm {
268extern const llvm::StringRef WebAssemblyNames[];
269extern const llvm::SubtargetFeatureKV WebAssemblyFeatureKV[];
270extern const llvm::SubtargetSubTypeKV WebAssemblySubTypeKV[];
271extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[];
272extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[];
273extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[];
274WebAssemblyGenSubtargetInfo::WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
275 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(WebAssemblyNames, 4), ArrayRef(WebAssemblyFeatureKV, 17), ArrayRef(WebAssemblySubTypeKV, 4),
276 WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
277 nullptr, nullptr, nullptr) {}
278
279unsigned WebAssemblyGenSubtargetInfo
280::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
281 report_fatal_error("Expected a variant SchedClass");
282} // WebAssemblyGenSubtargetInfo::resolveSchedClass
283
284unsigned WebAssemblyGenSubtargetInfo
285::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
286 return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
287} // WebAssemblyGenSubtargetInfo::resolveVariantSchedClass
288
289} // end namespace llvm
290
291#endif // GET_SUBTARGETINFO_CTOR
292
293
294#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
295#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
296
297#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
298
299
300#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
301#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
302
303#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
304
305