1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace X86 {
13enum : unsigned {
14 InvalidRegBankID = ~0u,
15 GPRRegBankID = 0,
16 PSRRegBankID = 1,
17 VECRRegBankID = 2,
18 NumRegisterBanks,
19};
20} // end namespace X86
21} // end namespace llvm
22#endif // GET_REGBANK_DECLARATIONS
23
24#ifdef GET_TARGET_REGBANK_CLASS
25#undef GET_TARGET_REGBANK_CLASS
26private:
27 static const RegisterBank *RegBanks[];
28 static const unsigned Sizes[];
29
30public:
31 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
32protected:
33 X86GenRegisterBankInfo(unsigned HwMode = 0);
34
35#endif // GET_TARGET_REGBANK_CLASS
36
37#ifdef GET_TARGET_REGBANK_IMPL
38#undef GET_TARGET_REGBANK_IMPL
39namespace llvm {
40namespace X86 {
41const uint32_t GPRRegBankCoverageData[] = {
42 // 0-31
43 (1u << (X86::GR8RegClassID - 0)) |
44 (1u << (X86::GR16RegClassID - 0)) |
45 (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) |
46 (1u << (X86::GR8_NOREX2RegClassID - 0)) |
47 (1u << (X86::GR16_NOREX2RegClassID - 0)) |
48 (1u << (X86::GR8_NOREXRegClassID - 0)) |
49 (1u << (X86::GR8_ABCD_HRegClassID - 0)) |
50 (1u << (X86::GR8_ABCD_LRegClassID - 0)) |
51 (1u << (X86::GR16_NOREXRegClassID - 0)) |
52 (1u << (X86::GR16_ABCDRegClassID - 0)) |
53 0,
54 // 32-63
55 (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 32)) |
56 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 32)) |
57 (1u << (X86::GR32RegClassID - 32)) |
58 (1u << (X86::GR32_NOSPRegClassID - 32)) |
59 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID - 32)) |
60 (1u << (X86::GR32_NOREX2RegClassID - 32)) |
61 (1u << (X86::GR32_NOREX2_NOSPRegClassID - 32)) |
62 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID - 32)) |
63 (1u << (X86::GR32_NOREXRegClassID - 32)) |
64 (1u << (X86::GR32_NOREX_NOSPRegClassID - 32)) |
65 (1u << (X86::GR32_ABCDRegClassID - 32)) |
66 (1u << (X86::GR32_TCRegClassID - 32)) |
67 (1u << (X86::GR32_ABCD_and_GR32_TCRegClassID - 32)) |
68 (1u << (X86::GR32_ADRegClassID - 32)) |
69 (1u << (X86::GR32_ArgRefRegClassID - 32)) |
70 (1u << (X86::GR32_DCRegClassID - 32)) |
71 (1u << (X86::GR32_AD_and_GR32_ArgRefRegClassID - 32)) |
72 (1u << (X86::GR32_CBRegClassID - 32)) |
73 (1u << (X86::GR32_SIDIRegClassID - 32)) |
74 (1u << (X86::GR32_BSIRegClassID - 32)) |
75 (1u << (X86::GR32_DIBPRegClassID - 32)) |
76 (1u << (X86::GR32_ABCD_and_GR32_BSIRegClassID - 32)) |
77 (1u << (X86::GR32_BPSPRegClassID - 32)) |
78 0,
79 // 64-95
80 (1u << (X86::GR64RegClassID - 64)) |
81 (1u << (X86::GR64_with_sub_8bitRegClassID - 64)) |
82 (1u << (X86::GR64_NOSPRegClassID - 64)) |
83 (1u << (X86::GR64_NOREX2_NOSPRegClassID - 64)) |
84 (1u << (X86::GR64PLTSafeRegClassID - 64)) |
85 (1u << (X86::GR64PLTSafe_and_GR64_TCRegClassID - 64)) |
86 (1u << (X86::GR32_ArgRef_and_GR32_CBRegClassID - 64)) |
87 (1u << (X86::GR32_BSI_and_GR32_SIDIRegClassID - 64)) |
88 (1u << (X86::GR32_DIBP_and_GR32_SIDIRegClassID - 64)) |
89 (1u << (X86::GR64_NOREX_NOSPRegClassID - 64)) |
90 (1u << (X86::GR32_BPSP_and_GR32_DIBPRegClassID - 64)) |
91 (1u << (X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID - 64)) |
92 (1u << (X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID - 64)) |
93 (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID - 64)) |
94 (1u << (X86::GR64_TC_with_sub_8bitRegClassID - 64)) |
95 (1u << (X86::GR32_BPSP_and_GR32_TCRegClassID - 64)) |
96 (1u << (X86::GR64_TCW64_with_sub_8bitRegClassID - 64)) |
97 (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 64)) |
98 (1u << (X86::GR64_NOREX2RegClassID - 64)) |
99 (1u << (X86::GR64_TCRegClassID - 64)) |
100 (1u << (X86::GR64_TC_and_GR64_TCW64RegClassID - 64)) |
101 (1u << (X86::GR64_NOREX_and_GR64_TCRegClassID - 64)) |
102 (1u << (X86::GR64_NOREXRegClassID - 64)) |
103 (1u << (X86::GR64_TCW64RegClassID - 64)) |
104 0,
105 // 96-127
106 (1u << (X86::GR64PLTSafe_and_GR64_TCW64RegClassID - 96)) |
107 (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID - 96)) |
108 (1u << (X86::GR64_ADRegClassID - 96)) |
109 (1u << (X86::GR64_ARegClassID - 96)) |
110 (1u << (X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID - 96)) |
111 (1u << (X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID - 96)) |
112 (1u << (X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID - 96)) |
113 (1u << (X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID - 96)) |
114 (1u << (X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID - 96)) |
115 (1u << (X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID - 96)) |
116 (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID - 96)) |
117 (1u << (X86::GR64_ABCDRegClassID - 96)) |
118 (1u << (X86::GR64_with_sub_32bit_in_GR32_CBRegClassID - 96)) |
119 (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID - 96)) |
120 (1u << (X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID - 96)) |
121 (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID - 96)) |
122 (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID - 96)) |
123 (1u << (X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID - 96)) |
124 (1u << (X86::GR64_ArgRef_and_GR64_TCRegClassID - 96)) |
125 (1u << (X86::GR64_ArgRefRegClassID - 96)) |
126 (1u << (X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID - 96)) |
127 (1u << (X86::GR64_with_sub_32bit_in_GR32_TCRegClassID - 96)) |
128 (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID - 96)) |
129 (1u << (X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 96)) |
130 (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID - 96)) |
131 (1u << (X86::GR64_NOREX_and_GR64_TCW64RegClassID - 96)) |
132 (1u << (X86::GR64_and_LOW32_ADDR_ACCESSRegClassID - 96)) |
133 (1u << (X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID - 96)) |
134 0,
135 // 128-159
136 0,
137};
138const uint32_t PSRRegBankCoverageData[] = {
139 // 0-31
140 0,
141 // 32-63
142 (1u << (X86::RFP32RegClassID - 32)) |
143 0,
144 // 64-95
145 (1u << (X86::RFP64RegClassID - 64)) |
146 0,
147 // 96-127
148 (1u << (X86::RFP80RegClassID - 96)) |
149 0,
150 // 128-159
151 0,
152};
153const uint32_t VECRRegBankCoverageData[] = {
154 // 0-31
155 (1u << (X86::FR16XRegClassID - 0)) |
156 (1u << (X86::FR16RegClassID - 0)) |
157 0,
158 // 32-63
159 (1u << (X86::FR32XRegClassID - 32)) |
160 (1u << (X86::FR32RegClassID - 32)) |
161 0,
162 // 64-95
163 (1u << (X86::FR64XRegClassID - 64)) |
164 (1u << (X86::FR64RegClassID - 64)) |
165 0,
166 // 96-127
167 0,
168 // 128-159
169 (1u << (X86::VR512RegClassID - 128)) |
170 (1u << (X86::VR128XRegClassID - 128)) |
171 (1u << (X86::VR256XRegClassID - 128)) |
172 (1u << (X86::VR512_0_15RegClassID - 128)) |
173 (1u << (X86::VR128RegClassID - 128)) |
174 (1u << (X86::VR256RegClassID - 128)) |
175 0,
176};
177
178constexpr RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 136);
179constexpr RegisterBank PSRRegBank(/* ID */ X86::PSRRegBankID, /* Name */ "PSR", /* CoveredRegClasses */ PSRRegBankCoverageData, /* NumRegClasses */ 136);
180constexpr RegisterBank VECRRegBank(/* ID */ X86::VECRRegBankID, /* Name */ "VECR", /* CoveredRegClasses */ VECRRegBankCoverageData, /* NumRegClasses */ 136);
181} // end namespace X86
182
183const RegisterBank *X86GenRegisterBankInfo::RegBanks[] = {
184 &X86::GPRRegBank,
185 &X86::PSRRegBank,
186 &X86::VECRRegBank,
187};
188
189const unsigned X86GenRegisterBankInfo::Sizes[] = {
190 // Mode = 0 (Default)
191 64,
192 80,
193 512,
194};
195
196X86GenRegisterBankInfo::X86GenRegisterBankInfo(unsigned HwMode)
197 : RegisterBankInfo(RegBanks, X86::NumRegisterBanks, Sizes, HwMode) {
198 // Assert that RegBank indices match their ID's
199#ifndef NDEBUG
200 for (auto RB : enumerate(RegBanks))
201 assert(RB.index() == RB.value()->getID() && "Index != ID");
202#endif // NDEBUG
203}
204const RegisterBank &
205X86GenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
206 constexpr uint32_t InvalidRegBankID = uint32_t(X86::InvalidRegBankID) & 3;
207 static const uint32_t RegClass2RegBank[9] = {
208 (uint32_t(X86::GPRRegBankID) << 0) | // GR8RegClassID
209 (uint32_t(InvalidRegBankID) << 2) |
210 (uint32_t(X86::GPRRegBankID) << 4) | // GR8_NOREX2RegClassID
211 (uint32_t(X86::GPRRegBankID) << 6) | // GR8_NOREXRegClassID
212 (uint32_t(X86::GPRRegBankID) << 8) | // GR8_ABCD_HRegClassID
213 (uint32_t(X86::GPRRegBankID) << 10) | // GR8_ABCD_LRegClassID
214 (uint32_t(InvalidRegBankID) << 12) |
215 (uint32_t(X86::GPRRegBankID) << 14) | // GR16RegClassID
216 (uint32_t(X86::GPRRegBankID) << 16) | // GR16_NOREX2RegClassID
217 (uint32_t(X86::GPRRegBankID) << 18) | // GR16_NOREXRegClassID
218 (uint32_t(InvalidRegBankID) << 20) |
219 (uint32_t(InvalidRegBankID) << 22) |
220 (uint32_t(InvalidRegBankID) << 24) |
221 (uint32_t(InvalidRegBankID) << 26) |
222 (uint32_t(InvalidRegBankID) << 28) |
223 (uint32_t(InvalidRegBankID) << 30),
224 (uint32_t(InvalidRegBankID) << 0) |
225 (uint32_t(InvalidRegBankID) << 2) |
226 (uint32_t(InvalidRegBankID) << 4) |
227 (uint32_t(InvalidRegBankID) << 6) |
228 (uint32_t(InvalidRegBankID) << 8) |
229 (uint32_t(X86::GPRRegBankID) << 10) | // GR16_ABCDRegClassID
230 (uint32_t(InvalidRegBankID) << 12) |
231 (uint32_t(X86::VECRRegBankID) << 14) | // FR16XRegClassID
232 (uint32_t(X86::VECRRegBankID) << 16) | // FR16RegClassID
233 (uint32_t(InvalidRegBankID) << 18) |
234 (uint32_t(InvalidRegBankID) << 20) |
235 (uint32_t(InvalidRegBankID) << 22) |
236 (uint32_t(InvalidRegBankID) << 24) |
237 (uint32_t(InvalidRegBankID) << 26) |
238 (uint32_t(InvalidRegBankID) << 28) |
239 (uint32_t(X86::GPRRegBankID) << 30), // LOW32_ADDR_ACCESS_RBPRegClassID
240 (uint32_t(X86::GPRRegBankID) << 0) | // LOW32_ADDR_ACCESSRegClassID
241 (uint32_t(X86::GPRRegBankID) << 2) | // LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID
242 (uint32_t(X86::VECRRegBankID) << 4) | // FR32XRegClassID
243 (uint32_t(X86::GPRRegBankID) << 6) | // GR32RegClassID
244 (uint32_t(X86::GPRRegBankID) << 8) | // GR32_NOSPRegClassID
245 (uint32_t(X86::GPRRegBankID) << 10) | // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID
246 (uint32_t(InvalidRegBankID) << 12) |
247 (uint32_t(X86::VECRRegBankID) << 14) | // FR32RegClassID
248 (uint32_t(X86::GPRRegBankID) << 16) | // GR32_NOREX2RegClassID
249 (uint32_t(X86::GPRRegBankID) << 18) | // GR32_NOREX2_NOSPRegClassID
250 (uint32_t(X86::GPRRegBankID) << 20) | // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID
251 (uint32_t(X86::GPRRegBankID) << 22) | // GR32_NOREXRegClassID
252 (uint32_t(InvalidRegBankID) << 24) |
253 (uint32_t(X86::GPRRegBankID) << 26) | // GR32_NOREX_NOSPRegClassID
254 (uint32_t(X86::PSRRegBankID) << 28) | // RFP32RegClassID
255 (uint32_t(InvalidRegBankID) << 30),
256 (uint32_t(X86::GPRRegBankID) << 0) | // GR32_ABCDRegClassID
257 (uint32_t(X86::GPRRegBankID) << 2) | // GR32_TCRegClassID
258 (uint32_t(X86::GPRRegBankID) << 4) | // GR32_ABCD_and_GR32_TCRegClassID
259 (uint32_t(X86::GPRRegBankID) << 6) | // GR32_ADRegClassID
260 (uint32_t(X86::GPRRegBankID) << 8) | // GR32_ArgRefRegClassID
261 (uint32_t(X86::GPRRegBankID) << 10) | // GR32_BPSPRegClassID
262 (uint32_t(X86::GPRRegBankID) << 12) | // GR32_BSIRegClassID
263 (uint32_t(X86::GPRRegBankID) << 14) | // GR32_CBRegClassID
264 (uint32_t(X86::GPRRegBankID) << 16) | // GR32_DCRegClassID
265 (uint32_t(X86::GPRRegBankID) << 18) | // GR32_DIBPRegClassID
266 (uint32_t(X86::GPRRegBankID) << 20) | // GR32_SIDIRegClassID
267 (uint32_t(InvalidRegBankID) << 22) |
268 (uint32_t(InvalidRegBankID) << 24) |
269 (uint32_t(InvalidRegBankID) << 26) |
270 (uint32_t(X86::GPRRegBankID) << 28) | // GR32_ABCD_and_GR32_BSIRegClassID
271 (uint32_t(X86::GPRRegBankID) << 30), // GR32_AD_and_GR32_ArgRefRegClassID
272 (uint32_t(X86::GPRRegBankID) << 0) | // GR32_ArgRef_and_GR32_CBRegClassID
273 (uint32_t(X86::GPRRegBankID) << 2) | // GR32_BPSP_and_GR32_DIBPRegClassID
274 (uint32_t(X86::GPRRegBankID) << 4) | // GR32_BPSP_and_GR32_TCRegClassID
275 (uint32_t(X86::GPRRegBankID) << 6) | // GR32_BSI_and_GR32_SIDIRegClassID
276 (uint32_t(X86::GPRRegBankID) << 8) | // GR32_DIBP_and_GR32_SIDIRegClassID
277 (uint32_t(InvalidRegBankID) << 10) |
278 (uint32_t(InvalidRegBankID) << 12) |
279 (uint32_t(X86::PSRRegBankID) << 14) | // RFP64RegClassID
280 (uint32_t(X86::GPRRegBankID) << 16) | // GR64RegClassID
281 (uint32_t(X86::VECRRegBankID) << 18) | // FR64XRegClassID
282 (uint32_t(X86::GPRRegBankID) << 20) | // GR64_with_sub_8bitRegClassID
283 (uint32_t(X86::GPRRegBankID) << 22) | // GR64_NOSPRegClassID
284 (uint32_t(X86::GPRRegBankID) << 24) | // GR64_NOREX2RegClassID
285 (uint32_t(InvalidRegBankID) << 26) |
286 (uint32_t(X86::VECRRegBankID) << 28) | // FR64RegClassID
287 (uint32_t(X86::GPRRegBankID) << 30), // GR64_with_sub_16bit_in_GR16_NOREX2RegClassID
288 (uint32_t(X86::GPRRegBankID) << 0) | // GR64_NOREX2_NOSPRegClassID
289 (uint32_t(X86::GPRRegBankID) << 2) | // GR64PLTSafeRegClassID
290 (uint32_t(X86::GPRRegBankID) << 4) | // GR64_TCRegClassID
291 (uint32_t(X86::GPRRegBankID) << 6) | // GR64_NOREXRegClassID
292 (uint32_t(X86::GPRRegBankID) << 8) | // GR64_TCW64RegClassID
293 (uint32_t(X86::GPRRegBankID) << 10) | // GR64_TC_with_sub_8bitRegClassID
294 (uint32_t(X86::GPRRegBankID) << 12) | // GR64_NOREX2_NOSP_and_GR64_TCRegClassID
295 (uint32_t(X86::GPRRegBankID) << 14) | // GR64_TCW64_with_sub_8bitRegClassID
296 (uint32_t(X86::GPRRegBankID) << 16) | // GR64_TC_and_GR64_TCW64RegClassID
297 (uint32_t(X86::GPRRegBankID) << 18) | // GR64_with_sub_16bit_in_GR16_NOREXRegClassID
298 (uint32_t(InvalidRegBankID) << 20) |
299 (uint32_t(InvalidRegBankID) << 22) |
300 (uint32_t(X86::GPRRegBankID) << 24) | // GR64PLTSafe_and_GR64_TCRegClassID
301 (uint32_t(X86::GPRRegBankID) << 26) | // GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID
302 (uint32_t(X86::GPRRegBankID) << 28) | // GR64_NOREX_NOSPRegClassID
303 (uint32_t(X86::GPRRegBankID) << 30), // GR64_NOREX_and_GR64_TCRegClassID
304 (uint32_t(X86::GPRRegBankID) << 0) | // GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID
305 (uint32_t(InvalidRegBankID) << 2) |
306 (uint32_t(X86::GPRRegBankID) << 4) | // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID
307 (uint32_t(X86::GPRRegBankID) << 6) | // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID
308 (uint32_t(X86::GPRRegBankID) << 8) | // GR64PLTSafe_and_GR64_TCW64RegClassID
309 (uint32_t(X86::GPRRegBankID) << 10) | // GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID
310 (uint32_t(X86::GPRRegBankID) << 12) | // GR64_NOREX_and_GR64_TCW64RegClassID
311 (uint32_t(X86::GPRRegBankID) << 14) | // GR64_ABCDRegClassID
312 (uint32_t(X86::GPRRegBankID) << 16) | // GR64_with_sub_32bit_in_GR32_TCRegClassID
313 (uint32_t(X86::GPRRegBankID) << 18) | // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID
314 (uint32_t(X86::GPRRegBankID) << 20) | // GR64_ADRegClassID
315 (uint32_t(X86::GPRRegBankID) << 22) | // GR64_ArgRefRegClassID
316 (uint32_t(X86::GPRRegBankID) << 24) | // GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID
317 (uint32_t(X86::GPRRegBankID) << 26) | // GR64_with_sub_32bit_in_GR32_ArgRefRegClassID
318 (uint32_t(X86::GPRRegBankID) << 28) | // GR64_with_sub_32bit_in_GR32_BPSPRegClassID
319 (uint32_t(X86::GPRRegBankID) << 30), // GR64_with_sub_32bit_in_GR32_BSIRegClassID
320 (uint32_t(X86::GPRRegBankID) << 0) | // GR64_with_sub_32bit_in_GR32_CBRegClassID
321 (uint32_t(X86::GPRRegBankID) << 2) | // GR64_with_sub_32bit_in_GR32_DIBPRegClassID
322 (uint32_t(X86::GPRRegBankID) << 4) | // GR64_with_sub_32bit_in_GR32_SIDIRegClassID
323 (uint32_t(X86::GPRRegBankID) << 6) | // GR64_ARegClassID
324 (uint32_t(X86::GPRRegBankID) << 8) | // GR64_ArgRef_and_GR64_TCRegClassID
325 (uint32_t(X86::GPRRegBankID) << 10) | // GR64_and_LOW32_ADDR_ACCESSRegClassID
326 (uint32_t(X86::GPRRegBankID) << 12) | // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID
327 (uint32_t(X86::GPRRegBankID) << 14) | // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID
328 (uint32_t(X86::GPRRegBankID) << 16) | // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID
329 (uint32_t(X86::GPRRegBankID) << 18) | // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID
330 (uint32_t(X86::GPRRegBankID) << 20) | // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID
331 (uint32_t(X86::GPRRegBankID) << 22) | // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID
332 (uint32_t(X86::GPRRegBankID) << 24) | // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID
333 (uint32_t(InvalidRegBankID) << 26) |
334 (uint32_t(X86::PSRRegBankID) << 28) | // RFP80RegClassID
335 (uint32_t(InvalidRegBankID) << 30),
336 (uint32_t(X86::VECRRegBankID) << 0) | // VR128XRegClassID
337 (uint32_t(X86::VECRRegBankID) << 2) | // VR128RegClassID
338 (uint32_t(X86::VECRRegBankID) << 4) | // VR256XRegClassID
339 (uint32_t(X86::VECRRegBankID) << 6) | // VR256RegClassID
340 (uint32_t(X86::VECRRegBankID) << 8) | // VR512RegClassID
341 (uint32_t(X86::VECRRegBankID) << 10) // VR512_0_15RegClassID
342 };
343 const unsigned RegClassID = RC.getID();
344 if (LLVM_LIKELY(RegClassID < 134)) {
345 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
346 if (RegBankID != InvalidRegBankID)
347 return getRegBank(RegBankID);
348 }
349 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
350}
351} // end namespace llvm
352#endif // GET_TARGET_REGBANK_IMPL
353