XCoreGenInstrInfo.inc source code [llvm_projects/build/lib/Target/XCore/XCoreGenInstrInfo.inc]

1	/===- TableGen'erated file -------------------------------------- C++ --===\
2	\| \|
3	\| Target Instruction Enum Values and Descriptors \|
4	\| \|
5	\| Automatically generated file, do not edit! \|
6	\| \|
7	\===----------------------------------------------------------------------===/
8
9	#ifdef GET_INSTRINFO_ENUM
10	#undef GET_INSTRINFO_ENUM
11	namespace llvm::XCore {
12	enum {
13	PHI = `0`,
14	INLINEASM = `1`,
15	INLINEASM_BR = `2`,
16	CFI_INSTRUCTION = `3`,
17	EH_LABEL = `4`,
18	GC_LABEL = `5`,
19	ANNOTATION_LABEL = `6`,
20	KILL = `7`,
21	EXTRACT_SUBREG = `8`,
22	INSERT_SUBREG = `9`,
23	IMPLICIT_DEF = `10`,
24	INIT_UNDEF = `11`,
25	SUBREG_TO_REG = `12`,
26	COPY_TO_REGCLASS = `13`,
27	DBG_VALUE = `14`,
28	DBG_VALUE_LIST = `15`,
29	DBG_INSTR_REF = `16`,
30	DBG_PHI = `17`,
31	DBG_LABEL = `18`,
32	REG_SEQUENCE = `19`,
33	COPY = `20`,
34	BUNDLE = `21`,
35	LIFETIME_START = `22`,
36	LIFETIME_END = `23`,
37	PSEUDO_PROBE = `24`,
38	ARITH_FENCE = `25`,
39	STACKMAP = `26`,
40	FENTRY_CALL = `27`,
41	PATCHPOINT = `28`,
42	LOAD_STACK_GUARD = `29`,
43	PREALLOCATED_SETUP = `30`,
44	PREALLOCATED_ARG = `31`,
45	STATEPOINT = `32`,
46	LOCAL_ESCAPE = `33`,
47	FAULTING_OP = `34`,
48	PATCHABLE_OP = `35`,
49	PATCHABLE_FUNCTION_ENTER = `36`,
50	PATCHABLE_RET = `37`,
51	PATCHABLE_FUNCTION_EXIT = `38`,
52	PATCHABLE_TAIL_CALL = `39`,
53	PATCHABLE_EVENT_CALL = `40`,
54	PATCHABLE_TYPED_EVENT_CALL = `41`,
55	ICALL_BRANCH_FUNNEL = `42`,
56	FAKE_USE = `43`,
57	MEMBARRIER = `44`,
58	JUMP_TABLE_DEBUG_INFO = `45`,
59	CONVERGENCECTRL_ENTRY = `46`,
60	CONVERGENCECTRL_ANCHOR = `47`,
61	CONVERGENCECTRL_LOOP = `48`,
62	CONVERGENCECTRL_GLUE = `49`,
63	G_ASSERT_SEXT = `50`,
64	G_ASSERT_ZEXT = `51`,
65	G_ASSERT_ALIGN = `52`,
66	G_ADD = `53`,
67	G_SUB = `54`,
68	G_MUL = `55`,
69	G_SDIV = `56`,
70	G_UDIV = `57`,
71	G_SREM = `58`,
72	G_UREM = `59`,
73	G_SDIVREM = `60`,
74	G_UDIVREM = `61`,
75	G_AND = `62`,
76	G_OR = `63`,
77	G_XOR = `64`,
78	G_ABDS = `65`,
79	G_ABDU = `66`,
80	G_IMPLICIT_DEF = `67`,
81	G_PHI = `68`,
82	G_FRAME_INDEX = `69`,
83	G_GLOBAL_VALUE = `70`,
84	G_PTRAUTH_GLOBAL_VALUE = `71`,
85	G_CONSTANT_POOL = `72`,
86	G_EXTRACT = `73`,
87	G_UNMERGE_VALUES = `74`,
88	G_INSERT = `75`,
89	G_MERGE_VALUES = `76`,
90	G_BUILD_VECTOR = `77`,
91	G_BUILD_VECTOR_TRUNC = `78`,
92	G_CONCAT_VECTORS = `79`,
93	G_PTRTOINT = `80`,
94	G_INTTOPTR = `81`,
95	G_BITCAST = `82`,
96	G_FREEZE = `83`,
97	G_CONSTANT_FOLD_BARRIER = `84`,
98	G_INTRINSIC_FPTRUNC_ROUND = `85`,
99	G_INTRINSIC_TRUNC = `86`,
100	G_INTRINSIC_ROUND = `87`,
101	G_INTRINSIC_LRINT = `88`,
102	G_INTRINSIC_LLRINT = `89`,
103	G_INTRINSIC_ROUNDEVEN = `90`,
104	G_READCYCLECOUNTER = `91`,
105	G_READSTEADYCOUNTER = `92`,
106	G_LOAD = `93`,
107	G_SEXTLOAD = `94`,
108	G_ZEXTLOAD = `95`,
109	G_INDEXED_LOAD = `96`,
110	G_INDEXED_SEXTLOAD = `97`,
111	G_INDEXED_ZEXTLOAD = `98`,
112	G_STORE = `99`,
113	G_INDEXED_STORE = `100`,
114	G_ATOMIC_CMPXCHG_WITH_SUCCESS = `101`,
115	G_ATOMIC_CMPXCHG = `102`,
116	G_ATOMICRMW_XCHG = `103`,
117	G_ATOMICRMW_ADD = `104`,
118	G_ATOMICRMW_SUB = `105`,
119	G_ATOMICRMW_AND = `106`,
120	G_ATOMICRMW_NAND = `107`,
121	G_ATOMICRMW_OR = `108`,
122	G_ATOMICRMW_XOR = `109`,
123	G_ATOMICRMW_MAX = `110`,
124	G_ATOMICRMW_MIN = `111`,
125	G_ATOMICRMW_UMAX = `112`,
126	G_ATOMICRMW_UMIN = `113`,
127	G_ATOMICRMW_FADD = `114`,
128	G_ATOMICRMW_FSUB = `115`,
129	G_ATOMICRMW_FMAX = `116`,
130	G_ATOMICRMW_FMIN = `117`,
131	G_ATOMICRMW_FMAXIMUM = `118`,
132	G_ATOMICRMW_FMINIMUM = `119`,
133	G_ATOMICRMW_UINC_WRAP = `120`,
134	G_ATOMICRMW_UDEC_WRAP = `121`,
135	G_ATOMICRMW_USUB_COND = `122`,
136	G_ATOMICRMW_USUB_SAT = `123`,
137	G_FENCE = `124`,
138	G_PREFETCH = `125`,
139	G_BRCOND = `126`,
140	G_BRINDIRECT = `127`,
141	G_INVOKE_REGION_START = `128`,
142	G_INTRINSIC = `129`,
143	G_INTRINSIC_W_SIDE_EFFECTS = `130`,
144	G_INTRINSIC_CONVERGENT = `131`,
145	G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = `132`,
146	G_ANYEXT = `133`,
147	G_TRUNC = `134`,
148	G_CONSTANT = `135`,
149	G_FCONSTANT = `136`,
150	G_VASTART = `137`,
151	G_VAARG = `138`,
152	G_SEXT = `139`,
153	G_SEXT_INREG = `140`,
154	G_ZEXT = `141`,
155	G_SHL = `142`,
156	G_LSHR = `143`,
157	G_ASHR = `144`,
158	G_FSHL = `145`,
159	G_FSHR = `146`,
160	G_ROTR = `147`,
161	G_ROTL = `148`,
162	G_ICMP = `149`,
163	G_FCMP = `150`,
164	G_SCMP = `151`,
165	G_UCMP = `152`,
166	G_SELECT = `153`,
167	G_UADDO = `154`,
168	G_UADDE = `155`,
169	G_USUBO = `156`,
170	G_USUBE = `157`,
171	G_SADDO = `158`,
172	G_SADDE = `159`,
173	G_SSUBO = `160`,
174	G_SSUBE = `161`,
175	G_UMULO = `162`,
176	G_SMULO = `163`,
177	G_UMULH = `164`,
178	G_SMULH = `165`,
179	G_UADDSAT = `166`,
180	G_SADDSAT = `167`,
181	G_USUBSAT = `168`,
182	G_SSUBSAT = `169`,
183	G_USHLSAT = `170`,
184	G_SSHLSAT = `171`,
185	G_SMULFIX = `172`,
186	G_UMULFIX = `173`,
187	G_SMULFIXSAT = `174`,
188	G_UMULFIXSAT = `175`,
189	G_SDIVFIX = `176`,
190	G_UDIVFIX = `177`,
191	G_SDIVFIXSAT = `178`,
192	G_UDIVFIXSAT = `179`,
193	G_FADD = `180`,
194	G_FSUB = `181`,
195	G_FMUL = `182`,
196	G_FMA = `183`,
197	G_FMAD = `184`,
198	G_FDIV = `185`,
199	G_FREM = `186`,
200	G_FPOW = `187`,
201	G_FPOWI = `188`,
202	G_FEXP = `189`,
203	G_FEXP2 = `190`,
204	G_FEXP10 = `191`,
205	G_FLOG = `192`,
206	G_FLOG2 = `193`,
207	G_FLOG10 = `194`,
208	G_FLDEXP = `195`,
209	G_FFREXP = `196`,
210	G_FNEG = `197`,
211	G_FPEXT = `198`,
212	G_FPTRUNC = `199`,
213	G_FPTOSI = `200`,
214	G_FPTOUI = `201`,
215	G_SITOFP = `202`,
216	G_UITOFP = `203`,
217	G_FPTOSI_SAT = `204`,
218	G_FPTOUI_SAT = `205`,
219	G_FABS = `206`,
220	G_FCOPYSIGN = `207`,
221	G_IS_FPCLASS = `208`,
222	G_FCANONICALIZE = `209`,
223	G_FMINNUM = `210`,
224	G_FMAXNUM = `211`,
225	G_FMINNUM_IEEE = `212`,
226	G_FMAXNUM_IEEE = `213`,
227	G_FMINIMUM = `214`,
228	G_FMAXIMUM = `215`,
229	G_FMINIMUMNUM = `216`,
230	G_FMAXIMUMNUM = `217`,
231	G_GET_FPENV = `218`,
232	G_SET_FPENV = `219`,
233	G_RESET_FPENV = `220`,
234	G_GET_FPMODE = `221`,
235	G_SET_FPMODE = `222`,
236	G_RESET_FPMODE = `223`,
237	G_PTR_ADD = `224`,
238	G_PTRMASK = `225`,
239	G_SMIN = `226`,
240	G_SMAX = `227`,
241	G_UMIN = `228`,
242	G_UMAX = `229`,
243	G_ABS = `230`,
244	G_LROUND = `231`,
245	G_LLROUND = `232`,
246	G_BR = `233`,
247	G_BRJT = `234`,
248	G_VSCALE = `235`,
249	G_INSERT_SUBVECTOR = `236`,
250	G_EXTRACT_SUBVECTOR = `237`,
251	G_INSERT_VECTOR_ELT = `238`,
252	G_EXTRACT_VECTOR_ELT = `239`,
253	G_SHUFFLE_VECTOR = `240`,
254	G_SPLAT_VECTOR = `241`,
255	G_STEP_VECTOR = `242`,
256	G_VECTOR_COMPRESS = `243`,
257	G_CTTZ = `244`,
258	G_CTTZ_ZERO_UNDEF = `245`,
259	G_CTLZ = `246`,
260	G_CTLZ_ZERO_UNDEF = `247`,
261	G_CTPOP = `248`,
262	G_BSWAP = `249`,
263	G_BITREVERSE = `250`,
264	G_FCEIL = `251`,
265	G_FCOS = `252`,
266	G_FSIN = `253`,
267	G_FSINCOS = `254`,
268	G_FTAN = `255`,
269	G_FACOS = `256`,
270	G_FASIN = `257`,
271	G_FATAN = `258`,
272	G_FATAN2 = `259`,
273	G_FCOSH = `260`,
274	G_FSINH = `261`,
275	G_FTANH = `262`,
276	G_FSQRT = `263`,
277	G_FFLOOR = `264`,
278	G_FRINT = `265`,
279	G_FNEARBYINT = `266`,
280	G_ADDRSPACE_CAST = `267`,
281	G_BLOCK_ADDR = `268`,
282	G_JUMP_TABLE = `269`,
283	G_DYN_STACKALLOC = `270`,
284	G_STACKSAVE = `271`,
285	G_STACKRESTORE = `272`,
286	G_STRICT_FADD = `273`,
287	G_STRICT_FSUB = `274`,
288	G_STRICT_FMUL = `275`,
289	G_STRICT_FDIV = `276`,
290	G_STRICT_FREM = `277`,
291	G_STRICT_FMA = `278`,
292	G_STRICT_FSQRT = `279`,
293	G_STRICT_FLDEXP = `280`,
294	G_READ_REGISTER = `281`,
295	G_WRITE_REGISTER = `282`,
296	G_MEMCPY = `283`,
297	G_MEMCPY_INLINE = `284`,
298	G_MEMMOVE = `285`,
299	G_MEMSET = `286`,
300	G_BZERO = `287`,
301	G_TRAP = `288`,
302	G_DEBUGTRAP = `289`,
303	G_UBSANTRAP = `290`,
304	G_VECREDUCE_SEQ_FADD = `291`,
305	G_VECREDUCE_SEQ_FMUL = `292`,
306	G_VECREDUCE_FADD = `293`,
307	G_VECREDUCE_FMUL = `294`,
308	G_VECREDUCE_FMAX = `295`,
309	G_VECREDUCE_FMIN = `296`,
310	G_VECREDUCE_FMAXIMUM = `297`,
311	G_VECREDUCE_FMINIMUM = `298`,
312	G_VECREDUCE_ADD = `299`,
313	G_VECREDUCE_MUL = `300`,
314	G_VECREDUCE_AND = `301`,
315	G_VECREDUCE_OR = `302`,
316	G_VECREDUCE_XOR = `303`,
317	G_VECREDUCE_SMAX = `304`,
318	G_VECREDUCE_SMIN = `305`,
319	G_VECREDUCE_UMAX = `306`,
320	G_VECREDUCE_UMIN = `307`,
321	G_SBFX = `308`,
322	G_UBFX = `309`,
323	ADJCALLSTACKDOWN = `310`,
324	ADJCALLSTACKUP = `311`,
325	BR_JT = `312`,
326	BR_JT32 = `313`,
327	EH_RETURN = `314`,
328	FRAME_TO_ARGS_OFFSET = `315`,
329	LDAWFI = `316`,
330	LDWFI = `317`,
331	SELECT_CC = `318`,
332	STWFI = `319`,
333	ADD_2rus = `320`,
334	ADD_3r = `321`,
335	ANDNOT_2r = `322`,
336	AND_3r = `323`,
337	ASHR_l2rus = `324`,
338	ASHR_l3r = `325`,
339	BAU_1r = `326`,
340	BITREV_l2r = `327`,
341	BLACP_lu10 = `328`,
342	BLACP_u10 = `329`,
343	BLAT_lu6 = `330`,
344	BLAT_u6 = `331`,
345	BLA_1r = `332`,
346	BLRB_lu10 = `333`,
347	BLRB_u10 = `334`,
348	BLRF_lu10 = `335`,
349	BLRF_u10 = `336`,
350	BRBF_lru6 = `337`,
351	BRBF_ru6 = `338`,
352	BRBT_lru6 = `339`,
353	BRBT_ru6 = `340`,
354	BRBU_lu6 = `341`,
355	BRBU_u6 = `342`,
356	BRFF_lru6 = `343`,
357	BRFF_ru6 = `344`,
358	BRFT_lru6 = `345`,
359	BRFT_ru6 = `346`,
360	BRFU_lu6 = `347`,
361	BRFU_u6 = `348`,
362	BRU_1r = `349`,
363	BYTEREV_l2r = `350`,
364	CHKCT_2r = `351`,
365	CHKCT_rus = `352`,
366	CLRE_0R = `353`,
367	CLRPT_1R = `354`,
368	CLRSR_branch_lu6 = `355`,
369	CLRSR_branch_u6 = `356`,
370	CLRSR_lu6 = `357`,
371	CLRSR_u6 = `358`,
372	CLZ_l2r = `359`,
373	CRC8_l4r = `360`,
374	CRC_l3r = `361`,
375	DCALL_0R = `362`,
376	DENTSP_0R = `363`,
377	DGETREG_1r = `364`,
378	DIVS_l3r = `365`,
379	DIVU_l3r = `366`,
380	DRESTSP_0R = `367`,
381	DRET_0R = `368`,
382	ECALLF_1r = `369`,
383	ECALLT_1r = `370`,
384	EDU_1r = `371`,
385	EEF_2r = `372`,
386	EET_2r = `373`,
387	EEU_1r = `374`,
388	ENDIN_2r = `375`,
389	ENTSP_lu6 = `376`,
390	ENTSP_u6 = `377`,
391	EQ_2rus = `378`,
392	EQ_3r = `379`,
393	EXTDP_lu6 = `380`,
394	EXTDP_u6 = `381`,
395	EXTSP_lu6 = `382`,
396	EXTSP_u6 = `383`,
397	FREER_1r = `384`,
398	FREET_0R = `385`,
399	GETD_l2r = `386`,
400	GETED_0R = `387`,
401	GETET_0R = `388`,
402	GETID_0R = `389`,
403	GETKEP_0R = `390`,
404	GETKSP_0R = `391`,
405	GETN_l2r = `392`,
406	GETPS_l2r = `393`,
407	GETR_rus = `394`,
408	GETSR_lu6 = `395`,
409	GETSR_u6 = `396`,
410	GETST_2r = `397`,
411	GETTS_2r = `398`,
412	INCT_2r = `399`,
413	INITCP_2r = `400`,
414	INITDP_2r = `401`,
415	INITLR_l2r = `402`,
416	INITPC_2r = `403`,
417	INITSP_2r = `404`,
418	INPW_l2rus = `405`,
419	INSHR_2r = `406`,
420	INT_2r = `407`,
421	IN_2r = `408`,
422	KCALL_1r = `409`,
423	KCALL_lu6 = `410`,
424	KCALL_u6 = `411`,
425	KENTSP_lu6 = `412`,
426	KENTSP_u6 = `413`,
427	KRESTSP_lu6 = `414`,
428	KRESTSP_u6 = `415`,
429	KRET_0R = `416`,
430	LADD_l5r = `417`,
431	LD16S_3r = `418`,
432	LD8U_3r = `419`,
433	LDA16B_l3r = `420`,
434	LDA16F_l3r = `421`,
435	LDAPB_lu10 = `422`,
436	LDAPB_u10 = `423`,
437	LDAPF_lu10 = `424`,
438	LDAPF_lu10_ba = `425`,
439	LDAPF_u10 = `426`,
440	LDAWB_l2rus = `427`,
441	LDAWB_l3r = `428`,
442	LDAWCP_lu6 = `429`,
443	LDAWCP_u6 = `430`,
444	LDAWDP_lru6 = `431`,
445	LDAWDP_ru6 = `432`,
446	LDAWF_l2rus = `433`,
447	LDAWF_l3r = `434`,
448	LDAWSP_lru6 = `435`,
449	LDAWSP_ru6 = `436`,
450	LDC_lru6 = `437`,
451	LDC_ru6 = `438`,
452	LDET_0R = `439`,
453	LDIVU_l5r = `440`,
454	LDSED_0R = `441`,
455	LDSPC_0R = `442`,
456	LDSSR_0R = `443`,
457	LDWCP_lru6 = `444`,
458	LDWCP_lu10 = `445`,
459	LDWCP_ru6 = `446`,
460	LDWCP_u10 = `447`,
461	LDWDP_lru6 = `448`,
462	LDWDP_ru6 = `449`,
463	LDWSP_lru6 = `450`,
464	LDWSP_ru6 = `451`,
465	LDW_2rus = `452`,
466	LDW_3r = `453`,
467	LMUL_l6r = `454`,
468	LSS_3r = `455`,
469	LSUB_l5r = `456`,
470	LSU_3r = `457`,
471	MACCS_l4r = `458`,
472	MACCU_l4r = `459`,
473	MJOIN_1r = `460`,
474	MKMSK_2r = `461`,
475	MKMSK_rus = `462`,
476	MSYNC_1r = `463`,
477	MUL_l3r = `464`,
478	NEG = `465`,
479	NOT = `466`,
480	OR_3r = `467`,
481	OUTCT_2r = `468`,
482	OUTCT_rus = `469`,
483	OUTPW_l2rus = `470`,
484	OUTSHR_2r = `471`,
485	OUTT_2r = `472`,
486	OUT_2r = `473`,
487	PEEK_2r = `474`,
488	REMS_l3r = `475`,
489	REMU_l3r = `476`,
490	RETSP_lu6 = `477`,
491	RETSP_u6 = `478`,
492	SETCLK_l2r = `479`,
493	SETCP_1r = `480`,
494	SETC_l2r = `481`,
495	SETC_lru6 = `482`,
496	SETC_ru6 = `483`,
497	SETDP_1r = `484`,
498	SETD_2r = `485`,
499	SETEV_1r = `486`,
500	SETKEP_0R = `487`,
501	SETN_l2r = `488`,
502	SETPSC_2r = `489`,
503	SETPS_l2r = `490`,
504	SETPT_2r = `491`,
505	SETRDY_l2r = `492`,
506	SETSP_1r = `493`,
507	SETSR_branch_lu6 = `494`,
508	SETSR_branch_u6 = `495`,
509	SETSR_lu6 = `496`,
510	SETSR_u6 = `497`,
511	SETTW_l2r = `498`,
512	SETV_1r = `499`,
513	SEXT_2r = `500`,
514	SEXT_rus = `501`,
515	SHL_2rus = `502`,
516	SHL_3r = `503`,
517	SHR_2rus = `504`,
518	SHR_3r = `505`,
519	SSYNC_0r = `506`,
520	ST16_l3r = `507`,
521	ST8_l3r = `508`,
522	STET_0R = `509`,
523	STSED_0R = `510`,
524	STSPC_0R = `511`,
525	STSSR_0R = `512`,
526	STWDP_lru6 = `513`,
527	STWDP_ru6 = `514`,
528	STWSP_lru6 = `515`,
529	STWSP_ru6 = `516`,
530	STW_2rus = `517`,
531	STW_l3r = `518`,
532	SUB_2rus = `519`,
533	SUB_3r = `520`,
534	SYNCR_1r = `521`,
535	TESTCT_2r = `522`,
536	TESTLCL_l2r = `523`,
537	TESTWCT_2r = `524`,
538	TSETMR_2r = `525`,
539	TSETR_3r = `526`,
540	TSTART_1R = `527`,
541	WAITEF_1R = `528`,
542	WAITET_1R = `529`,
543	WAITEU_0R = `530`,
544	XOR_l3r = `531`,
545	ZEXT_2r = `532`,
546	ZEXT_rus = `533`,
547	INSTRUCTION_LIST_END = `534`
548	};
549
550	} // end namespace llvm::XCore
551	#endif // GET_INSTRINFO_ENUM
552
553	#ifdef GET_INSTRINFO_SCHED_ENUM
554	#undef GET_INSTRINFO_SCHED_ENUM
555	namespace llvm::XCore::Sched {
556
557	enum {
558	NoInstrModel = `0`,
559	SCHED_LIST_END = `1`
560	};
561	} // end namespace llvm::XCore::Sched
562	#endif // GET_INSTRINFO_SCHED_ENUM
563
564	#if defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)
565	namespace llvm {
566
567	struct XCoreInstrTable {
568	MCInstrDesc Insts[`534`];
569	static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
570	MCOperandInfo OperandInfo[`213`];
571	static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
572	MCPhysReg ImplicitOps[`11`];
573	};
574
575	} // end namespace llvm
576	#endif // defined(GET_INSTRINFO_MC_DESC) \|\| defined(GET_INSTRINFO_CTOR_DTOR)
577
578	#ifdef GET_INSTRINFO_MC_DESC
579	#undef GET_INSTRINFO_MC_DESC
580	namespace llvm {
581
582	static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == `0`);
583	static constexpr unsigned XCoreImpOpBase = sizeof XCoreInstrTable::OperandInfo / (sizeof(MCPhysReg));
584
585	extern const XCoreInstrTable XCoreDescs = {
586	{
587	{ `533`, `3`, `1`, `2`, `0`, `0`, `0`, `205`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #533 = ZEXT_rus
588	{ `532`, `3`, `1`, `2`, `0`, `0`, `0`, `170`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #532 = ZEXT_2r
589	{ `531`, `3`, `1`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #531 = XOR_l3r
590	{ `530`, `0`, `0`, `2`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #530 = WAITEU_0R
591	{ `529`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #529 = WAITET_1R
592	{ `528`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #528 = WAITEF_1R
593	{ `527`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #527 = TSTART_1R
594	{ `526`, `3`, `0`, `2`, `0`, `0`, `0`, `210`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #526 = TSETR_3r
595	{ `525`, `2`, `0`, `2`, `0`, `0`, `0`, `208`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #525 = TSETMR_2r
596	{ `524`, `2`, `1`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #524 = TESTWCT_2r
597	{ `523`, `2`, `1`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #523 = TESTLCL_l2r
598	{ `522`, `2`, `1`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #522 = TESTCT_2r
599	{ `521`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #521 = SYNCR_1r
600	{ `520`, `3`, `1`, `2`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #520 = SUB_3r
601	{ `519`, `3`, `1`, `2`, `0`, `0`, `0`, `164`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #519 = SUB_2rus
602	{ `518`, `3`, `0`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #518 = STW_l3r
603	{ `517`, `3`, `0`, `2`, `0`, `0`, `0`, `164`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #517 = STW_2rus
604	{ `516`, `2`, `0`, `2`, `0`, `1`, `0`, `191`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #516 = STWSP_ru6
605	{ `515`, `2`, `0`, `4`, `0`, `1`, `0`, `191`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #515 = STWSP_lru6
606	{ `514`, `2`, `0`, `2`, `0`, `0`, `0`, `191`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #514 = STWDP_ru6
607	{ `513`, `2`, `0`, `4`, `0`, `0`, `0`, `191`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #513 = STWDP_lru6
608	{ `512`, `0`, `0`, `2`, `0`, `1`, `0`, `1`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #512 = STSSR_0R
609	{ `511`, `0`, `0`, `2`, `0`, `1`, `0`, `1`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #511 = STSPC_0R
610	{ `510`, `0`, `0`, `2`, `0`, `1`, `0`, `1`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #510 = STSED_0R
611	{ `509`, `0`, `0`, `2`, `0`, `1`, `0`, `1`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #509 = STET_0R
612	{ `508`, `3`, `0`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #508 = ST8_l3r
613	{ `507`, `3`, `0`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #507 = ST16_l3r
614	{ `506`, `0`, `0`, `2`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #506 = SSYNC_0r
615	{ `505`, `3`, `1`, `2`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #505 = SHR_3r
616	{ `504`, `3`, `1`, `2`, `0`, `0`, `0`, `164`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #504 = SHR_2rus
617	{ `503`, `3`, `1`, `2`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #503 = SHL_3r
618	{ `502`, `3`, `1`, `2`, `0`, `0`, `0`, `164`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #502 = SHL_2rus
619	{ `501`, `3`, `1`, `2`, `0`, `0`, `0`, `205`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #501 = SEXT_rus
620	{ `500`, `3`, `1`, `2`, `0`, `0`, `0`, `170`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #500 = SEXT_2r
621	{ `499`, `1`, `0`, `2`, `0`, `1`, `0`, `156`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #499 = SETV_1r
622	{ `498`, `2`, `0`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #498 = SETTW_l2r
623	{ `497`, `1`, `0`, `2`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #497 = SETSR_u6
624	{ `496`, `1`, `0`, `4`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #496 = SETSR_lu6
625	{ `495`, `1`, `0`, `2`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #495 = SETSR_branch_u6
626	{ `494`, `1`, `0`, `4`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #494 = SETSR_branch_lu6
627	{ `493`, `1`, `0`, `2`, `0`, `0`, `1`, `156`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #493 = SETSP_1r
628	{ `492`, `2`, `0`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #492 = SETRDY_l2r
629	{ `491`, `2`, `0`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #491 = SETPT_2r
630	{ `490`, `2`, `0`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #490 = SETPS_l2r
631	{ `489`, `2`, `0`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #489 = SETPSC_2r
632	{ `488`, `2`, `0`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #488 = SETN_l2r
633	{ `487`, `0`, `0`, `2`, `0`, `1`, `0`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #487 = SETKEP_0R
634	{ `486`, `1`, `0`, `2`, `0`, `1`, `0`, `156`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #486 = SETEV_1r
635	{ `485`, `2`, `0`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #485 = SETD_2r
636	{ `484`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #484 = SETDP_1r
637	{ `483`, `2`, `0`, `2`, `0`, `0`, `0`, `175`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #483 = SETC_ru6
638	{ `482`, `2`, `0`, `4`, `0`, `0`, `0`, `175`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #482 = SETC_lru6
639	{ `481`, `2`, `0`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #481 = SETC_l2r
640	{ `480`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #480 = SETCP_1r
641	{ `479`, `2`, `0`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #479 = SETCLK_l2r
642	{ `478`, `1`, `0`, `2`, `0`, `1`, `1`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Return)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #478 = RETSP_u6
643	{ `477`, `1`, `0`, `4`, `0`, `1`, `1`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Return)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #477 = RETSP_lu6
644	{ `476`, `3`, `1`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #476 = REMU_l3r
645	{ `475`, `3`, `1`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #475 = REMS_l3r
646	{ `474`, `2`, `1`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #474 = PEEK_2r
647	{ `473`, `2`, `0`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #473 = OUT_2r
648	{ `472`, `2`, `0`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #472 = OUTT_2r
649	{ `471`, `3`, `1`, `2`, `0`, `0`, `0`, `170`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #471 = OUTSHR_2r
650	{ `470`, `3`, `0`, `4`, `0`, `0`, `0`, `164`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #470 = OUTPW_l2rus
651	{ `469`, `2`, `0`, `2`, `0`, `0`, `0`, `175`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #469 = OUTCT_rus
652	{ `468`, `2`, `0`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #468 = OUTCT_2r
653	{ `467`, `3`, `1`, `2`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #467 = OR_3r
654	{ `466`, `2`, `1`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #466 = NOT
655	{ `465`, `2`, `1`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #465 = NEG
656	{ `464`, `3`, `1`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #464 = MUL_l3r
657	{ `463`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #463 = MSYNC_1r
658	{ `462`, `2`, `1`, `2`, `0`, `0`, `0`, `175`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #462 = MKMSK_rus
659	{ `461`, `2`, `1`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #461 = MKMSK_2r
660	{ `460`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #460 = MJOIN_1r
661	{ `459`, `6`, `2`, `4`, `0`, `0`, `0`, `199`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #459 = MACCU_l4r
662	{ `458`, `6`, `2`, `4`, `0`, `0`, `0`, `199`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #458 = MACCS_l4r
663	{ `457`, `3`, `1`, `2`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #457 = LSU_3r
664	{ `456`, `5`, `2`, `4`, `0`, `0`, `0`, `186`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #456 = LSUB_l5r
665	{ `455`, `3`, `1`, `2`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #455 = LSS_3r
666	{ `454`, `6`, `2`, `4`, `0`, `0`, `0`, `193`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #454 = LMUL_l6r
667	{ `453`, `3`, `1`, `2`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #453 = LDW_3r
668	{ `452`, `3`, `1`, `2`, `0`, `0`, `0`, `164`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #452 = LDW_2rus
669	{ `451`, `2`, `1`, `2`, `0`, `1`, `0`, `191`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #451 = LDWSP_ru6
670	{ `450`, `2`, `1`, `4`, `0`, `1`, `0`, `191`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #450 = LDWSP_lru6
671	{ `449`, `2`, `1`, `2`, `0`, `0`, `0`, `191`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #449 = LDWDP_ru6
672	{ `448`, `2`, `1`, `4`, `0`, `0`, `0`, `191`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #448 = LDWDP_lru6
673	{ `447`, `1`, `0`, `2`, `0`, `0`, `1`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #447 = LDWCP_u10
674	{ `446`, `2`, `1`, `2`, `0`, `0`, `0`, `191`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #446 = LDWCP_ru6
675	{ `445`, `1`, `0`, `4`, `0`, `0`, `1`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #445 = LDWCP_lu10
676	{ `444`, `2`, `1`, `4`, `0`, `0`, `0`, `191`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #444 = LDWCP_lru6
677	{ `443`, `0`, `0`, `2`, `0`, `1`, `0`, `1`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #443 = LDSSR_0R
678	{ `442`, `0`, `0`, `2`, `0`, `1`, `0`, `1`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #442 = LDSPC_0R
679	{ `441`, `0`, `0`, `2`, `0`, `1`, `0`, `1`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #441 = LDSED_0R
680	{ `440`, `5`, `2`, `4`, `0`, `0`, `0`, `186`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #440 = LDIVU_l5r
681	{ `439`, `0`, `0`, `2`, `0`, `1`, `0`, `1`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #439 = LDET_0R
682	{ `438`, `2`, `1`, `2`, `0`, `0`, `0`, `191`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #438 = LDC_ru6
683	{ `437`, `2`, `1`, `4`, `0`, `0`, `0`, `191`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #437 = LDC_lru6
684	{ `436`, `2`, `1`, `2`, `0`, `1`, `0`, `191`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #436 = LDAWSP_ru6
685	{ `435`, `2`, `1`, `4`, `0`, `1`, `0`, `191`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #435 = LDAWSP_lru6
686	{ `434`, `3`, `1`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #434 = LDAWF_l3r
687	{ `433`, `3`, `1`, `4`, `0`, `0`, `0`, `164`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #433 = LDAWF_l2rus
688	{ `432`, `2`, `1`, `2`, `0`, `0`, `0`, `191`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #432 = LDAWDP_ru6
689	{ `431`, `2`, `1`, `4`, `0`, `0`, `0`, `191`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #431 = LDAWDP_lru6
690	{ `430`, `1`, `0`, `2`, `0`, `0`, `1`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #430 = LDAWCP_u6
691	{ `429`, `1`, `0`, `4`, `0`, `0`, `1`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #429 = LDAWCP_lu6
692	{ `428`, `3`, `1`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #428 = LDAWB_l3r
693	{ `427`, `3`, `1`, `4`, `0`, `0`, `0`, `164`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #427 = LDAWB_l2rus
694	{ `426`, `1`, `0`, `2`, `0`, `0`, `1`, `0`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #426 = LDAPF_u10
695	{ `425`, `1`, `0`, `4`, `0`, `0`, `1`, `0`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #425 = LDAPF_lu10_ba
696	{ `424`, `1`, `0`, `4`, `0`, `0`, `1`, `0`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #424 = LDAPF_lu10
697	{ `423`, `1`, `0`, `2`, `0`, `0`, `1`, `0`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #423 = LDAPB_u10
698	{ `422`, `1`, `0`, `4`, `0`, `0`, `1`, `0`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #422 = LDAPB_lu10
699	{ `421`, `3`, `1`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #421 = LDA16F_l3r
700	{ `420`, `3`, `1`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #420 = LDA16B_l3r
701	{ `419`, `3`, `1`, `2`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #419 = LD8U_3r
702	{ `418`, `3`, `1`, `2`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #418 = LD16S_3r
703	{ `417`, `5`, `2`, `4`, `0`, `0`, `0`, `186`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #417 = LADD_l5r
704	{ `416`, `0`, `0`, `2`, `0`, `0`, `1`, `1`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #416 = KRET_0R
705	{ `415`, `1`, `0`, `2`, `0`, `1`, `1`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #415 = KRESTSP_u6
706	{ `414`, `1`, `0`, `4`, `0`, `1`, `1`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #414 = KRESTSP_lu6
707	{ `413`, `1`, `0`, `2`, `0`, `1`, `1`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #413 = KENTSP_u6
708	{ `412`, `1`, `0`, `4`, `0`, `1`, `1`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #412 = KENTSP_lu6
709	{ `411`, `1`, `0`, `2`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #411 = KCALL_u6
710	{ `410`, `1`, `0`, `4`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #410 = KCALL_lu6
711	{ `409`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #409 = KCALL_1r
712	{ `408`, `2`, `1`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #408 = IN_2r
713	{ `407`, `2`, `1`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #407 = INT_2r
714	{ `406`, `3`, `1`, `2`, `0`, `0`, `0`, `170`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #406 = INSHR_2r
715	{ `405`, `3`, `1`, `4`, `0`, `0`, `0`, `164`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #405 = INPW_l2rus
716	{ `404`, `2`, `0`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #404 = INITSP_2r
717	{ `403`, `2`, `0`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #403 = INITPC_2r
718	{ `402`, `2`, `0`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #402 = INITLR_l2r
719	{ `401`, `2`, `0`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #401 = INITDP_2r
720	{ `400`, `2`, `0`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #400 = INITCP_2r
721	{ `399`, `2`, `1`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #399 = INCT_2r
722	{ `398`, `2`, `1`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #398 = GETTS_2r
723	{ `397`, `2`, `1`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #397 = GETST_2r
724	{ `396`, `1`, `0`, `2`, `0`, `0`, `1`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #396 = GETSR_u6
725	{ `395`, `1`, `0`, `4`, `0`, `0`, `1`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #395 = GETSR_lu6
726	{ `394`, `2`, `1`, `2`, `0`, `0`, `0`, `175`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #394 = GETR_rus
727	{ `393`, `2`, `1`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #393 = GETPS_l2r
728	{ `392`, `2`, `1`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #392 = GETN_l2r
729	{ `391`, `0`, `0`, `2`, `0`, `0`, `1`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #391 = GETKSP_0R
730	{ `390`, `0`, `0`, `2`, `0`, `0`, `1`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #390 = GETKEP_0R
731	{ `389`, `0`, `0`, `2`, `0`, `0`, `1`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #389 = GETID_0R
732	{ `388`, `0`, `0`, `2`, `0`, `0`, `1`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #388 = GETET_0R
733	{ `387`, `0`, `0`, `2`, `0`, `0`, `1`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #387 = GETED_0R
734	{ `386`, `2`, `1`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #386 = GETD_l2r
735	{ `385`, `0`, `0`, `2`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #385 = FREET_0R
736	{ `384`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #384 = FREER_1r
737	{ `383`, `1`, `0`, `2`, `0`, `1`, `1`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #383 = EXTSP_u6
738	{ `382`, `1`, `0`, `4`, `0`, `1`, `1`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #382 = EXTSP_lu6
739	{ `381`, `1`, `0`, `2`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #381 = EXTDP_u6
740	{ `380`, `1`, `0`, `4`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #380 = EXTDP_lu6
741	{ `379`, `3`, `1`, `2`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #379 = EQ_3r
742	{ `378`, `3`, `1`, `2`, `0`, `0`, `0`, `164`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #378 = EQ_2rus
743	{ `377`, `1`, `0`, `2`, `0`, `1`, `1`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #377 = ENTSP_u6
744	{ `376`, `1`, `0`, `4`, `0`, `1`, `1`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #376 = ENTSP_lu6
745	{ `375`, `2`, `1`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #375 = ENDIN_2r
746	{ `374`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #374 = EEU_1r
747	{ `373`, `2`, `0`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #373 = EET_2r
748	{ `372`, `2`, `0`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #372 = EEF_2r
749	{ `371`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #371 = EDU_1r
750	{ `370`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #370 = ECALLT_1r
751	{ `369`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #369 = ECALLF_1r
752	{ `368`, `0`, `0`, `2`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #368 = DRET_0R
753	{ `367`, `0`, `0`, `2`, `0`, `0`, `1`, `1`, XCoreImpOpBase + `10`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #367 = DRESTSP_0R
754	{ `366`, `3`, `1`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #366 = DIVU_l3r
755	{ `365`, `3`, `1`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #365 = DIVS_l3r
756	{ `364`, `1`, `1`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #364 = DGETREG_1r
757	{ `363`, `0`, `0`, `2`, `0`, `1`, `1`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #363 = DENTSP_0R
758	{ `362`, `0`, `0`, `2`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #362 = DCALL_0R
759	{ `361`, `4`, `1`, `4`, `0`, `0`, `0`, `182`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #361 = CRC_l3r
760	{ `360`, `5`, `2`, `4`, `0`, `0`, `0`, `177`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #360 = CRC8_l4r
761	{ `359`, `2`, `1`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #359 = CLZ_l2r
762	{ `358`, `1`, `0`, `2`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #358 = CLRSR_u6
763	{ `357`, `1`, `0`, `4`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #357 = CLRSR_lu6
764	{ `356`, `1`, `0`, `2`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #356 = CLRSR_branch_u6
765	{ `355`, `1`, `0`, `4`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #355 = CLRSR_branch_lu6
766	{ `354`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #354 = CLRPT_1R
767	{ `353`, `0`, `0`, `2`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #353 = CLRE_0R
768	{ `352`, `2`, `0`, `2`, `0`, `0`, `0`, `175`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #352 = CHKCT_rus
769	{ `351`, `2`, `0`, `2`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #351 = CHKCT_2r
770	{ `350`, `2`, `1`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #350 = BYTEREV_l2r
771	{ `349`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #349 = BRU_1r
772	{ `348`, `1`, `0`, `2`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #348 = BRFU_u6
773	{ `347`, `1`, `0`, `4`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #347 = BRFU_lu6
774	{ `346`, `2`, `0`, `2`, `0`, `0`, `0`, `173`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #346 = BRFT_ru6
775	{ `345`, `2`, `0`, `4`, `0`, `0`, `0`, `173`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #345 = BRFT_lru6
776	{ `344`, `2`, `0`, `2`, `0`, `0`, `0`, `173`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #344 = BRFF_ru6
777	{ `343`, `2`, `0`, `4`, `0`, `0`, `0`, `173`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #343 = BRFF_lru6
778	{ `342`, `1`, `0`, `2`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #342 = BRBU_u6
779	{ `341`, `1`, `0`, `4`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #341 = BRBU_lu6
780	{ `340`, `2`, `0`, `2`, `0`, `0`, `0`, `173`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #340 = BRBT_ru6
781	{ `339`, `2`, `0`, `4`, `0`, `0`, `0`, `173`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #339 = BRBT_lru6
782	{ `338`, `2`, `0`, `2`, `0`, `0`, `0`, `173`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #338 = BRBF_ru6
783	{ `337`, `2`, `0`, `4`, `0`, `0`, `0`, `173`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #337 = BRBF_lru6
784	{ `336`, `1`, `0`, `2`, `0`, `1`, `6`, `0`, XCoreImpOpBase + `2`, `0`\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #336 = BLRF_u10
785	{ `335`, `1`, `0`, `4`, `0`, `1`, `6`, `0`, XCoreImpOpBase + `2`, `0`\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #335 = BLRF_lu10
786	{ `334`, `1`, `0`, `2`, `0`, `1`, `6`, `0`, XCoreImpOpBase + `2`, `0`\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #334 = BLRB_u10
787	{ `333`, `1`, `0`, `4`, `0`, `1`, `6`, `0`, XCoreImpOpBase + `2`, `0`\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #333 = BLRB_lu10
788	{ `332`, `1`, `0`, `2`, `0`, `1`, `6`, `156`, XCoreImpOpBase + `2`, `0`\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #332 = BLA_1r
789	{ `331`, `1`, `0`, `2`, `0`, `1`, `0`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #331 = BLAT_u6
790	{ `330`, `1`, `0`, `4`, `0`, `1`, `0`, `1`, XCoreImpOpBase + `9`, `0`\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #330 = BLAT_lu6
791	{ `329`, `1`, `0`, `2`, `0`, `1`, `6`, `1`, XCoreImpOpBase + `2`, `0`\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #329 = BLACP_u10
792	{ `328`, `1`, `0`, `4`, `0`, `1`, `6`, `1`, XCoreImpOpBase + `2`, `0`\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #328 = BLACP_lu10
793	{ `327`, `2`, `1`, `4`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #327 = BITREV_l2r
794	{ `326`, `1`, `0`, `2`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #326 = BAU_1r
795	{ `325`, `3`, `1`, `4`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #325 = ASHR_l3r
796	{ `324`, `3`, `1`, `4`, `0`, `0`, `0`, `164`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #324 = ASHR_l2rus
797	{ `323`, `3`, `1`, `2`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #323 = AND_3r
798	{ `322`, `3`, `1`, `2`, `0`, `0`, `0`, `170`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #322 = ANDNOT_2r
799	{ `321`, `3`, `1`, `2`, `0`, `0`, `0`, `167`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #321 = ADD_3r
800	{ `320`, `3`, `1`, `2`, `0`, `0`, `0`, `164`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #320 = ADD_2rus
801	{ `319`, `3`, `0`, `0`, `0`, `0`, `0`, `157`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #319 = STWFI
802	{ `318`, `4`, `1`, `0`, `0`, `0`, `0`, `160`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #318 = SELECT_CC
803	{ `317`, `3`, `1`, `0`, `0`, `0`, `0`, `157`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #317 = LDWFI
804	{ `316`, `3`, `1`, `0`, `0`, `0`, `0`, `157`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #316 = LDAWFI
805	{ `315`, `1`, `1`, `0`, `0`, `0`, `0`, `156`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #315 = FRAME_TO_ARGS_OFFSET
806	{ `314`, `2`, `0`, `0`, `0`, `0`, `0`, `154`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Return)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #314 = EH_RETURN
807	{ `313`, `2`, `0`, `0`, `0`, `0`, `0`, `152`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #313 = BR_JT32
808	{ `312`, `2`, `0`, `0`, `0`, `0`, `0`, `152`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #312 = BR_JT
809	{ `311`, `2`, `0`, `0`, `0`, `1`, `1`, `21`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #311 = ADJCALLSTACKUP
810	{ `310`, `2`, `0`, `0`, `0`, `1`, `1`, `21`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #310 = ADJCALLSTACKDOWN
811	{ `309`, `4`, `1`, `0`, `0`, `0`, `0`, `148`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #309 = G_UBFX
812	{ `308`, `4`, `1`, `0`, `0`, `0`, `0`, `148`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #308 = G_SBFX
813	{ `307`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #307 = G_VECREDUCE_UMIN
814	{ `306`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #306 = G_VECREDUCE_UMAX
815	{ `305`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #305 = G_VECREDUCE_SMIN
816	{ `304`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #304 = G_VECREDUCE_SMAX
817	{ `303`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #303 = G_VECREDUCE_XOR
818	{ `302`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #302 = G_VECREDUCE_OR
819	{ `301`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #301 = G_VECREDUCE_AND
820	{ `300`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #300 = G_VECREDUCE_MUL
821	{ `299`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #299 = G_VECREDUCE_ADD
822	{ `298`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #298 = G_VECREDUCE_FMINIMUM
823	{ `297`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #297 = G_VECREDUCE_FMAXIMUM
824	{ `296`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #296 = G_VECREDUCE_FMIN
825	{ `295`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #295 = G_VECREDUCE_FMAX
826	{ `294`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #294 = G_VECREDUCE_FMUL
827	{ `293`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #293 = G_VECREDUCE_FADD
828	{ `292`, `3`, `1`, `0`, `0`, `0`, `0`, `131`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #292 = G_VECREDUCE_SEQ_FMUL
829	{ `291`, `3`, `1`, `0`, `0`, `0`, `0`, `131`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #291 = G_VECREDUCE_SEQ_FADD
830	{ `290`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #290 = G_UBSANTRAP
831	{ `289`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #289 = G_DEBUGTRAP
832	{ `288`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #288 = G_TRAP
833	{ `287`, `3`, `0`, `0`, `0`, `0`, `0`, `58`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #287 = G_BZERO
834	{ `286`, `4`, `0`, `0`, `0`, `0`, `0`, `144`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #286 = G_MEMSET
835	{ `285`, `4`, `0`, `0`, `0`, `0`, `0`, `144`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #285 = G_MEMMOVE
836	{ `284`, `3`, `0`, `0`, `0`, `0`, `0`, `131`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #284 = G_MEMCPY_INLINE
837	{ `283`, `4`, `0`, `0`, `0`, `0`, `0`, `144`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #283 = G_MEMCPY
838	{ `282`, `2`, `0`, `0`, `0`, `0`, `0`, `142`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #282 = G_WRITE_REGISTER
839	{ `281`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #281 = G_READ_REGISTER
840	{ `280`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #280 = G_STRICT_FLDEXP
841	{ `279`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #279 = G_STRICT_FSQRT
842	{ `278`, `4`, `1`, `0`, `0`, `0`, `0`, `46`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #278 = G_STRICT_FMA
843	{ `277`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #277 = G_STRICT_FREM
844	{ `276`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #276 = G_STRICT_FDIV
845	{ `275`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #275 = G_STRICT_FMUL
846	{ `274`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #274 = G_STRICT_FSUB
847	{ `273`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayRaiseFPException)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #273 = G_STRICT_FADD
848	{ `272`, `1`, `0`, `0`, `0`, `0`, `0`, `50`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #272 = G_STACKRESTORE
849	{ `271`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #271 = G_STACKSAVE
850	{ `270`, `3`, `1`, `0`, `0`, `0`, `0`, `69`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #270 = G_DYN_STACKALLOC
851	{ `269`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #269 = G_JUMP_TABLE
852	{ `268`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #268 = G_BLOCK_ADDR
853	{ `267`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #267 = G_ADDRSPACE_CAST
854	{ `266`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #266 = G_FNEARBYINT
855	{ `265`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #265 = G_FRINT
856	{ `264`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #264 = G_FFLOOR
857	{ `263`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #263 = G_FSQRT
858	{ `262`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #262 = G_FTANH
859	{ `261`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #261 = G_FSINH
860	{ `260`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #260 = G_FCOSH
861	{ `259`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #259 = G_FATAN2
862	{ `258`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #258 = G_FATAN
863	{ `257`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #257 = G_FASIN
864	{ `256`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #256 = G_FACOS
865	{ `255`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #255 = G_FTAN
866	{ `254`, `3`, `2`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #254 = G_FSINCOS
867	{ `253`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #253 = G_FSIN
868	{ `252`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #252 = G_FCOS
869	{ `251`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #251 = G_FCEIL
870	{ `250`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #250 = G_BITREVERSE
871	{ `249`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #249 = G_BSWAP
872	{ `248`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #248 = G_CTPOP
873	{ `247`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #247 = G_CTLZ_ZERO_UNDEF
874	{ `246`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #246 = G_CTLZ
875	{ `245`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #245 = G_CTTZ_ZERO_UNDEF
876	{ `244`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #244 = G_CTTZ
877	{ `243`, `4`, `1`, `0`, `0`, `0`, `0`, `138`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #243 = G_VECTOR_COMPRESS
878	{ `242`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #242 = G_STEP_VECTOR
879	{ `241`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #241 = G_SPLAT_VECTOR
880	{ `240`, `4`, `1`, `0`, `0`, `0`, `0`, `134`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #240 = G_SHUFFLE_VECTOR
881	{ `239`, `3`, `1`, `0`, `0`, `0`, `0`, `131`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #239 = G_EXTRACT_VECTOR_ELT
882	{ `238`, `4`, `1`, `0`, `0`, `0`, `0`, `127`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #238 = G_INSERT_VECTOR_ELT
883	{ `237`, `3`, `1`, `0`, `0`, `0`, `0`, `58`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #237 = G_EXTRACT_SUBVECTOR
884	{ `236`, `4`, `1`, `0`, `0`, `0`, `0`, `63`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #236 = G_INSERT_SUBVECTOR
885	{ `235`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #235 = G_VSCALE
886	{ `234`, `3`, `0`, `0`, `0`, `0`, `0`, `124`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #234 = G_BRJT
887	{ `233`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #233 = G_BR
888	{ `232`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #232 = G_LLROUND
889	{ `231`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #231 = G_LROUND
890	{ `230`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #230 = G_ABS
891	{ `229`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #229 = G_UMAX
892	{ `228`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #228 = G_UMIN
893	{ `227`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #227 = G_SMAX
894	{ `226`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #226 = G_SMIN
895	{ `225`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #225 = G_PTRMASK
896	{ `224`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #224 = G_PTR_ADD
897	{ `223`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #223 = G_RESET_FPMODE
898	{ `222`, `1`, `0`, `0`, `0`, `0`, `0`, `50`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #222 = G_SET_FPMODE
899	{ `221`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #221 = G_GET_FPMODE
900	{ `220`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #220 = G_RESET_FPENV
901	{ `219`, `1`, `0`, `0`, `0`, `0`, `0`, `50`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #219 = G_SET_FPENV
902	{ `218`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #218 = G_GET_FPENV
903	{ `217`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #217 = G_FMAXIMUMNUM
904	{ `216`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #216 = G_FMINIMUMNUM
905	{ `215`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #215 = G_FMAXIMUM
906	{ `214`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #214 = G_FMINIMUM
907	{ `213`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #213 = G_FMAXNUM_IEEE
908	{ `212`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #212 = G_FMINNUM_IEEE
909	{ `211`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #211 = G_FMAXNUM
910	{ `210`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #210 = G_FMINNUM
911	{ `209`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #209 = G_FCANONICALIZE
912	{ `208`, `3`, `1`, `0`, `0`, `0`, `0`, `98`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #208 = G_IS_FPCLASS
913	{ `207`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #207 = G_FCOPYSIGN
914	{ `206`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #206 = G_FABS
915	{ `205`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #205 = G_FPTOUI_SAT
916	{ `204`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #204 = G_FPTOSI_SAT
917	{ `203`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #203 = G_UITOFP
918	{ `202`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #202 = G_SITOFP
919	{ `201`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #201 = G_FPTOUI
920	{ `200`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #200 = G_FPTOSI
921	{ `199`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #199 = G_FPTRUNC
922	{ `198`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #198 = G_FPEXT
923	{ `197`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #197 = G_FNEG
924	{ `196`, `3`, `2`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #196 = G_FFREXP
925	{ `195`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #195 = G_FLDEXP
926	{ `194`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #194 = G_FLOG10
927	{ `193`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #193 = G_FLOG2
928	{ `192`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #192 = G_FLOG
929	{ `191`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #191 = G_FEXP10
930	{ `190`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #190 = G_FEXP2
931	{ `189`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #189 = G_FEXP
932	{ `188`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #188 = G_FPOWI
933	{ `187`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #187 = G_FPOW
934	{ `186`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #186 = G_FREM
935	{ `185`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #185 = G_FDIV
936	{ `184`, `4`, `1`, `0`, `0`, `0`, `0`, `46`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #184 = G_FMAD
937	{ `183`, `4`, `1`, `0`, `0`, `0`, `0`, `46`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #183 = G_FMA
938	{ `182`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #182 = G_FMUL
939	{ `181`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #181 = G_FSUB
940	{ `180`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #180 = G_FADD
941	{ `179`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #179 = G_UDIVFIXSAT
942	{ `178`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #178 = G_SDIVFIXSAT
943	{ `177`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #177 = G_UDIVFIX
944	{ `176`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #176 = G_SDIVFIX
945	{ `175`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #175 = G_UMULFIXSAT
946	{ `174`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #174 = G_SMULFIXSAT
947	{ `173`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #173 = G_UMULFIX
948	{ `172`, `4`, `1`, `0`, `0`, `0`, `0`, `120`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #172 = G_SMULFIX
949	{ `171`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #171 = G_SSHLSAT
950	{ `170`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #170 = G_USHLSAT
951	{ `169`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #169 = G_SSUBSAT
952	{ `168`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #168 = G_USUBSAT
953	{ `167`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #167 = G_SADDSAT
954	{ `166`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #166 = G_UADDSAT
955	{ `165`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #165 = G_SMULH
956	{ `164`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #164 = G_UMULH
957	{ `163`, `4`, `2`, `0`, `0`, `0`, `0`, `87`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #163 = G_SMULO
958	{ `162`, `4`, `2`, `0`, `0`, `0`, `0`, `87`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #162 = G_UMULO
959	{ `161`, `5`, `2`, `0`, `0`, `0`, `0`, `115`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #161 = G_SSUBE
960	{ `160`, `4`, `2`, `0`, `0`, `0`, `0`, `87`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #160 = G_SSUBO
961	{ `159`, `5`, `2`, `0`, `0`, `0`, `0`, `115`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #159 = G_SADDE
962	{ `158`, `4`, `2`, `0`, `0`, `0`, `0`, `87`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #158 = G_SADDO
963	{ `157`, `5`, `2`, `0`, `0`, `0`, `0`, `115`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #157 = G_USUBE
964	{ `156`, `4`, `2`, `0`, `0`, `0`, `0`, `87`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #156 = G_USUBO
965	{ `155`, `5`, `2`, `0`, `0`, `0`, `0`, `115`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #155 = G_UADDE
966	{ `154`, `4`, `2`, `0`, `0`, `0`, `0`, `87`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #154 = G_UADDO
967	{ `153`, `4`, `1`, `0`, `0`, `0`, `0`, `87`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #153 = G_SELECT
968	{ `152`, `3`, `1`, `0`, `0`, `0`, `0`, `112`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #152 = G_UCMP
969	{ `151`, `3`, `1`, `0`, `0`, `0`, `0`, `112`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #151 = G_SCMP
970	{ `150`, `4`, `1`, `0`, `0`, `0`, `0`, `108`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #150 = G_FCMP
971	{ `149`, `4`, `1`, `0`, `0`, `0`, `0`, `108`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #149 = G_ICMP
972	{ `148`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #148 = G_ROTL
973	{ `147`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #147 = G_ROTR
974	{ `146`, `4`, `1`, `0`, `0`, `0`, `0`, `104`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #146 = G_FSHR
975	{ `145`, `4`, `1`, `0`, `0`, `0`, `0`, `104`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #145 = G_FSHL
976	{ `144`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #144 = G_ASHR
977	{ `143`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #143 = G_LSHR
978	{ `142`, `3`, `1`, `0`, `0`, `0`, `0`, `101`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #142 = G_SHL
979	{ `141`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #141 = G_ZEXT
980	{ `140`, `3`, `1`, `0`, `0`, `0`, `0`, `40`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #140 = G_SEXT_INREG
981	{ `139`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #139 = G_SEXT
982	{ `138`, `3`, `1`, `0`, `0`, `0`, `0`, `98`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #138 = G_VAARG
983	{ `137`, `1`, `0`, `0`, `0`, `0`, `0`, `50`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #137 = G_VASTART
984	{ `136`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #136 = G_FCONSTANT
985	{ `135`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #135 = G_CONSTANT
986	{ `134`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #134 = G_TRUNC
987	{ `133`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #133 = G_ANYEXT
988	{ `132`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
989	{ `131`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #131 = G_INTRINSIC_CONVERGENT
990	{ `130`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS
991	{ `129`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #129 = G_INTRINSIC
992	{ `128`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #128 = G_INVOKE_REGION_START
993	{ `127`, `1`, `0`, `0`, `0`, `0`, `0`, `50`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::IndirectBranch)\|(`1ULL`<<MCID::Barrier)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #127 = G_BRINDIRECT
994	{ `126`, `2`, `0`, `0`, `0`, `0`, `0`, `51`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #126 = G_BRCOND
995	{ `125`, `4`, `0`, `0`, `0`, `0`, `0`, `94`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #125 = G_PREFETCH
996	{ `124`, `2`, `0`, `0`, `0`, `0`, `0`, `21`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #124 = G_FENCE
997	{ `123`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #123 = G_ATOMICRMW_USUB_SAT
998	{ `122`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #122 = G_ATOMICRMW_USUB_COND
999	{ `121`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP
1000	{ `120`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #120 = G_ATOMICRMW_UINC_WRAP
1001	{ `119`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #119 = G_ATOMICRMW_FMINIMUM
1002	{ `118`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #118 = G_ATOMICRMW_FMAXIMUM
1003	{ `117`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #117 = G_ATOMICRMW_FMIN
1004	{ `116`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #116 = G_ATOMICRMW_FMAX
1005	{ `115`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #115 = G_ATOMICRMW_FSUB
1006	{ `114`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #114 = G_ATOMICRMW_FADD
1007	{ `113`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #113 = G_ATOMICRMW_UMIN
1008	{ `112`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #112 = G_ATOMICRMW_UMAX
1009	{ `111`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #111 = G_ATOMICRMW_MIN
1010	{ `110`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #110 = G_ATOMICRMW_MAX
1011	{ `109`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #109 = G_ATOMICRMW_XOR
1012	{ `108`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #108 = G_ATOMICRMW_OR
1013	{ `107`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #107 = G_ATOMICRMW_NAND
1014	{ `106`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #106 = G_ATOMICRMW_AND
1015	{ `105`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #105 = G_ATOMICRMW_SUB
1016	{ `104`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #104 = G_ATOMICRMW_ADD
1017	{ `103`, `3`, `1`, `0`, `0`, `0`, `0`, `91`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #103 = G_ATOMICRMW_XCHG
1018	{ `102`, `4`, `1`, `0`, `0`, `0`, `0`, `87`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #102 = G_ATOMIC_CMPXCHG
1019	{ `101`, `5`, `2`, `0`, `0`, `0`, `0`, `82`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1020	{ `100`, `5`, `1`, `0`, `0`, `0`, `0`, `77`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #100 = G_INDEXED_STORE
1021	{ `99`, `2`, `0`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #99 = G_STORE
1022	{ `98`, `5`, `2`, `0`, `0`, `0`, `0`, `72`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #98 = G_INDEXED_ZEXTLOAD
1023	{ `97`, `5`, `2`, `0`, `0`, `0`, `0`, `72`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #97 = G_INDEXED_SEXTLOAD
1024	{ `96`, `5`, `2`, `0`, `0`, `0`, `0`, `72`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #96 = G_INDEXED_LOAD
1025	{ `95`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #95 = G_ZEXTLOAD
1026	{ `94`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #94 = G_SEXTLOAD
1027	{ `93`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #93 = G_LOAD
1028	{ `92`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #92 = G_READSTEADYCOUNTER
1029	{ `91`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #91 = G_READCYCLECOUNTER
1030	{ `90`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #90 = G_INTRINSIC_ROUNDEVEN
1031	{ `89`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #89 = G_INTRINSIC_LLRINT
1032	{ `88`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #88 = G_INTRINSIC_LRINT
1033	{ `87`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #87 = G_INTRINSIC_ROUND
1034	{ `86`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #86 = G_INTRINSIC_TRUNC
1035	{ `85`, `3`, `1`, `0`, `0`, `0`, `0`, `69`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
1036	{ `84`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #84 = G_CONSTANT_FOLD_BARRIER
1037	{ `83`, `2`, `1`, `0`, `0`, `0`, `0`, `67`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #83 = G_FREEZE
1038	{ `82`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #82 = G_BITCAST
1039	{ `81`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #81 = G_INTTOPTR
1040	{ `80`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #80 = G_PTRTOINT
1041	{ `79`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #79 = G_CONCAT_VECTORS
1042	{ `78`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #78 = G_BUILD_VECTOR_TRUNC
1043	{ `77`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #77 = G_BUILD_VECTOR
1044	{ `76`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #76 = G_MERGE_VALUES
1045	{ `75`, `4`, `1`, `0`, `0`, `0`, `0`, `63`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #75 = G_INSERT
1046	{ `74`, `2`, `1`, `0`, `0`, `0`, `0`, `61`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #74 = G_UNMERGE_VALUES
1047	{ `73`, `3`, `1`, `0`, `0`, `0`, `0`, `58`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #73 = G_EXTRACT
1048	{ `72`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #72 = G_CONSTANT_POOL
1049	{ `71`, `5`, `1`, `0`, `0`, `0`, `0`, `53`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
1050	{ `70`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #70 = G_GLOBAL_VALUE
1051	{ `69`, `2`, `1`, `0`, `0`, `0`, `0`, `51`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #69 = G_FRAME_INDEX
1052	{ `68`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #68 = G_PHI
1053	{ `67`, `1`, `1`, `0`, `0`, `0`, `0`, `50`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #67 = G_IMPLICIT_DEF
1054	{ `66`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #66 = G_ABDU
1055	{ `65`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #65 = G_ABDS
1056	{ `64`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #64 = G_XOR
1057	{ `63`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #63 = G_OR
1058	{ `62`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #62 = G_AND
1059	{ `61`, `4`, `2`, `0`, `0`, `0`, `0`, `46`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #61 = G_UDIVREM
1060	{ `60`, `4`, `2`, `0`, `0`, `0`, `0`, `46`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #60 = G_SDIVREM
1061	{ `59`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #59 = G_UREM
1062	{ `58`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #58 = G_SREM
1063	{ `57`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #57 = G_UDIV
1064	{ `56`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #56 = G_SDIV
1065	{ `55`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #55 = G_MUL
1066	{ `54`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #54 = G_SUB
1067	{ `53`, `3`, `1`, `0`, `0`, `0`, `0`, `43`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Commutable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #53 = G_ADD
1068	{ `52`, `3`, `1`, `0`, `0`, `0`, `0`, `40`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #52 = G_ASSERT_ALIGN
1069	{ `51`, `3`, `1`, `0`, `0`, `0`, `0`, `40`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #51 = G_ASSERT_ZEXT
1070	{ `50`, `3`, `1`, `0`, `0`, `0`, `0`, `40`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::PreISelOpcode)\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #50 = G_ASSERT_SEXT
1071	{ `49`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #49 = CONVERGENCECTRL_GLUE
1072	{ `48`, `2`, `1`, `0`, `0`, `0`, `0`, `13`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #48 = CONVERGENCECTRL_LOOP
1073	{ `47`, `1`, `1`, `0`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #47 = CONVERGENCECTRL_ANCHOR
1074	{ `46`, `1`, `1`, `0`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq)\|(`1ULL`<<MCID::Convergent), `0x0ULL` }, // Inst #46 = CONVERGENCECTRL_ENTRY
1075	{ `45`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #45 = JUMP_TABLE_DEBUG_INFO
1076	{ `44`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #44 = MEMBARRIER
1077	{ `43`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #43 = FAKE_USE
1078	{ `42`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #42 = ICALL_BRANCH_FUNNEL
1079	{ `41`, `3`, `0`, `0`, `0`, `0`, `0`, `37`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
1080	{ `40`, `2`, `0`, `0`, `0`, `0`, `0`, `35`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #40 = PATCHABLE_EVENT_CALL
1081	{ `39`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Return)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #39 = PATCHABLE_TAIL_CALL
1082	{ `38`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #38 = PATCHABLE_FUNCTION_EXIT
1083	{ `37`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Return)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #37 = PATCHABLE_RET
1084	{ `36`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #36 = PATCHABLE_FUNCTION_ENTER
1085	{ `35`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #35 = PATCHABLE_OP
1086	{ `34`, `1`, `1`, `0`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Branch)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::Terminator)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #34 = FAULTING_OP
1087	{ `33`, `2`, `0`, `0`, `0`, `0`, `0`, `33`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #33 = LOCAL_ESCAPE
1088	{ `32`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #32 = STATEPOINT
1089	{ `31`, `3`, `1`, `0`, `0`, `0`, `0`, `30`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #31 = PREALLOCATED_ARG
1090	{ `30`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #30 = PREALLOCATED_SETUP
1091	{ `29`, `1`, `1`, `0`, `0`, `0`, `0`, `29`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #29 = LOAD_STACK_GUARD
1092	{ `28`, `6`, `1`, `0`, `0`, `0`, `0`, `23`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #28 = PATCHPOINT
1093	{ `27`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::MayStore)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #27 = FENTRY_CALL
1094	{ `26`, `2`, `0`, `0`, `0`, `0`, `0`, `21`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Call)\|(`1ULL`<<MCID::MayLoad)\|(`1ULL`<<MCID::UsesCustomInserter)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #26 = STACKMAP
1095	{ `25`, `2`, `1`, `0`, `0`, `0`, `0`, `19`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #25 = ARITH_FENCE
1096	{ `24`, `4`, `0`, `0`, `0`, `0`, `0`, `15`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #24 = PSEUDO_PROBE
1097	{ `23`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #23 = LIFETIME_END
1098	{ `22`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #22 = LIFETIME_START
1099	{ `21`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #21 = BUNDLE
1100	{ `20`, `2`, `1`, `0`, `0`, `0`, `0`, `13`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #20 = COPY
1101	{ `19`, `2`, `1`, `0`, `0`, `0`, `0`, `13`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #19 = REG_SEQUENCE
1102	{ `18`, `1`, `0`, `0`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #18 = DBG_LABEL
1103	{ `17`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #17 = DBG_PHI
1104	{ `16`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #16 = DBG_INSTR_REF
1105	{ `15`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #15 = DBG_VALUE_LIST
1106	{ `14`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #14 = DBG_VALUE
1107	{ `13`, `3`, `1`, `0`, `0`, `0`, `0`, `2`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #13 = COPY_TO_REGCLASS
1108	{ `12`, `4`, `1`, `0`, `0`, `0`, `0`, `9`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #12 = SUBREG_TO_REG
1109	{ `11`, `1`, `1`, `0`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #11 = INIT_UNDEF
1110	{ `10`, `1`, `1`, `0`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Rematerializable)\|(`1ULL`<<MCID::CheapAsAMove)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #10 = IMPLICIT_DEF
1111	{ `9`, `4`, `1`, `0`, `0`, `0`, `0`, `5`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #9 = INSERT_SUBREG
1112	{ `8`, `3`, `1`, `0`, `0`, `0`, `0`, `2`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #8 = EXTRACT_SUBREG
1113	{ `7`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #7 = KILL
1114	{ `6`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::NotDuplicable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #6 = ANNOTATION_LABEL
1115	{ `5`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::NotDuplicable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #5 = GC_LABEL
1116	{ `4`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::NotDuplicable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #4 = EH_LABEL
1117	{ `3`, `1`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Meta)\|(`1ULL`<<MCID::NotDuplicable)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #3 = CFI_INSTRUCTION
1118	{ `2`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::UnmodeledSideEffects)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #2 = INLINEASM_BR
1119	{ `1`, `0`, `0`, `0`, `0`, `0`, `0`, `1`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #1 = INLINEASM
1120	{ `0`, `1`, `1`, `0`, `0`, `0`, `0`, `0`, XCoreImpOpBase + `0`, `0`\|(`1ULL`<<MCID::Pseudo)\|(`1ULL`<<MCID::Variadic)\|(`1ULL`<<MCID::ExtraSrcRegAllocReq)\|(`1ULL`<<MCID::ExtraDefRegAllocReq), `0x0ULL` }, // Inst #0 = PHI
1121	}, {
1122	/ 0 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
1123	/ 1 /
1124	/ 1 / { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1125	/ 2 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1126	/ 5 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(`0`) }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1127	/ 9 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1128	/ 13 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
1129	/ 15 / { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1130	/ 19 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(`0`) },
1131	/ 21 / { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1132	/ 23 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1133	/ 29 / { `0`, `0`\|(`1`<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, `0` },
1134	/ 30 / { `0`, `0`\|(`1`<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1135	/ 33 / { `0`, `0`\|(`1`<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1136	/ 35 / { `0`, `0`\|(`1`<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
1137	/ 37 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { `0`, `0`\|(`1`<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
1138	/ 40 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_IMM_0, `0` },
1139	/ 43 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
1140	/ 46 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
1141	/ 50 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
1142	/ 51 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
1143	/ 53 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1144	/ 58 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_IMM_0, `0` },
1145	/ 61 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
1146	/ 63 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_IMM_0, `0` },
1147	/ 67 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
1148	/ 69 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1149	/ 72 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_2, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
1150	/ 77 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_2, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
1151	/ 82 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_2, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
1152	/ 87 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
1153	/ 91 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
1154	/ 94 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1155	/ 98 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
1156	/ 101 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
1157	/ 104 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
1158	/ 108 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
1159	/ 112 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
1160	/ 115 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
1161	/ 120 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_IMM_0, `0` },
1162	/ 124 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
1163	/ 127 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_2, `0` },
1164	/ 131 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_2, `0` },
1165	/ 134 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
1166	/ 138 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
1167	/ 142 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` },
1168	/ 144 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_2, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_IMM_0, `0` },
1169	/ 148 / { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_0, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` }, { -`1`, `0`, MCOI::OPERAND_GENERIC_1, `0` },
1170	/ 152 / { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
1171	/ 154 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
1172	/ 156 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
1173	/ 157 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
1174	/ 160 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
1175	/ 164 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1176	/ 167 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
1177	/ 170 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(`0`) }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
1178	/ 173 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { -`1`, `0`, MCOI::OPERAND_UNKNOWN, `0` },
1179	/ 175 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1180	/ 177 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(`1`) }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
1181	/ 182 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(`0`) }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
1182	/ 186 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
1183	/ 191 / { XCore::RRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1184	/ 193 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
1185	/ 199 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(`0`) }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(`1`) }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
1186	/ 205 / { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(`0`) }, { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` },
1187	/ 208 / { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
1188	/ 210 / { -`1`, `0`, MCOI::OPERAND_IMMEDIATE, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` }, { XCore::GRRegsRegClassID, `0`, MCOI::OPERAND_REGISTER, `0` },
1189	}, {
1190	/ 0 /
1191	/ 0 / XCore::SP, XCore::SP,
1192	/ 2 / XCore::SP, XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR,
1193	/ 9 / XCore::R11,
1194	/ 10 / XCore::SP,
1195	}
1196	};
1197
1198
1199	#ifdef __GNUC__
1200	#pragma GCC diagnostic push
1201	#pragma GCC diagnostic ignored "-Woverlength-strings"
1202	#endif
1203	extern const char XCoreInstrNameData[] = {
1204	/ 0 / "G_FLOG10\000"
1205	/ 9 / "G_FEXP10\000"
1206	/ 18 / "LDAPB_u10\000"
1207	/ 28 / "BLRB_u10\000"
1208	/ 37 / "LDAPF_u10\000"
1209	/ 47 / "BLRF_u10\000"
1210	/ 56 / "BLACP_u10\000"
1211	/ 66 / "LDWCP_u10\000"
1212	/ 76 / "LDAPB_lu10\000"
1213	/ 87 / "BLRB_lu10\000"
1214	/ 97 / "LDAPF_lu10\000"
1215	/ 108 / "BLRF_lu10\000"
1216	/ 118 / "BLACP_lu10\000"
1217	/ 129 / "LDWCP_lu10\000"
1218	/ 140 / "BR_JT32\000"
1219	/ 148 / "G_FLOG2\000"
1220	/ 156 / "G_FATAN2\000"
1221	/ 165 / "G_FEXP2\000"
1222	/ 173 / "KCALL_u6\000"
1223	/ 182 / "LDAWCP_u6\000"
1224	/ 192 / "EXTDP_u6\000"
1225	/ 201 / "RETSP_u6\000"
1226	/ 210 / "KENTSP_u6\000"
1227	/ 220 / "KRESTSP_u6\000"
1228	/ 231 / "EXTSP_u6\000"
1229	/ 240 / "CLRSR_u6\000"
1230	/ 249 / "GETSR_u6\000"
1231	/ 258 / "SETSR_u6\000"
1232	/ 267 / "BLAT_u6\000"
1233	/ 275 / "BRBU_u6\000"
1234	/ 283 / "BRFU_u6\000"
1235	/ 291 / "CLRSR_branch_u6\000"
1236	/ 307 / "SETSR_branch_u6\000"
1237	/ 323 / "KCALL_lu6\000"
1238	/ 333 / "LDAWCP_lu6\000"
1239	/ 344 / "EXTDP_lu6\000"
1240	/ 354 / "RETSP_lu6\000"
1241	/ 364 / "KENTSP_lu6\000"
1242	/ 375 / "KRESTSP_lu6\000"
1243	/ 387 / "EXTSP_lu6\000"
1244	/ 397 / "CLRSR_lu6\000"
1245	/ 407 / "GETSR_lu6\000"
1246	/ 417 / "SETSR_lu6\000"
1247	/ 427 / "BLAT_lu6\000"
1248	/ 436 / "BRBU_lu6\000"
1249	/ 445 / "BRFU_lu6\000"
1250	/ 454 / "CLRSR_branch_lu6\000"
1251	/ 471 / "SETSR_branch_lu6\000"
1252	/ 488 / "LDC_ru6\000"
1253	/ 496 / "SETC_ru6\000"
1254	/ 505 / "BRBF_ru6\000"
1255	/ 514 / "BRFF_ru6\000"
1256	/ 523 / "LDWCP_ru6\000"
1257	/ 533 / "LDAWDP_ru6\000"
1258	/ 544 / "LDWDP_ru6\000"
1259	/ 554 / "STWDP_ru6\000"
1260	/ 564 / "LDAWSP_ru6\000"
1261	/ 575 / "LDWSP_ru6\000"
1262	/ 585 / "STWSP_ru6\000"
1263	/ 595 / "BRBT_ru6\000"
1264	/ 604 / "BRFT_ru6\000"
1265	/ 613 / "LDC_lru6\000"
1266	/ 622 / "SETC_lru6\000"
1267	/ 632 / "BRBF_lru6\000"
1268	/ 642 / "BRFF_lru6\000"
1269	/ 652 / "LDWCP_lru6\000"
1270	/ 663 / "LDAWDP_lru6\000"
1271	/ 675 / "LDWDP_lru6\000"
1272	/ 686 / "STWDP_lru6\000"
1273	/ 697 / "LDAWSP_lru6\000"
1274	/ 709 / "LDWSP_lru6\000"
1275	/ 720 / "STWSP_lru6\000"
1276	/ 731 / "BRBT_lru6\000"
1277	/ 741 / "BRFT_lru6\000"
1278	/ 751 / "G_FMA\000"
1279	/ 757 / "G_STRICT_FMA\000"
1280	/ 770 / "G_FSUB\000"
1281	/ 777 / "G_STRICT_FSUB\000"
1282	/ 791 / "G_ATOMICRMW_FSUB\000"
1283	/ 808 / "G_SUB\000"
1284	/ 814 / "G_ATOMICRMW_SUB\000"
1285	/ 830 / "SELECT_CC\000"
1286	/ 840 / "G_INTRINSIC\000"
1287	/ 852 / "G_FPTRUNC\000"
1288	/ 862 / "G_INTRINSIC_TRUNC\000"
1289	/ 880 / "G_TRUNC\000"
1290	/ 888 / "G_BUILD_VECTOR_TRUNC\000"
1291	/ 909 / "G_DYN_STACKALLOC\000"
1292	/ 926 / "G_FMAD\000"
1293	/ 933 / "G_INDEXED_SEXTLOAD\000"
1294	/ 952 / "G_SEXTLOAD\000"
1295	/ 963 / "G_INDEXED_ZEXTLOAD\000"
1296	/ 982 / "G_ZEXTLOAD\000"
1297	/ 993 / "G_INDEXED_LOAD\000"
1298	/ 1008 / "G_LOAD\000"
1299	/ 1015 / "G_VECREDUCE_FADD\000"
1300	/ 1032 / "G_FADD\000"
1301	/ 1039 / "G_VECREDUCE_SEQ_FADD\000"
1302	/ 1060 / "G_STRICT_FADD\000"
1303	/ 1074 / "G_ATOMICRMW_FADD\000"
1304	/ 1091 / "G_VECREDUCE_ADD\000"
1305	/ 1107 / "G_ADD\000"
1306	/ 1113 / "G_PTR_ADD\000"
1307	/ 1123 / "G_ATOMICRMW_ADD\000"
1308	/ 1139 / "G_ATOMICRMW_NAND\000"
1309	/ 1156 / "G_VECREDUCE_AND\000"
1310	/ 1172 / "G_AND\000"
1311	/ 1178 / "G_ATOMICRMW_AND\000"
1312	/ 1194 / "LIFETIME_END\000"
1313	/ 1207 / "G_BRCOND\000"
1314	/ 1216 / "G_ATOMICRMW_USUB_COND\000"
1315	/ 1238 / "G_LLROUND\000"
1316	/ 1248 / "G_LROUND\000"
1317	/ 1257 / "G_INTRINSIC_ROUND\000"
1318	/ 1275 / "G_INTRINSIC_FPTRUNC_ROUND\000"
1319	/ 1301 / "LOAD_STACK_GUARD\000"
1320	/ 1318 / "PSEUDO_PROBE\000"
1321	/ 1331 / "G_SSUBE\000"
1322	/ 1339 / "G_USUBE\000"
1323	/ 1347 / "G_FENCE\000"
1324	/ 1355 / "ARITH_FENCE\000"
1325	/ 1367 / "REG_SEQUENCE\000"
1326	/ 1380 / "G_SADDE\000"
1327	/ 1388 / "G_UADDE\000"
1328	/ 1396 / "G_GET_FPMODE\000"
1329	/ 1409 / "G_RESET_FPMODE\000"
1330	/ 1424 / "G_SET_FPMODE\000"
1331	/ 1437 / "G_FMINNUM_IEEE\000"
1332	/ 1452 / "G_FMAXNUM_IEEE\000"
1333	/ 1467 / "G_VSCALE\000"
1334	/ 1476 / "G_JUMP_TABLE\000"
1335	/ 1489 / "BUNDLE\000"
1336	/ 1496 / "G_MEMCPY_INLINE\000"
1337	/ 1512 / "LOCAL_ESCAPE\000"
1338	/ 1525 / "G_STACKRESTORE\000"
1339	/ 1540 / "G_INDEXED_STORE\000"
1340	/ 1556 / "G_STORE\000"
1341	/ 1564 / "G_BITREVERSE\000"
1342	/ 1577 / "FAKE_USE\000"
1343	/ 1586 / "DBG_VALUE\000"
1344	/ 1596 / "G_GLOBAL_VALUE\000"
1345	/ 1611 / "G_PTRAUTH_GLOBAL_VALUE\000"
1346	/ 1634 / "CONVERGENCECTRL_GLUE\000"
1347	/ 1655 / "G_STACKSAVE\000"
1348	/ 1667 / "G_MEMMOVE\000"
1349	/ 1677 / "G_FREEZE\000"
1350	/ 1686 / "G_FCANONICALIZE\000"
1351	/ 1702 / "G_CTLZ_ZERO_UNDEF\000"
1352	/ 1720 / "G_CTTZ_ZERO_UNDEF\000"
1353	/ 1738 / "INIT_UNDEF\000"
1354	/ 1749 / "G_IMPLICIT_DEF\000"
1355	/ 1764 / "DBG_INSTR_REF\000"
1356	/ 1778 / "G_FNEG\000"
1357	/ 1785 / "EXTRACT_SUBREG\000"
1358	/ 1800 / "INSERT_SUBREG\000"
1359	/ 1814 / "G_SEXT_INREG\000"
1360	/ 1827 / "SUBREG_TO_REG\000"
1361	/ 1841 / "G_ATOMIC_CMPXCHG\000"
1362	/ 1858 / "G_ATOMICRMW_XCHG\000"
1363	/ 1875 / "G_FLOG\000"
1364	/ 1882 / "G_VAARG\000"
1365	/ 1890 / "PREALLOCATED_ARG\000"
1366	/ 1907 / "G_PREFETCH\000"
1367	/ 1918 / "G_SMULH\000"
1368	/ 1926 / "G_UMULH\000"
1369	/ 1934 / "G_FTANH\000"
1370	/ 1942 / "G_FSINH\000"
1371	/ 1950 / "G_FCOSH\000"
1372	/ 1958 / "LDAWFI\000"
1373	/ 1965 / "LDWFI\000"
1374	/ 1971 / "STWFI\000"
1375	/ 1977 / "DBG_PHI\000"
1376	/ 1985 / "G_FPTOSI\000"
1377	/ 1994 / "G_FPTOUI\000"
1378	/ 2003 / "G_FPOWI\000"
1379	/ 2011 / "G_PTRMASK\000"
1380	/ 2021 / "GC_LABEL\000"
1381	/ 2030 / "DBG_LABEL\000"
1382	/ 2040 / "EH_LABEL\000"
1383	/ 2049 / "ANNOTATION_LABEL\000"
1384	/ 2066 / "ICALL_BRANCH_FUNNEL\000"
1385	/ 2086 / "G_FSHL\000"
1386	/ 2093 / "G_SHL\000"
1387	/ 2099 / "G_FCEIL\000"
1388	/ 2107 / "PATCHABLE_TAIL_CALL\000"
1389	/ 2127 / "PATCHABLE_TYPED_EVENT_CALL\000"
1390	/ 2154 / "PATCHABLE_EVENT_CALL\000"
1391	/ 2175 / "FENTRY_CALL\000"
1392	/ 2187 / "KILL\000"
1393	/ 2192 / "G_CONSTANT_POOL\000"
1394	/ 2208 / "G_ROTL\000"
1395	/ 2215 / "G_VECREDUCE_FMUL\000"
1396	/ 2232 / "G_FMUL\000"
1397	/ 2239 / "G_VECREDUCE_SEQ_FMUL\000"
1398	/ 2260 / "G_STRICT_FMUL\000"
1399	/ 2274 / "G_VECREDUCE_MUL\000"
1400	/ 2290 / "G_MUL\000"
1401	/ 2296 / "G_FREM\000"
1402	/ 2303 / "G_STRICT_FREM\000"
1403	/ 2317 / "G_SREM\000"
1404	/ 2324 / "G_UREM\000"
1405	/ 2331 / "G_SDIVREM\000"
1406	/ 2341 / "G_UDIVREM\000"
1407	/ 2351 / "INLINEASM\000"
1408	/ 2361 / "G_VECREDUCE_FMINIMUM\000"
1409	/ 2382 / "G_FMINIMUM\000"
1410	/ 2393 / "G_ATOMICRMW_FMINIMUM\000"
1411	/ 2414 / "G_VECREDUCE_FMAXIMUM\000"
1412	/ 2435 / "G_FMAXIMUM\000"
1413	/ 2446 / "G_ATOMICRMW_FMAXIMUM\000"
1414	/ 2467 / "G_FMINIMUMNUM\000"
1415	/ 2481 / "G_FMAXIMUMNUM\000"
1416	/ 2495 / "G_FMINNUM\000"
1417	/ 2505 / "G_FMAXNUM\000"
1418	/ 2515 / "G_FATAN\000"
1419	/ 2523 / "G_FTAN\000"
1420	/ 2530 / "G_INTRINSIC_ROUNDEVEN\000"
1421	/ 2552 / "G_ASSERT_ALIGN\000"
1422	/ 2567 / "G_FCOPYSIGN\000"
1423	/ 2579 / "G_VECREDUCE_FMIN\000"
1424	/ 2596 / "G_ATOMICRMW_FMIN\000"
1425	/ 2613 / "G_VECREDUCE_SMIN\000"
1426	/ 2630 / "G_SMIN\000"
1427	/ 2637 / "G_VECREDUCE_UMIN\000"
1428	/ 2654 / "G_UMIN\000"
1429	/ 2661 / "G_ATOMICRMW_UMIN\000"
1430	/ 2678 / "G_ATOMICRMW_MIN\000"
1431	/ 2694 / "G_FASIN\000"
1432	/ 2702 / "G_FSIN\000"
1433	/ 2709 / "CFI_INSTRUCTION\000"
1434	/ 2725 / "EH_RETURN\000"
1435	/ 2735 / "ADJCALLSTACKDOWN\000"
1436	/ 2752 / "G_SSUBO\000"
1437	/ 2760 / "G_USUBO\000"
1438	/ 2768 / "G_SADDO\000"
1439	/ 2776 / "G_UADDO\000"
1440	/ 2784 / "JUMP_TABLE_DEBUG_INFO\000"
1441	/ 2806 / "G_SMULO\000"
1442	/ 2814 / "G_UMULO\000"
1443	/ 2822 / "G_BZERO\000"
1444	/ 2830 / "STACKMAP\000"
1445	/ 2839 / "G_DEBUGTRAP\000"
1446	/ 2851 / "G_UBSANTRAP\000"
1447	/ 2863 / "G_TRAP\000"
1448	/ 2870 / "G_ATOMICRMW_UDEC_WRAP\000"
1449	/ 2892 / "G_ATOMICRMW_UINC_WRAP\000"
1450	/ 2914 / "G_BSWAP\000"
1451	/ 2922 / "G_SITOFP\000"
1452	/ 2931 / "G_UITOFP\000"
1453	/ 2940 / "G_FCMP\000"
1454	/ 2947 / "G_ICMP\000"
1455	/ 2954 / "G_SCMP\000"
1456	/ 2961 / "G_UCMP\000"
1457	/ 2968 / "CONVERGENCECTRL_LOOP\000"
1458	/ 2989 / "G_CTPOP\000"
1459	/ 2997 / "PATCHABLE_OP\000"
1460	/ 3010 / "FAULTING_OP\000"
1461	/ 3022 / "ADJCALLSTACKUP\000"
1462	/ 3037 / "PREALLOCATED_SETUP\000"
1463	/ 3056 / "G_FLDEXP\000"
1464	/ 3065 / "G_STRICT_FLDEXP\000"
1465	/ 3081 / "G_FEXP\000"
1466	/ 3088 / "G_FFREXP\000"
1467	/ 3097 / "LDSPC_0R\000"
1468	/ 3106 / "STSPC_0R\000"
1469	/ 3115 / "LDSED_0R\000"
1470	/ 3124 / "STSED_0R\000"
1471	/ 3133 / "GETED_0R\000"
1472	/ 3142 / "GETID_0R\000"
1473	/ 3151 / "CLRE_0R\000"
1474	/ 3159 / "DCALL_0R\000"
1475	/ 3168 / "GETKEP_0R\000"
1476	/ 3178 / "SETKEP_0R\000"
1477	/ 3188 / "GETKSP_0R\000"
1478	/ 3198 / "DENTSP_0R\000"
1479	/ 3208 / "DRESTSP_0R\000"
1480	/ 3219 / "LDSSR_0R\000"
1481	/ 3228 / "STSSR_0R\000"
1482	/ 3237 / "LDET_0R\000"
1483	/ 3245 / "FREET_0R\000"
1484	/ 3254 / "DRET_0R\000"
1485	/ 3262 / "KRET_0R\000"
1486	/ 3270 / "GETET_0R\000"
1487	/ 3279 / "STET_0R\000"
1488	/ 3287 / "WAITEU_0R\000"
1489	/ 3297 / "WAITEF_1R\000"
1490	/ 3307 / "WAITET_1R\000"
1491	/ 3317 / "CLRPT_1R\000"
1492	/ 3326 / "TSTART_1R\000"
1493	/ 3336 / "G_BR\000"
1494	/ 3341 / "INLINEASM_BR\000"
1495	/ 3354 / "G_BLOCK_ADDR\000"
1496	/ 3367 / "MEMBARRIER\000"
1497	/ 3378 / "G_CONSTANT_FOLD_BARRIER\000"
1498	/ 3402 / "PATCHABLE_FUNCTION_ENTER\000"
1499	/ 3427 / "G_READCYCLECOUNTER\000"
1500	/ 3446 / "G_READSTEADYCOUNTER\000"
1501	/ 3466 / "G_READ_REGISTER\000"
1502	/ 3482 / "G_WRITE_REGISTER\000"
1503	/ 3499 / "G_ASHR\000"
1504	/ 3506 / "G_FSHR\000"
1505	/ 3513 / "G_LSHR\000"
1506	/ 3520 / "CONVERGENCECTRL_ANCHOR\000"
1507	/ 3543 / "G_FFLOOR\000"
1508	/ 3552 / "G_EXTRACT_SUBVECTOR\000"
1509	/ 3572 / "G_INSERT_SUBVECTOR\000"
1510	/ 3591 / "G_BUILD_VECTOR\000"
1511	/ 3606 / "G_SHUFFLE_VECTOR\000"
1512	/ 3623 / "G_STEP_VECTOR\000"
1513	/ 3637 / "G_SPLAT_VECTOR\000"
1514	/ 3652 / "G_VECREDUCE_XOR\000"
1515	/ 3668 / "G_XOR\000"
1516	/ 3674 / "G_ATOMICRMW_XOR\000"
1517	/ 3690 / "G_VECREDUCE_OR\000"
1518	/ 3705 / "G_OR\000"
1519	/ 3710 / "G_ATOMICRMW_OR\000"
1520	/ 3725 / "G_ROTR\000"
1521	/ 3732 / "G_INTTOPTR\000"
1522	/ 3743 / "G_FABS\000"
1523	/ 3750 / "G_ABS\000"
1524	/ 3756 / "G_ABDS\000"
1525	/ 3763 / "G_UNMERGE_VALUES\000"
1526	/ 3780 / "G_MERGE_VALUES\000"
1527	/ 3795 / "G_FACOS\000"
1528	/ 3803 / "G_FCOS\000"
1529	/ 3810 / "G_FSINCOS\000"
1530	/ 3820 / "G_CONCAT_VECTORS\000"
1531	/ 3837 / "COPY_TO_REGCLASS\000"
1532	/ 3854 / "G_IS_FPCLASS\000"
1533	/ 3867 / "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1534	/ 3897 / "G_VECTOR_COMPRESS\000"
1535	/ 3915 / "G_INTRINSIC_W_SIDE_EFFECTS\000"
1536	/ 3942 / "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1537	/ 3980 / "G_SSUBSAT\000"
1538	/ 3990 / "G_USUBSAT\000"
1539	/ 4000 / "G_SADDSAT\000"
1540	/ 4010 / "G_UADDSAT\000"
1541	/ 4020 / "G_SSHLSAT\000"
1542	/ 4030 / "G_USHLSAT\000"
1543	/ 4040 / "G_SMULFIXSAT\000"
1544	/ 4053 / "G_UMULFIXSAT\000"
1545	/ 4066 / "G_SDIVFIXSAT\000"
1546	/ 4079 / "G_UDIVFIXSAT\000"
1547	/ 4092 / "G_ATOMICRMW_USUB_SAT\000"
1548	/ 4113 / "G_FPTOSI_SAT\000"
1549	/ 4126 / "G_FPTOUI_SAT\000"
1550	/ 4139 / "G_EXTRACT\000"
1551	/ 4149 / "G_SELECT\000"
1552	/ 4158 / "G_BRINDIRECT\000"
1553	/ 4171 / "PATCHABLE_RET\000"
1554	/ 4185 / "FRAME_TO_ARGS_OFFSET\000"
1555	/ 4206 / "G_MEMSET\000"
1556	/ 4215 / "PATCHABLE_FUNCTION_EXIT\000"
1557	/ 4239 / "G_BRJT\000"
1558	/ 4246 / "BR_JT\000"
1559	/ 4252 / "G_EXTRACT_VECTOR_ELT\000"
1560	/ 4273 / "G_INSERT_VECTOR_ELT\000"
1561	/ 4293 / "G_FCONSTANT\000"
1562	/ 4305 / "G_CONSTANT\000"
1563	/ 4316 / "G_INTRINSIC_CONVERGENT\000"
1564	/ 4339 / "STATEPOINT\000"
1565	/ 4350 / "PATCHPOINT\000"
1566	/ 4361 / "G_PTRTOINT\000"
1567	/ 4372 / "G_FRINT\000"
1568	/ 4380 / "G_INTRINSIC_LLRINT\000"
1569	/ 4399 / "G_INTRINSIC_LRINT\000"
1570	/ 4417 / "G_FNEARBYINT\000"
1571	/ 4430 / "NOT\000"
1572	/ 4434 / "G_VASTART\000"
1573	/ 4444 / "LIFETIME_START\000"
1574	/ 4459 / "G_INVOKE_REGION_START\000"
1575	/ 4481 / "G_INSERT\000"
1576	/ 4490 / "G_FSQRT\000"
1577	/ 4498 / "G_STRICT_FSQRT\000"
1578	/ 4513 / "G_BITCAST\000"
1579	/ 4523 / "G_ADDRSPACE_CAST\000"
1580	/ 4540 / "DBG_VALUE_LIST\000"
1581	/ 4555 / "G_FPEXT\000"
1582	/ 4563 / "G_SEXT\000"
1583	/ 4570 / "G_ASSERT_SEXT\000"
1584	/ 4584 / "G_ANYEXT\000"
1585	/ 4593 / "G_ZEXT\000"
1586	/ 4600 / "G_ASSERT_ZEXT\000"
1587	/ 4614 / "G_ABDU\000"
1588	/ 4621 / "G_FDIV\000"
1589	/ 4628 / "G_STRICT_FDIV\000"
1590	/ 4642 / "G_SDIV\000"
1591	/ 4649 / "G_UDIV\000"
1592	/ 4656 / "G_GET_FPENV\000"
1593	/ 4668 / "G_RESET_FPENV\000"
1594	/ 4682 / "G_SET_FPENV\000"
1595	/ 4694 / "G_FPOW\000"
1596	/ 4701 / "G_VECREDUCE_FMAX\000"
1597	/ 4718 / "G_ATOMICRMW_FMAX\000"
1598	/ 4735 / "G_VECREDUCE_SMAX\000"
1599	/ 4752 / "G_SMAX\000"
1600	/ 4759 / "G_VECREDUCE_UMAX\000"
1601	/ 4776 / "G_UMAX\000"
1602	/ 4783 / "G_ATOMICRMW_UMAX\000"
1603	/ 4800 / "G_ATOMICRMW_MAX\000"
1604	/ 4816 / "G_FRAME_INDEX\000"
1605	/ 4830 / "G_SBFX\000"
1606	/ 4837 / "G_UBFX\000"
1607	/ 4844 / "G_SMULFIX\000"
1608	/ 4854 / "G_UMULFIX\000"
1609	/ 4864 / "G_SDIVFIX\000"
1610	/ 4874 / "G_UDIVFIX\000"
1611	/ 4884 / "G_MEMCPY\000"
1612	/ 4893 / "COPY\000"
1613	/ 4898 / "CONVERGENCECTRL_ENTRY\000"
1614	/ 4920 / "G_CTLZ\000"
1615	/ 4927 / "G_CTTZ\000"
1616	/ 4934 / "LDAPF_lu10_ba\000"
1617	/ 4948 / "SSYNC_0r\000"
1618	/ 4957 / "BLA_1r\000"
1619	/ 4964 / "MSYNC_1r\000"
1620	/ 4973 / "ECALLF_1r\000"
1621	/ 4983 / "DGETREG_1r\000"
1622	/ 4994 / "KCALL_1r\000"
1623	/ 5003 / "MJOIN_1r\000"
1624	/ 5012 / "SETCP_1r\000"
1625	/ 5021 / "SETDP_1r\000"
1626	/ 5030 / "SETSP_1r\000"
1627	/ 5039 / "SYNCR_1r\000"
1628	/ 5048 / "FREER_1r\000"
1629	/ 5057 / "ECALLT_1r\000"
1630	/ 5067 / "BAU_1r\000"
1631	/ 5074 / "EDU_1r\000"
1632	/ 5081 / "EEU_1r\000"
1633	/ 5088 / "BRU_1r\000"
1634	/ 5095 / "SETEV_1r\000"
1635	/ 5104 / "SETV_1r\000"
1636	/ 5112 / "INITPC_2r\000"
1637	/ 5122 / "SETPSC_2r\000"
1638	/ 5132 / "SETD_2r\000"
1639	/ 5140 / "EEF_2r\000"
1640	/ 5147 / "PEEK_2r\000"
1641	/ 5155 / "MKMSK_2r\000"
1642	/ 5164 / "ENDIN_2r\000"
1643	/ 5173 / "INITCP_2r\000"
1644	/ 5183 / "INITDP_2r\000"
1645	/ 5193 / "INITSP_2r\000"
1646	/ 5203 / "INSHR_2r\000"
1647	/ 5212 / "OUTSHR_2r\000"
1648	/ 5222 / "TSETMR_2r\000"
1649	/ 5232 / "GETTS_2r\000"
1650	/ 5241 / "CHKCT_2r\000"
1651	/ 5250 / "INCT_2r\000"
1652	/ 5258 / "TESTCT_2r\000"
1653	/ 5268 / "OUTCT_2r\000"
1654	/ 5277 / "TESTWCT_2r\000"
1655	/ 5288 / "EET_2r\000"
1656	/ 5295 / "INT_2r\000"
1657	/ 5302 / "ANDNOT_2r\000"
1658	/ 5312 / "SETPT_2r\000"
1659	/ 5321 / "GETST_2r\000"
1660	/ 5330 / "OUTT_2r\000"
1661	/ 5338 / "OUT_2r\000"
1662	/ 5345 / "SEXT_2r\000"
1663	/ 5353 / "ZEXT_2r\000"
1664	/ 5361 / "SETC_l2r\000"
1665	/ 5370 / "GETD_l2r\000"
1666	/ 5379 / "SETCLK_l2r\000"
1667	/ 5390 / "TESTLCL_l2r\000"
1668	/ 5402 / "GETN_l2r\000"
1669	/ 5411 / "SETN_l2r\000"
1670	/ 5420 / "INITLR_l2r\000"
1671	/ 5431 / "GETPS_l2r\000"
1672	/ 5441 / "SETPS_l2r\000"
1673	/ 5451 / "BYTEREV_l2r\000"
1674	/ 5463 / "BITREV_l2r\000"
1675	/ 5474 / "SETTW_l2r\000"
1676	/ 5484 / "SETRDY_l2r\000"
1677	/ 5495 / "CLZ_l2r\000"
1678	/ 5503 / "SUB_3r\000"
1679	/ 5510 / "ADD_3r\000"
1680	/ 5517 / "AND_3r\000"
1681	/ 5524 / "SHL_3r\000"
1682	/ 5531 / "EQ_3r\000"
1683	/ 5537 / "SHR_3r\000"
1684	/ 5544 / "OR_3r\000"
1685	/ 5550 / "TSETR_3r\000"
1686	/ 5559 / "LD16S_3r\000"
1687	/ 5568 / "LSS_3r\000"
1688	/ 5575 / "LD8U_3r\000"
1689	/ 5583 / "LSU_3r\000"
1690	/ 5590 / "LDW_3r\000"
1691	/ 5597 / "ST16_l3r\000"
1692	/ 5606 / "ST8_l3r\000"
1693	/ 5614 / "LDA16B_l3r\000"
1694	/ 5625 / "LDAWB_l3r\000"
1695	/ 5635 / "CRC_l3r\000"
1696	/ 5643 / "LDA16F_l3r\000"
1697	/ 5654 / "LDAWF_l3r\000"
1698	/ 5664 / "MUL_l3r\000"
1699	/ 5672 / "ASHR_l3r\000"
1700	/ 5681 / "XOR_l3r\000"
1701	/ 5689 / "REMS_l3r\000"
1702	/ 5698 / "DIVS_l3r\000"
1703	/ 5707 / "REMU_l3r\000"
1704	/ 5716 / "DIVU_l3r\000"
1705	/ 5725 / "STW_l3r\000"
1706	/ 5733 / "CRC8_l4r\000"
1707	/ 5742 / "MACCS_l4r\000"
1708	/ 5752 / "MACCU_l4r\000"
1709	/ 5762 / "LSUB_l5r\000"
1710	/ 5771 / "LADD_l5r\000"
1711	/ 5780 / "LDIVU_l5r\000"
1712	/ 5790 / "LMUL_l6r\000"
1713	/ 5799 / "SUB_2rus\000"
1714	/ 5808 / "ADD_2rus\000"
1715	/ 5817 / "SHL_2rus\000"
1716	/ 5826 / "EQ_2rus\000"
1717	/ 5834 / "SHR_2rus\000"
1718	/ 5843 / "LDW_2rus\000"
1719	/ 5852 / "STW_2rus\000"
1720	/ 5861 / "LDAWB_l2rus\000"
1721	/ 5873 / "LDAWF_l2rus\000"
1722	/ 5885 / "ASHR_l2rus\000"
1723	/ 5896 / "INPW_l2rus\000"
1724	/ 5907 / "OUTPW_l2rus\000"
1725	/ 5919 / "MKMSK_rus\000"
1726	/ 5929 / "GETR_rus\000"
1727	/ 5938 / "CHKCT_rus\000"
1728	/ 5948 / "OUTCT_rus\000"
1729	/ 5958 / "SEXT_rus\000"
1730	/ 5967 / "ZEXT_rus\000"
1731	};
1732	#ifdef __GNUC__
1733	#pragma GCC diagnostic pop
1734	#endif
1735
1736	extern const unsigned XCoreInstrNameIndices[] = {
1737	`1981U`, `2351U`, `3341U`, `2709U`, `2040U`, `2021U`, `2049U`, `2187U`,
1738	`1785U`, `1800U`, `1751U`, `1738U`, `1827U`, `3837U`, `1586U`, `4540U`,
1739	`1764U`, `1977U`, `2030U`, `1367U`, `4893U`, `1489U`, `4444U`, `1194U`,
1740	`1318U`, `1355U`, `2830U`, `2175U`, `4350U`, `1301U`, `3037U`, `1890U`,
1741	`4339U`, `1512U`, `3010U`, `2997U`, `3402U`, `4171U`, `4215U`, `2107U`,
1742	`2154U`, `2127U`, `2066U`, `1577U`, `3367U`, `2784U`, `4898U`, `3520U`,
1743	`2968U`, `1634U`, `4570U`, `4600U`, `2552U`, `1107U`, `808U`, `2290U`,
1744	`4642U`, `4649U`, `2317U`, `2324U`, `2331U`, `2341U`, `1172U`, `3705U`,
1745	`3668U`, `3756U`, `4614U`, `1749U`, `1979U`, `4816U`, `1596U`, `1611U`,
1746	`2192U`, `4139U`, `3763U`, `4481U`, `3780U`, `3591U`, `888U`, `3820U`,
1747	`4361U`, `3732U`, `4513U`, `1677U`, `3378U`, `1275U`, `862U`, `1257U`,
1748	`4399U`, `4380U`, `2530U`, `3427U`, `3446U`, `1008U`, `952U`, `982U`,
1749	`993U`, `933U`, `963U`, `1556U`, `1540U`, `3867U`, `1841U`, `1858U`,
1750	`1123U`, `814U`, `1178U`, `1139U`, `3710U`, `3674U`, `4800U`, `2678U`,
1751	`4783U`, `2661U`, `1074U`, `791U`, `4718U`, `2596U`, `2446U`, `2393U`,
1752	`2892U`, `2870U`, `1216U`, `4092U`, `1347U`, `1907U`, `1207U`, `4158U`,
1753	`4459U`, `840U`, `3915U`, `4316U`, `3942U`, `4584U`, `880U`, `4305U`,
1754	`4293U`, `4434U`, `1882U`, `4563U`, `1814U`, `4593U`, `2093U`, `3513U`,
1755	`3499U`, `2086U`, `3506U`, `3725U`, `2208U`, `2947U`, `2940U`, `2954U`,
1756	`2961U`, `4149U`, `2776U`, `1388U`, `2760U`, `1339U`, `2768U`, `1380U`,
1757	`2752U`, `1331U`, `2814U`, `2806U`, `1926U`, `1918U`, `4010U`, `4000U`,
1758	`3990U`, `3980U`, `4030U`, `4020U`, `4844U`, `4854U`, `4040U`, `4053U`,
1759	`4864U`, `4874U`, `4066U`, `4079U`, `1032U`, `770U`, `2232U`, `751U`,
1760	`926U`, `4621U`, `2296U`, `4694U`, `2003U`, `3081U`, `165U`, `9U`,
1761	`1875U`, `148U`, `0U`, `3056U`, `3088U`, `1778U`, `4555U`, `852U`,
1762	`1985U`, `1994U`, `2922U`, `2931U`, `4113U`, `4126U`, `3743U`, `2567U`,
1763	`3854U`, `1686U`, `2495U`, `2505U`, `1437U`, `1452U`, `2382U`, `2435U`,
1764	`2467U`, `2481U`, `4656U`, `4682U`, `4668U`, `1396U`, `1424U`, `1409U`,
1765	`1113U`, `2011U`, `2630U`, `4752U`, `2654U`, `4776U`, `3750U`, `1248U`,
1766	`1238U`, `3336U`, `4239U`, `1467U`, `3572U`, `3552U`, `4273U`, `4252U`,
1767	`3606U`, `3637U`, `3623U`, `3897U`, `4927U`, `1720U`, `4920U`, `1702U`,
1768	`2989U`, `2914U`, `1564U`, `2099U`, `3803U`, `2702U`, `3810U`, `2523U`,
1769	`3795U`, `2694U`, `2515U`, `156U`, `1950U`, `1942U`, `1934U`, `4490U`,
1770	`3543U`, `4372U`, `4417U`, `4523U`, `3354U`, `1476U`, `909U`, `1655U`,
1771	`1525U`, `1060U`, `777U`, `2260U`, `4628U`, `2303U`, `757U`, `4498U`,
1772	`3065U`, `3466U`, `3482U`, `4884U`, `1496U`, `1667U`, `4206U`, `2822U`,
1773	`2863U`, `2839U`, `2851U`, `1039U`, `2239U`, `1015U`, `2215U`, `4701U`,
1774	`2579U`, `2414U`, `2361U`, `1091U`, `2274U`, `1156U`, `3690U`, `3652U`,
1775	`4735U`, `2613U`, `4759U`, `2637U`, `4830U`, `4837U`, `2735U`, `3022U`,
1776	`4246U`, `140U`, `2725U`, `4185U`, `1958U`, `1965U`, `830U`, `1971U`,
1777	`5808U`, `5510U`, `5302U`, `5517U`, `5885U`, `5672U`, `5067U`, `5463U`,
1778	`118U`, `56U`, `427U`, `267U`, `4957U`, `87U`, `28U`, `108U`,
1779	`47U`, `632U`, `505U`, `731U`, `595U`, `436U`, `275U`, `642U`,
1780	`514U`, `741U`, `604U`, `445U`, `283U`, `5088U`, `5451U`, `5241U`,
1781	`5938U`, `3151U`, `3317U`, `454U`, `291U`, `397U`, `240U`, `5495U`,
1782	`5733U`, `5635U`, `3159U`, `3198U`, `4983U`, `5698U`, `5716U`, `3208U`,
1783	`3254U`, `4973U`, `5057U`, `5074U`, `5140U`, `5288U`, `5081U`, `5164U`,
1784	`365U`, `211U`, `5826U`, `5531U`, `344U`, `192U`, `387U`, `231U`,
1785	`5048U`, `3245U`, `5370U`, `3133U`, `3270U`, `3142U`, `3168U`, `3188U`,
1786	`5402U`, `5431U`, `5929U`, `407U`, `249U`, `5321U`, `5232U`, `5250U`,
1787	`5173U`, `5183U`, `5420U`, `5112U`, `5193U`, `5896U`, `5203U`, `5295U`,
1788	`5167U`, `4994U`, `323U`, `173U`, `364U`, `210U`, `375U`, `220U`,
1789	`3262U`, `5771U`, `5559U`, `5575U`, `5614U`, `5643U`, `76U`, `18U`,
1790	`97U`, `4934U`, `37U`, `5861U`, `5625U`, `333U`, `182U`, `663U`,
1791	`533U`, `5873U`, `5654U`, `697U`, `564U`, `613U`, `488U`, `3237U`,
1792	`5780U`, `3115U`, `3097U`, `3219U`, `652U`, `129U`, `523U`, `66U`,
1793	`675U`, `544U`, `709U`, `575U`, `5843U`, `5590U`, `5790U`, `5568U`,
1794	`5762U`, `5583U`, `5742U`, `5752U`, `5003U`, `5155U`, `5919U`, `4964U`,
1795	`5664U`, `1781U`, `4430U`, `5544U`, `5268U`, `5948U`, `5907U`, `5212U`,
1796	`5330U`, `5338U`, `5147U`, `5689U`, `5707U`, `354U`, `201U`, `5379U`,
1797	`5012U`, `5361U`, `622U`, `496U`, `5021U`, `5132U`, `5095U`, `3178U`,
1798	`5411U`, `5122U`, `5441U`, `5312U`, `5484U`, `5030U`, `471U`, `307U`,
1799	`417U`, `258U`, `5474U`, `5104U`, `5345U`, `5958U`, `5817U`, `5524U`,
1800	`5834U`, `5537U`, `4948U`, `5597U`, `5606U`, `3279U`, `3124U`, `3106U`,
1801	`3228U`, `686U`, `554U`, `720U`, `585U`, `5852U`, `5725U`, `5799U`,
1802	`5503U`, `5039U`, `5258U`, `5390U`, `5277U`, `5222U`, `5550U`, `3326U`,
1803	`3297U`, `3307U`, `3287U`, `5681U`, `5353U`, `5967U`,
1804	};
1805
1806	static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
1807	II->InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, `534`);
1808	}
1809
1810	} // end namespace llvm
1811	#endif // GET_INSTRINFO_MC_DESC
1812
1813	#ifdef GET_INSTRINFO_HEADER
1814	#undef GET_INSTRINFO_HEADER
1815	namespace llvm {
1816	struct XCoreGenInstrInfo : public TargetInstrInfo {
1817	explicit XCoreGenInstrInfo(unsigned CFSetupOpcode = ~`0u`, unsigned CFDestroyOpcode = ~`0u`, unsigned CatchRetOpcode = ~`0u`, unsigned ReturnOpcode = ~`0u`);
1818	~XCoreGenInstrInfo() override = default;
1819
1820	};
1821	} // end namespace llvm
1822	#endif // GET_INSTRINFO_HEADER
1823
1824	#ifdef GET_INSTRINFO_HELPER_DECLS
1825	#undef GET_INSTRINFO_HELPER_DECLS
1826
1827
1828	#endif // GET_INSTRINFO_HELPER_DECLS
1829
1830	#ifdef GET_INSTRINFO_HELPERS
1831	#undef GET_INSTRINFO_HELPERS
1832
1833	#endif // GET_INSTRINFO_HELPERS
1834
1835	#ifdef GET_INSTRINFO_CTOR_DTOR
1836	#undef GET_INSTRINFO_CTOR_DTOR
1837	namespace llvm {
1838	extern const XCoreInstrTable XCoreDescs;
1839	extern const unsigned XCoreInstrNameIndices[];
1840	extern const char XCoreInstrNameData[];
1841	XCoreGenInstrInfo::XCoreGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1842	: TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1843	InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, `534`);
1844	}
1845	} // end namespace llvm
1846	#endif // GET_INSTRINFO_CTOR_DTOR
1847
1848	#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1849	#undef GET_INSTRINFO_MC_HELPER_DECLS
1850
1851	namespace llvm {
1852	class MCInst;
1853	class FeatureBitset;
1854
1855	namespace XCore_MC {
1856
1857	void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1858
1859	} // end namespace XCore_MC
1860	} // end namespace llvm
1861
1862	#endif // GET_INSTRINFO_MC_HELPER_DECLS
1863
1864	#ifdef GET_INSTRINFO_MC_HELPERS
1865	#undef GET_INSTRINFO_MC_HELPERS
1866
1867	namespace llvm::XCore_MC {
1868	} // end namespace llvm::XCore_MC
1869	#endif // GET_GENISTRINFO_MC_HELPERS
1870
1871	#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) \|\|\
1872	defined(GET_AVAILABLE_OPCODE_CHECKER)
1873	#define GET_COMPUTE_FEATURES
1874	#endif
1875	#ifdef GET_COMPUTE_FEATURES
1876	#undef GET_COMPUTE_FEATURES
1877	namespace llvm::XCore_MC {
1878	// Bits for subtarget features that participate in instruction matching.
1879	enum SubtargetFeatureBits : uint8_t {
1880	};
1881
1882	inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1883	FeatureBitset Features;
1884	return Features;
1885	}
1886
1887	inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1888	enum : uint8_t {
1889	CEFBS_None,
1890	};
1891
1892	static constexpr FeatureBitset FeatureBitsets[] = {
1893	{}, // CEFBS_None
1894	};
1895	static constexpr uint8_t RequiredFeaturesRefs[] = {
1896	CEFBS_None, // PHI = 0
1897	CEFBS_None, // INLINEASM = 1
1898	CEFBS_None, // INLINEASM_BR = 2
1899	CEFBS_None, // CFI_INSTRUCTION = 3
1900	CEFBS_None, // EH_LABEL = 4
1901	CEFBS_None, // GC_LABEL = 5
1902	CEFBS_None, // ANNOTATION_LABEL = 6
1903	CEFBS_None, // KILL = 7
1904	CEFBS_None, // EXTRACT_SUBREG = 8
1905	CEFBS_None, // INSERT_SUBREG = 9
1906	CEFBS_None, // IMPLICIT_DEF = 10
1907	CEFBS_None, // INIT_UNDEF = 11
1908	CEFBS_None, // SUBREG_TO_REG = 12
1909	CEFBS_None, // COPY_TO_REGCLASS = 13
1910	CEFBS_None, // DBG_VALUE = 14
1911	CEFBS_None, // DBG_VALUE_LIST = 15
1912	CEFBS_None, // DBG_INSTR_REF = 16
1913	CEFBS_None, // DBG_PHI = 17
1914	CEFBS_None, // DBG_LABEL = 18
1915	CEFBS_None, // REG_SEQUENCE = 19
1916	CEFBS_None, // COPY = 20
1917	CEFBS_None, // BUNDLE = 21
1918	CEFBS_None, // LIFETIME_START = 22
1919	CEFBS_None, // LIFETIME_END = 23
1920	CEFBS_None, // PSEUDO_PROBE = 24
1921	CEFBS_None, // ARITH_FENCE = 25
1922	CEFBS_None, // STACKMAP = 26
1923	CEFBS_None, // FENTRY_CALL = 27
1924	CEFBS_None, // PATCHPOINT = 28
1925	CEFBS_None, // LOAD_STACK_GUARD = 29
1926	CEFBS_None, // PREALLOCATED_SETUP = 30
1927	CEFBS_None, // PREALLOCATED_ARG = 31
1928	CEFBS_None, // STATEPOINT = 32
1929	CEFBS_None, // LOCAL_ESCAPE = 33
1930	CEFBS_None, // FAULTING_OP = 34
1931	CEFBS_None, // PATCHABLE_OP = 35
1932	CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
1933	CEFBS_None, // PATCHABLE_RET = 37
1934	CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
1935	CEFBS_None, // PATCHABLE_TAIL_CALL = 39
1936	CEFBS_None, // PATCHABLE_EVENT_CALL = 40
1937	CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
1938	CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
1939	CEFBS_None, // FAKE_USE = 43
1940	CEFBS_None, // MEMBARRIER = 44
1941	CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
1942	CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
1943	CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
1944	CEFBS_None, // CONVERGENCECTRL_LOOP = 48
1945	CEFBS_None, // CONVERGENCECTRL_GLUE = 49
1946	CEFBS_None, // G_ASSERT_SEXT = 50
1947	CEFBS_None, // G_ASSERT_ZEXT = 51
1948	CEFBS_None, // G_ASSERT_ALIGN = 52
1949	CEFBS_None, // G_ADD = 53
1950	CEFBS_None, // G_SUB = 54
1951	CEFBS_None, // G_MUL = 55
1952	CEFBS_None, // G_SDIV = 56
1953	CEFBS_None, // G_UDIV = 57
1954	CEFBS_None, // G_SREM = 58
1955	CEFBS_None, // G_UREM = 59
1956	CEFBS_None, // G_SDIVREM = 60
1957	CEFBS_None, // G_UDIVREM = 61
1958	CEFBS_None, // G_AND = 62
1959	CEFBS_None, // G_OR = 63
1960	CEFBS_None, // G_XOR = 64
1961	CEFBS_None, // G_ABDS = 65
1962	CEFBS_None, // G_ABDU = 66
1963	CEFBS_None, // G_IMPLICIT_DEF = 67
1964	CEFBS_None, // G_PHI = 68
1965	CEFBS_None, // G_FRAME_INDEX = 69
1966	CEFBS_None, // G_GLOBAL_VALUE = 70
1967	CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
1968	CEFBS_None, // G_CONSTANT_POOL = 72
1969	CEFBS_None, // G_EXTRACT = 73
1970	CEFBS_None, // G_UNMERGE_VALUES = 74
1971	CEFBS_None, // G_INSERT = 75
1972	CEFBS_None, // G_MERGE_VALUES = 76
1973	CEFBS_None, // G_BUILD_VECTOR = 77
1974	CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
1975	CEFBS_None, // G_CONCAT_VECTORS = 79
1976	CEFBS_None, // G_PTRTOINT = 80
1977	CEFBS_None, // G_INTTOPTR = 81
1978	CEFBS_None, // G_BITCAST = 82
1979	CEFBS_None, // G_FREEZE = 83
1980	CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
1981	CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
1982	CEFBS_None, // G_INTRINSIC_TRUNC = 86
1983	CEFBS_None, // G_INTRINSIC_ROUND = 87
1984	CEFBS_None, // G_INTRINSIC_LRINT = 88
1985	CEFBS_None, // G_INTRINSIC_LLRINT = 89
1986	CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
1987	CEFBS_None, // G_READCYCLECOUNTER = 91
1988	CEFBS_None, // G_READSTEADYCOUNTER = 92
1989	CEFBS_None, // G_LOAD = 93
1990	CEFBS_None, // G_SEXTLOAD = 94
1991	CEFBS_None, // G_ZEXTLOAD = 95
1992	CEFBS_None, // G_INDEXED_LOAD = 96
1993	CEFBS_None, // G_INDEXED_SEXTLOAD = 97
1994	CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
1995	CEFBS_None, // G_STORE = 99
1996	CEFBS_None, // G_INDEXED_STORE = 100
1997	CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
1998	CEFBS_None, // G_ATOMIC_CMPXCHG = 102
1999	CEFBS_None, // G_ATOMICRMW_XCHG = 103
2000	CEFBS_None, // G_ATOMICRMW_ADD = 104
2001	CEFBS_None, // G_ATOMICRMW_SUB = 105
2002	CEFBS_None, // G_ATOMICRMW_AND = 106
2003	CEFBS_None, // G_ATOMICRMW_NAND = 107
2004	CEFBS_None, // G_ATOMICRMW_OR = 108
2005	CEFBS_None, // G_ATOMICRMW_XOR = 109
2006	CEFBS_None, // G_ATOMICRMW_MAX = 110
2007	CEFBS_None, // G_ATOMICRMW_MIN = 111
2008	CEFBS_None, // G_ATOMICRMW_UMAX = 112
2009	CEFBS_None, // G_ATOMICRMW_UMIN = 113
2010	CEFBS_None, // G_ATOMICRMW_FADD = 114
2011	CEFBS_None, // G_ATOMICRMW_FSUB = 115
2012	CEFBS_None, // G_ATOMICRMW_FMAX = 116
2013	CEFBS_None, // G_ATOMICRMW_FMIN = 117
2014	CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118
2015	CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119
2016	CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120
2017	CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121
2018	CEFBS_None, // G_ATOMICRMW_USUB_COND = 122
2019	CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123
2020	CEFBS_None, // G_FENCE = 124
2021	CEFBS_None, // G_PREFETCH = 125
2022	CEFBS_None, // G_BRCOND = 126
2023	CEFBS_None, // G_BRINDIRECT = 127
2024	CEFBS_None, // G_INVOKE_REGION_START = 128
2025	CEFBS_None, // G_INTRINSIC = 129
2026	CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130
2027	CEFBS_None, // G_INTRINSIC_CONVERGENT = 131
2028	CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132
2029	CEFBS_None, // G_ANYEXT = 133
2030	CEFBS_None, // G_TRUNC = 134
2031	CEFBS_None, // G_CONSTANT = 135
2032	CEFBS_None, // G_FCONSTANT = 136
2033	CEFBS_None, // G_VASTART = 137
2034	CEFBS_None, // G_VAARG = 138
2035	CEFBS_None, // G_SEXT = 139
2036	CEFBS_None, // G_SEXT_INREG = 140
2037	CEFBS_None, // G_ZEXT = 141
2038	CEFBS_None, // G_SHL = 142
2039	CEFBS_None, // G_LSHR = 143
2040	CEFBS_None, // G_ASHR = 144
2041	CEFBS_None, // G_FSHL = 145
2042	CEFBS_None, // G_FSHR = 146
2043	CEFBS_None, // G_ROTR = 147
2044	CEFBS_None, // G_ROTL = 148
2045	CEFBS_None, // G_ICMP = 149
2046	CEFBS_None, // G_FCMP = 150
2047	CEFBS_None, // G_SCMP = 151
2048	CEFBS_None, // G_UCMP = 152
2049	CEFBS_None, // G_SELECT = 153
2050	CEFBS_None, // G_UADDO = 154
2051	CEFBS_None, // G_UADDE = 155
2052	CEFBS_None, // G_USUBO = 156
2053	CEFBS_None, // G_USUBE = 157
2054	CEFBS_None, // G_SADDO = 158
2055	CEFBS_None, // G_SADDE = 159
2056	CEFBS_None, // G_SSUBO = 160
2057	CEFBS_None, // G_SSUBE = 161
2058	CEFBS_None, // G_UMULO = 162
2059	CEFBS_None, // G_SMULO = 163
2060	CEFBS_None, // G_UMULH = 164
2061	CEFBS_None, // G_SMULH = 165
2062	CEFBS_None, // G_UADDSAT = 166
2063	CEFBS_None, // G_SADDSAT = 167
2064	CEFBS_None, // G_USUBSAT = 168
2065	CEFBS_None, // G_SSUBSAT = 169
2066	CEFBS_None, // G_USHLSAT = 170
2067	CEFBS_None, // G_SSHLSAT = 171
2068	CEFBS_None, // G_SMULFIX = 172
2069	CEFBS_None, // G_UMULFIX = 173
2070	CEFBS_None, // G_SMULFIXSAT = 174
2071	CEFBS_None, // G_UMULFIXSAT = 175
2072	CEFBS_None, // G_SDIVFIX = 176
2073	CEFBS_None, // G_UDIVFIX = 177
2074	CEFBS_None, // G_SDIVFIXSAT = 178
2075	CEFBS_None, // G_UDIVFIXSAT = 179
2076	CEFBS_None, // G_FADD = 180
2077	CEFBS_None, // G_FSUB = 181
2078	CEFBS_None, // G_FMUL = 182
2079	CEFBS_None, // G_FMA = 183
2080	CEFBS_None, // G_FMAD = 184
2081	CEFBS_None, // G_FDIV = 185
2082	CEFBS_None, // G_FREM = 186
2083	CEFBS_None, // G_FPOW = 187
2084	CEFBS_None, // G_FPOWI = 188
2085	CEFBS_None, // G_FEXP = 189
2086	CEFBS_None, // G_FEXP2 = 190
2087	CEFBS_None, // G_FEXP10 = 191
2088	CEFBS_None, // G_FLOG = 192
2089	CEFBS_None, // G_FLOG2 = 193
2090	CEFBS_None, // G_FLOG10 = 194
2091	CEFBS_None, // G_FLDEXP = 195
2092	CEFBS_None, // G_FFREXP = 196
2093	CEFBS_None, // G_FNEG = 197
2094	CEFBS_None, // G_FPEXT = 198
2095	CEFBS_None, // G_FPTRUNC = 199
2096	CEFBS_None, // G_FPTOSI = 200
2097	CEFBS_None, // G_FPTOUI = 201
2098	CEFBS_None, // G_SITOFP = 202
2099	CEFBS_None, // G_UITOFP = 203
2100	CEFBS_None, // G_FPTOSI_SAT = 204
2101	CEFBS_None, // G_FPTOUI_SAT = 205
2102	CEFBS_None, // G_FABS = 206
2103	CEFBS_None, // G_FCOPYSIGN = 207
2104	CEFBS_None, // G_IS_FPCLASS = 208
2105	CEFBS_None, // G_FCANONICALIZE = 209
2106	CEFBS_None, // G_FMINNUM = 210
2107	CEFBS_None, // G_FMAXNUM = 211
2108	CEFBS_None, // G_FMINNUM_IEEE = 212
2109	CEFBS_None, // G_FMAXNUM_IEEE = 213
2110	CEFBS_None, // G_FMINIMUM = 214
2111	CEFBS_None, // G_FMAXIMUM = 215
2112	CEFBS_None, // G_FMINIMUMNUM = 216
2113	CEFBS_None, // G_FMAXIMUMNUM = 217
2114	CEFBS_None, // G_GET_FPENV = 218
2115	CEFBS_None, // G_SET_FPENV = 219
2116	CEFBS_None, // G_RESET_FPENV = 220
2117	CEFBS_None, // G_GET_FPMODE = 221
2118	CEFBS_None, // G_SET_FPMODE = 222
2119	CEFBS_None, // G_RESET_FPMODE = 223
2120	CEFBS_None, // G_PTR_ADD = 224
2121	CEFBS_None, // G_PTRMASK = 225
2122	CEFBS_None, // G_SMIN = 226
2123	CEFBS_None, // G_SMAX = 227
2124	CEFBS_None, // G_UMIN = 228
2125	CEFBS_None, // G_UMAX = 229
2126	CEFBS_None, // G_ABS = 230
2127	CEFBS_None, // G_LROUND = 231
2128	CEFBS_None, // G_LLROUND = 232
2129	CEFBS_None, // G_BR = 233
2130	CEFBS_None, // G_BRJT = 234
2131	CEFBS_None, // G_VSCALE = 235
2132	CEFBS_None, // G_INSERT_SUBVECTOR = 236
2133	CEFBS_None, // G_EXTRACT_SUBVECTOR = 237
2134	CEFBS_None, // G_INSERT_VECTOR_ELT = 238
2135	CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239
2136	CEFBS_None, // G_SHUFFLE_VECTOR = 240
2137	CEFBS_None, // G_SPLAT_VECTOR = 241
2138	CEFBS_None, // G_STEP_VECTOR = 242
2139	CEFBS_None, // G_VECTOR_COMPRESS = 243
2140	CEFBS_None, // G_CTTZ = 244
2141	CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245
2142	CEFBS_None, // G_CTLZ = 246
2143	CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247
2144	CEFBS_None, // G_CTPOP = 248
2145	CEFBS_None, // G_BSWAP = 249
2146	CEFBS_None, // G_BITREVERSE = 250
2147	CEFBS_None, // G_FCEIL = 251
2148	CEFBS_None, // G_FCOS = 252
2149	CEFBS_None, // G_FSIN = 253
2150	CEFBS_None, // G_FSINCOS = 254
2151	CEFBS_None, // G_FTAN = 255
2152	CEFBS_None, // G_FACOS = 256
2153	CEFBS_None, // G_FASIN = 257
2154	CEFBS_None, // G_FATAN = 258
2155	CEFBS_None, // G_FATAN2 = 259
2156	CEFBS_None, // G_FCOSH = 260
2157	CEFBS_None, // G_FSINH = 261
2158	CEFBS_None, // G_FTANH = 262
2159	CEFBS_None, // G_FSQRT = 263
2160	CEFBS_None, // G_FFLOOR = 264
2161	CEFBS_None, // G_FRINT = 265
2162	CEFBS_None, // G_FNEARBYINT = 266
2163	CEFBS_None, // G_ADDRSPACE_CAST = 267
2164	CEFBS_None, // G_BLOCK_ADDR = 268
2165	CEFBS_None, // G_JUMP_TABLE = 269
2166	CEFBS_None, // G_DYN_STACKALLOC = 270
2167	CEFBS_None, // G_STACKSAVE = 271
2168	CEFBS_None, // G_STACKRESTORE = 272
2169	CEFBS_None, // G_STRICT_FADD = 273
2170	CEFBS_None, // G_STRICT_FSUB = 274
2171	CEFBS_None, // G_STRICT_FMUL = 275
2172	CEFBS_None, // G_STRICT_FDIV = 276
2173	CEFBS_None, // G_STRICT_FREM = 277
2174	CEFBS_None, // G_STRICT_FMA = 278
2175	CEFBS_None, // G_STRICT_FSQRT = 279
2176	CEFBS_None, // G_STRICT_FLDEXP = 280
2177	CEFBS_None, // G_READ_REGISTER = 281
2178	CEFBS_None, // G_WRITE_REGISTER = 282
2179	CEFBS_None, // G_MEMCPY = 283
2180	CEFBS_None, // G_MEMCPY_INLINE = 284
2181	CEFBS_None, // G_MEMMOVE = 285
2182	CEFBS_None, // G_MEMSET = 286
2183	CEFBS_None, // G_BZERO = 287
2184	CEFBS_None, // G_TRAP = 288
2185	CEFBS_None, // G_DEBUGTRAP = 289
2186	CEFBS_None, // G_UBSANTRAP = 290
2187	CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291
2188	CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292
2189	CEFBS_None, // G_VECREDUCE_FADD = 293
2190	CEFBS_None, // G_VECREDUCE_FMUL = 294
2191	CEFBS_None, // G_VECREDUCE_FMAX = 295
2192	CEFBS_None, // G_VECREDUCE_FMIN = 296
2193	CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297
2194	CEFBS_None, // G_VECREDUCE_FMINIMUM = 298
2195	CEFBS_None, // G_VECREDUCE_ADD = 299
2196	CEFBS_None, // G_VECREDUCE_MUL = 300
2197	CEFBS_None, // G_VECREDUCE_AND = 301
2198	CEFBS_None, // G_VECREDUCE_OR = 302
2199	CEFBS_None, // G_VECREDUCE_XOR = 303
2200	CEFBS_None, // G_VECREDUCE_SMAX = 304
2201	CEFBS_None, // G_VECREDUCE_SMIN = 305
2202	CEFBS_None, // G_VECREDUCE_UMAX = 306
2203	CEFBS_None, // G_VECREDUCE_UMIN = 307
2204	CEFBS_None, // G_SBFX = 308
2205	CEFBS_None, // G_UBFX = 309
2206	CEFBS_None, // ADJCALLSTACKDOWN = 310
2207	CEFBS_None, // ADJCALLSTACKUP = 311
2208	CEFBS_None, // BR_JT = 312
2209	CEFBS_None, // BR_JT32 = 313
2210	CEFBS_None, // EH_RETURN = 314
2211	CEFBS_None, // FRAME_TO_ARGS_OFFSET = 315
2212	CEFBS_None, // LDAWFI = 316
2213	CEFBS_None, // LDWFI = 317
2214	CEFBS_None, // SELECT_CC = 318
2215	CEFBS_None, // STWFI = 319
2216	CEFBS_None, // ADD_2rus = 320
2217	CEFBS_None, // ADD_3r = 321
2218	CEFBS_None, // ANDNOT_2r = 322
2219	CEFBS_None, // AND_3r = 323
2220	CEFBS_None, // ASHR_l2rus = 324
2221	CEFBS_None, // ASHR_l3r = 325
2222	CEFBS_None, // BAU_1r = 326
2223	CEFBS_None, // BITREV_l2r = 327
2224	CEFBS_None, // BLACP_lu10 = 328
2225	CEFBS_None, // BLACP_u10 = 329
2226	CEFBS_None, // BLAT_lu6 = 330
2227	CEFBS_None, // BLAT_u6 = 331
2228	CEFBS_None, // BLA_1r = 332
2229	CEFBS_None, // BLRB_lu10 = 333
2230	CEFBS_None, // BLRB_u10 = 334
2231	CEFBS_None, // BLRF_lu10 = 335
2232	CEFBS_None, // BLRF_u10 = 336
2233	CEFBS_None, // BRBF_lru6 = 337
2234	CEFBS_None, // BRBF_ru6 = 338
2235	CEFBS_None, // BRBT_lru6 = 339
2236	CEFBS_None, // BRBT_ru6 = 340
2237	CEFBS_None, // BRBU_lu6 = 341
2238	CEFBS_None, // BRBU_u6 = 342
2239	CEFBS_None, // BRFF_lru6 = 343
2240	CEFBS_None, // BRFF_ru6 = 344
2241	CEFBS_None, // BRFT_lru6 = 345
2242	CEFBS_None, // BRFT_ru6 = 346
2243	CEFBS_None, // BRFU_lu6 = 347
2244	CEFBS_None, // BRFU_u6 = 348
2245	CEFBS_None, // BRU_1r = 349
2246	CEFBS_None, // BYTEREV_l2r = 350
2247	CEFBS_None, // CHKCT_2r = 351
2248	CEFBS_None, // CHKCT_rus = 352
2249	CEFBS_None, // CLRE_0R = 353
2250	CEFBS_None, // CLRPT_1R = 354
2251	CEFBS_None, // CLRSR_branch_lu6 = 355
2252	CEFBS_None, // CLRSR_branch_u6 = 356
2253	CEFBS_None, // CLRSR_lu6 = 357
2254	CEFBS_None, // CLRSR_u6 = 358
2255	CEFBS_None, // CLZ_l2r = 359
2256	CEFBS_None, // CRC8_l4r = 360
2257	CEFBS_None, // CRC_l3r = 361
2258	CEFBS_None, // DCALL_0R = 362
2259	CEFBS_None, // DENTSP_0R = 363
2260	CEFBS_None, // DGETREG_1r = 364
2261	CEFBS_None, // DIVS_l3r = 365
2262	CEFBS_None, // DIVU_l3r = 366
2263	CEFBS_None, // DRESTSP_0R = 367
2264	CEFBS_None, // DRET_0R = 368
2265	CEFBS_None, // ECALLF_1r = 369
2266	CEFBS_None, // ECALLT_1r = 370
2267	CEFBS_None, // EDU_1r = 371
2268	CEFBS_None, // EEF_2r = 372
2269	CEFBS_None, // EET_2r = 373
2270	CEFBS_None, // EEU_1r = 374
2271	CEFBS_None, // ENDIN_2r = 375
2272	CEFBS_None, // ENTSP_lu6 = 376
2273	CEFBS_None, // ENTSP_u6 = 377
2274	CEFBS_None, // EQ_2rus = 378
2275	CEFBS_None, // EQ_3r = 379
2276	CEFBS_None, // EXTDP_lu6 = 380
2277	CEFBS_None, // EXTDP_u6 = 381
2278	CEFBS_None, // EXTSP_lu6 = 382
2279	CEFBS_None, // EXTSP_u6 = 383
2280	CEFBS_None, // FREER_1r = 384
2281	CEFBS_None, // FREET_0R = 385
2282	CEFBS_None, // GETD_l2r = 386
2283	CEFBS_None, // GETED_0R = 387
2284	CEFBS_None, // GETET_0R = 388
2285	CEFBS_None, // GETID_0R = 389
2286	CEFBS_None, // GETKEP_0R = 390
2287	CEFBS_None, // GETKSP_0R = 391
2288	CEFBS_None, // GETN_l2r = 392
2289	CEFBS_None, // GETPS_l2r = 393
2290	CEFBS_None, // GETR_rus = 394
2291	CEFBS_None, // GETSR_lu6 = 395
2292	CEFBS_None, // GETSR_u6 = 396
2293	CEFBS_None, // GETST_2r = 397
2294	CEFBS_None, // GETTS_2r = 398
2295	CEFBS_None, // INCT_2r = 399
2296	CEFBS_None, // INITCP_2r = 400
2297	CEFBS_None, // INITDP_2r = 401
2298	CEFBS_None, // INITLR_l2r = 402
2299	CEFBS_None, // INITPC_2r = 403
2300	CEFBS_None, // INITSP_2r = 404
2301	CEFBS_None, // INPW_l2rus = 405
2302	CEFBS_None, // INSHR_2r = 406
2303	CEFBS_None, // INT_2r = 407
2304	CEFBS_None, // IN_2r = 408
2305	CEFBS_None, // KCALL_1r = 409
2306	CEFBS_None, // KCALL_lu6 = 410
2307	CEFBS_None, // KCALL_u6 = 411
2308	CEFBS_None, // KENTSP_lu6 = 412
2309	CEFBS_None, // KENTSP_u6 = 413
2310	CEFBS_None, // KRESTSP_lu6 = 414
2311	CEFBS_None, // KRESTSP_u6 = 415
2312	CEFBS_None, // KRET_0R = 416
2313	CEFBS_None, // LADD_l5r = 417
2314	CEFBS_None, // LD16S_3r = 418
2315	CEFBS_None, // LD8U_3r = 419
2316	CEFBS_None, // LDA16B_l3r = 420
2317	CEFBS_None, // LDA16F_l3r = 421
2318	CEFBS_None, // LDAPB_lu10 = 422
2319	CEFBS_None, // LDAPB_u10 = 423
2320	CEFBS_None, // LDAPF_lu10 = 424
2321	CEFBS_None, // LDAPF_lu10_ba = 425
2322	CEFBS_None, // LDAPF_u10 = 426
2323	CEFBS_None, // LDAWB_l2rus = 427
2324	CEFBS_None, // LDAWB_l3r = 428
2325	CEFBS_None, // LDAWCP_lu6 = 429
2326	CEFBS_None, // LDAWCP_u6 = 430
2327	CEFBS_None, // LDAWDP_lru6 = 431
2328	CEFBS_None, // LDAWDP_ru6 = 432
2329	CEFBS_None, // LDAWF_l2rus = 433
2330	CEFBS_None, // LDAWF_l3r = 434
2331	CEFBS_None, // LDAWSP_lru6 = 435
2332	CEFBS_None, // LDAWSP_ru6 = 436
2333	CEFBS_None, // LDC_lru6 = 437
2334	CEFBS_None, // LDC_ru6 = 438
2335	CEFBS_None, // LDET_0R = 439
2336	CEFBS_None, // LDIVU_l5r = 440
2337	CEFBS_None, // LDSED_0R = 441
2338	CEFBS_None, // LDSPC_0R = 442
2339	CEFBS_None, // LDSSR_0R = 443
2340	CEFBS_None, // LDWCP_lru6 = 444
2341	CEFBS_None, // LDWCP_lu10 = 445
2342	CEFBS_None, // LDWCP_ru6 = 446
2343	CEFBS_None, // LDWCP_u10 = 447
2344	CEFBS_None, // LDWDP_lru6 = 448
2345	CEFBS_None, // LDWDP_ru6 = 449
2346	CEFBS_None, // LDWSP_lru6 = 450
2347	CEFBS_None, // LDWSP_ru6 = 451
2348	CEFBS_None, // LDW_2rus = 452
2349	CEFBS_None, // LDW_3r = 453
2350	CEFBS_None, // LMUL_l6r = 454
2351	CEFBS_None, // LSS_3r = 455
2352	CEFBS_None, // LSUB_l5r = 456
2353	CEFBS_None, // LSU_3r = 457
2354	CEFBS_None, // MACCS_l4r = 458
2355	CEFBS_None, // MACCU_l4r = 459
2356	CEFBS_None, // MJOIN_1r = 460
2357	CEFBS_None, // MKMSK_2r = 461
2358	CEFBS_None, // MKMSK_rus = 462
2359	CEFBS_None, // MSYNC_1r = 463
2360	CEFBS_None, // MUL_l3r = 464
2361	CEFBS_None, // NEG = 465
2362	CEFBS_None, // NOT = 466
2363	CEFBS_None, // OR_3r = 467
2364	CEFBS_None, // OUTCT_2r = 468
2365	CEFBS_None, // OUTCT_rus = 469
2366	CEFBS_None, // OUTPW_l2rus = 470
2367	CEFBS_None, // OUTSHR_2r = 471
2368	CEFBS_None, // OUTT_2r = 472
2369	CEFBS_None, // OUT_2r = 473
2370	CEFBS_None, // PEEK_2r = 474
2371	CEFBS_None, // REMS_l3r = 475
2372	CEFBS_None, // REMU_l3r = 476
2373	CEFBS_None, // RETSP_lu6 = 477
2374	CEFBS_None, // RETSP_u6 = 478
2375	CEFBS_None, // SETCLK_l2r = 479
2376	CEFBS_None, // SETCP_1r = 480
2377	CEFBS_None, // SETC_l2r = 481
2378	CEFBS_None, // SETC_lru6 = 482
2379	CEFBS_None, // SETC_ru6 = 483
2380	CEFBS_None, // SETDP_1r = 484
2381	CEFBS_None, // SETD_2r = 485
2382	CEFBS_None, // SETEV_1r = 486
2383	CEFBS_None, // SETKEP_0R = 487
2384	CEFBS_None, // SETN_l2r = 488
2385	CEFBS_None, // SETPSC_2r = 489
2386	CEFBS_None, // SETPS_l2r = 490
2387	CEFBS_None, // SETPT_2r = 491
2388	CEFBS_None, // SETRDY_l2r = 492
2389	CEFBS_None, // SETSP_1r = 493
2390	CEFBS_None, // SETSR_branch_lu6 = 494
2391	CEFBS_None, // SETSR_branch_u6 = 495
2392	CEFBS_None, // SETSR_lu6 = 496
2393	CEFBS_None, // SETSR_u6 = 497
2394	CEFBS_None, // SETTW_l2r = 498
2395	CEFBS_None, // SETV_1r = 499
2396	CEFBS_None, // SEXT_2r = 500
2397	CEFBS_None, // SEXT_rus = 501
2398	CEFBS_None, // SHL_2rus = 502
2399	CEFBS_None, // SHL_3r = 503
2400	CEFBS_None, // SHR_2rus = 504
2401	CEFBS_None, // SHR_3r = 505
2402	CEFBS_None, // SSYNC_0r = 506
2403	CEFBS_None, // ST16_l3r = 507
2404	CEFBS_None, // ST8_l3r = 508
2405	CEFBS_None, // STET_0R = 509
2406	CEFBS_None, // STSED_0R = 510
2407	CEFBS_None, // STSPC_0R = 511
2408	CEFBS_None, // STSSR_0R = 512
2409	CEFBS_None, // STWDP_lru6 = 513
2410	CEFBS_None, // STWDP_ru6 = 514
2411	CEFBS_None, // STWSP_lru6 = 515
2412	CEFBS_None, // STWSP_ru6 = 516
2413	CEFBS_None, // STW_2rus = 517
2414	CEFBS_None, // STW_l3r = 518
2415	CEFBS_None, // SUB_2rus = 519
2416	CEFBS_None, // SUB_3r = 520
2417	CEFBS_None, // SYNCR_1r = 521
2418	CEFBS_None, // TESTCT_2r = 522
2419	CEFBS_None, // TESTLCL_l2r = 523
2420	CEFBS_None, // TESTWCT_2r = 524
2421	CEFBS_None, // TSETMR_2r = 525
2422	CEFBS_None, // TSETR_3r = 526
2423	CEFBS_None, // TSTART_1R = 527
2424	CEFBS_None, // WAITEF_1R = 528
2425	CEFBS_None, // WAITET_1R = 529
2426	CEFBS_None, // WAITEU_0R = 530
2427	CEFBS_None, // XOR_l3r = 531
2428	CEFBS_None, // ZEXT_2r = 532
2429	CEFBS_None, // ZEXT_rus = 533
2430	};
2431
2432	assert(Opcode < `534`);
2433	return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2434	}
2435
2436	} // end namespace llvm::XCore_MC
2437	#endif // GET_COMPUTE_FEATURES
2438
2439	#ifdef GET_AVAILABLE_OPCODE_CHECKER
2440	#undef GET_AVAILABLE_OPCODE_CHECKER
2441	namespace llvm::XCore_MC {
2442	bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2443	FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2444	FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2445	FeatureBitset MissingFeatures =
2446	(AvailableFeatures & RequiredFeatures) ^
2447	RequiredFeatures;
2448	return !MissingFeatures.any();
2449	}
2450	} // end namespace llvm::XCore_MC
2451	#endif // GET_AVAILABLE_OPCODE_CHECKER
2452
2453	#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2454	#undef ENABLE_INSTR_PREDICATE_VERIFIER
2455	#include <sstream>
2456
2457	namespace llvm::XCore_MC {
2458	#ifndef NDEBUG
2459	static const char *SubtargetFeatureNames[] = {
2460	nullptr
2461	};
2462
2463	#endif // NDEBUG
2464
2465	void verifyInstructionPredicates(
2466	unsigned Opcode, const FeatureBitset &Features) {
2467	#ifndef NDEBUG
2468	FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2469	FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2470	FeatureBitset MissingFeatures =
2471	(AvailableFeatures & RequiredFeatures) ^
2472	RequiredFeatures;
2473	if (MissingFeatures.any()) {
2474	std::ostringstream Msg;
2475	Msg << "Attempting to emit " << &XCoreInstrNameData[XCoreInstrNameIndices[Opcode]]
2476	<< " instruction but the ";
2477	for (unsigned i = `0`, e = MissingFeatures.size(); i != e; ++i)
2478	if (MissingFeatures.test(i))
2479	Msg << SubtargetFeatureNames[i] << " ";
2480	Msg << "predicate(s) are not met";
2481	report_fatal_error(Msg.str().c_str());
2482	}
2483	#endif // NDEBUG
2484	}
2485	} // end namespace llvm::XCore_MC
2486	#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2487
2488

Browse the source code of llvm_projects/build/lib/Target/XCore/XCoreGenInstrInfo.inc