1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass XCoreMCRegisterClasses[];
17
18namespace XCore {
19enum : unsigned {
20 NoRegister,
21 CP = 1,
22 DP = 2,
23 LR = 3,
24 SP = 4,
25 R0 = 5,
26 R1 = 6,
27 R2 = 7,
28 R3 = 8,
29 R4 = 9,
30 R5 = 10,
31 R6 = 11,
32 R7 = 12,
33 R8 = 13,
34 R9 = 14,
35 R10 = 15,
36 R11 = 16,
37 NUM_TARGET_REGS // 17
38};
39} // end namespace XCore
40
41// Register classes
42
43namespace XCore {
44enum {
45 RRegsRegClassID = 0,
46 GRRegsRegClassID = 1,
47
48};
49} // end namespace XCore
50
51// Register pressure sets enum.
52namespace XCore {
53enum RegisterPressureSets {
54 GRRegs = 0,
55};
56} // end namespace XCore
57
58} // end namespace llvm
59
60#endif // GET_REGINFO_ENUM
61
62/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
63|* *|
64|* MC Register Information *|
65|* *|
66|* Automatically generated file, do not edit! *|
67|* *|
68\*===----------------------------------------------------------------------===*/
69
70
71#ifdef GET_REGINFO_MC_DESC
72#undef GET_REGINFO_MC_DESC
73
74namespace llvm {
75
76extern const int16_t XCoreRegDiffLists[] = {
77 /* 0 */ 0,
78};
79
80extern const LaneBitmask XCoreLaneMaskLists[] = {
81 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
82};
83
84extern const uint16_t XCoreSubRegIdxLists[] = {
85 /* 0 */
86 /* dummy */ 0
87};
88
89
90#ifdef __GNUC__
91#pragma GCC diagnostic push
92#pragma GCC diagnostic ignored "-Woverlength-strings"
93#endif
94extern const char XCoreRegStrings[] = {
95 /* 0 */ "R10\000"
96 /* 4 */ "R0\000"
97 /* 7 */ "R11\000"
98 /* 11 */ "R1\000"
99 /* 14 */ "R2\000"
100 /* 17 */ "R3\000"
101 /* 20 */ "R4\000"
102 /* 23 */ "R5\000"
103 /* 26 */ "R6\000"
104 /* 29 */ "R7\000"
105 /* 32 */ "R8\000"
106 /* 35 */ "R9\000"
107 /* 38 */ "CP\000"
108 /* 41 */ "DP\000"
109 /* 44 */ "SP\000"
110 /* 47 */ "LR\000"
111};
112#ifdef __GNUC__
113#pragma GCC diagnostic pop
114#endif
115
116extern const MCRegisterDesc XCoreRegDesc[] = { // Descriptors
117 { 3, 0, 0, 0, 0, 0, 0, 0 },
118 { 38, 0, 0, 0, 0, 0, 0, 0 },
119 { 41, 0, 0, 0, 1, 0, 0, 0 },
120 { 47, 0, 0, 0, 2, 0, 0, 0 },
121 { 44, 0, 0, 0, 3, 0, 0, 0 },
122 { 4, 0, 0, 0, 4, 0, 0, 0 },
123 { 11, 0, 0, 0, 5, 0, 0, 0 },
124 { 14, 0, 0, 0, 6, 0, 0, 0 },
125 { 17, 0, 0, 0, 7, 0, 0, 0 },
126 { 20, 0, 0, 0, 8, 0, 0, 0 },
127 { 23, 0, 0, 0, 9, 0, 0, 0 },
128 { 26, 0, 0, 0, 10, 0, 0, 0 },
129 { 29, 0, 0, 0, 11, 0, 0, 0 },
130 { 32, 0, 0, 0, 12, 0, 0, 0 },
131 { 35, 0, 0, 0, 13, 0, 0, 0 },
132 { 0, 0, 0, 0, 14, 0, 0, 0 },
133 { 7, 0, 0, 0, 15, 0, 0, 0 },
134};
135
136extern const MCPhysReg XCoreRegUnitRoots[][2] = {
137 { XCore::CP },
138 { XCore::DP },
139 { XCore::LR },
140 { XCore::SP },
141 { XCore::R0 },
142 { XCore::R1 },
143 { XCore::R2 },
144 { XCore::R3 },
145 { XCore::R4 },
146 { XCore::R5 },
147 { XCore::R6 },
148 { XCore::R7 },
149 { XCore::R8 },
150 { XCore::R9 },
151 { XCore::R10 },
152 { XCore::R11 },
153};
154
155namespace { // Register classes...
156 // RRegs Register Class...
157 const MCPhysReg RRegs[] = {
158 XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11, XCore::CP, XCore::DP, XCore::SP, XCore::LR,
159 };
160
161 // RRegs Bit set.
162 const uint8_t RRegsBits[] = {
163 0xfe, 0xff, 0x01,
164 };
165
166 // GRRegs Register Class...
167 const MCPhysReg GRRegs[] = {
168 XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11,
169 };
170
171 // GRRegs Bit set.
172 const uint8_t GRRegsBits[] = {
173 0xe0, 0xff, 0x01,
174 };
175
176} // end anonymous namespace
177
178
179#ifdef __GNUC__
180#pragma GCC diagnostic push
181#pragma GCC diagnostic ignored "-Woverlength-strings"
182#endif
183extern const char XCoreRegClassStrings[] = {
184 /* 0 */ "GRRegs\000"
185};
186#ifdef __GNUC__
187#pragma GCC diagnostic pop
188#endif
189
190extern const MCRegisterClass XCoreMCRegisterClasses[] = {
191 { RRegs, RRegsBits, 1, 16, sizeof(RRegsBits), XCore::RRegsRegClassID, 32, 1, false, false },
192 { GRRegs, GRRegsBits, 0, 12, sizeof(GRRegsBits), XCore::GRRegsRegClassID, 32, 1, true, false },
193};
194
195// XCore Dwarf<->LLVM register mappings.
196extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[] = {
197 { 0U, XCore::R0 },
198 { 1U, XCore::R1 },
199 { 2U, XCore::R2 },
200 { 3U, XCore::R3 },
201 { 4U, XCore::R4 },
202 { 5U, XCore::R5 },
203 { 6U, XCore::R6 },
204 { 7U, XCore::R7 },
205 { 8U, XCore::R8 },
206 { 9U, XCore::R9 },
207 { 10U, XCore::R10 },
208 { 11U, XCore::R11 },
209 { 12U, XCore::CP },
210 { 13U, XCore::DP },
211 { 14U, XCore::SP },
212 { 15U, XCore::LR },
213};
214extern const unsigned XCoreDwarfFlavour0Dwarf2LSize = std::size(XCoreDwarfFlavour0Dwarf2L);
215
216extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[] = {
217 { 0U, XCore::R0 },
218 { 1U, XCore::R1 },
219 { 2U, XCore::R2 },
220 { 3U, XCore::R3 },
221 { 4U, XCore::R4 },
222 { 5U, XCore::R5 },
223 { 6U, XCore::R6 },
224 { 7U, XCore::R7 },
225 { 8U, XCore::R8 },
226 { 9U, XCore::R9 },
227 { 10U, XCore::R10 },
228 { 11U, XCore::R11 },
229 { 12U, XCore::CP },
230 { 13U, XCore::DP },
231 { 14U, XCore::SP },
232 { 15U, XCore::LR },
233};
234extern const unsigned XCoreEHFlavour0Dwarf2LSize = std::size(XCoreEHFlavour0Dwarf2L);
235
236extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[] = {
237 { XCore::CP, 12U },
238 { XCore::DP, 13U },
239 { XCore::LR, 15U },
240 { XCore::SP, 14U },
241 { XCore::R0, 0U },
242 { XCore::R1, 1U },
243 { XCore::R2, 2U },
244 { XCore::R3, 3U },
245 { XCore::R4, 4U },
246 { XCore::R5, 5U },
247 { XCore::R6, 6U },
248 { XCore::R7, 7U },
249 { XCore::R8, 8U },
250 { XCore::R9, 9U },
251 { XCore::R10, 10U },
252 { XCore::R11, 11U },
253};
254extern const unsigned XCoreDwarfFlavour0L2DwarfSize = std::size(XCoreDwarfFlavour0L2Dwarf);
255
256extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[] = {
257 { XCore::CP, 12U },
258 { XCore::DP, 13U },
259 { XCore::LR, 15U },
260 { XCore::SP, 14U },
261 { XCore::R0, 0U },
262 { XCore::R1, 1U },
263 { XCore::R2, 2U },
264 { XCore::R3, 3U },
265 { XCore::R4, 4U },
266 { XCore::R5, 5U },
267 { XCore::R6, 6U },
268 { XCore::R7, 7U },
269 { XCore::R8, 8U },
270 { XCore::R9, 9U },
271 { XCore::R10, 10U },
272 { XCore::R11, 11U },
273};
274extern const unsigned XCoreEHFlavour0L2DwarfSize = std::size(XCoreEHFlavour0L2Dwarf);
275
276extern const uint16_t XCoreRegEncodingTable[] = {
277 0,
278 0,
279 0,
280 0,
281 0,
282 0,
283 0,
284 0,
285 0,
286 0,
287 0,
288 0,
289 0,
290 0,
291 0,
292 0,
293 0,
294};
295static inline void InitXCoreMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
296 RI->InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC, XCoreMCRegisterClasses, 2, XCoreRegUnitRoots, 16, XCoreRegDiffLists, XCoreLaneMaskLists, XCoreRegStrings, XCoreRegClassStrings, XCoreSubRegIdxLists, 1,
297XCoreRegEncodingTable);
298
299 switch (DwarfFlavour) {
300 default:
301 llvm_unreachable("Unknown DWARF flavour");
302 case 0:
303 RI->mapDwarfRegsToLLVMRegs(XCoreDwarfFlavour0Dwarf2L, XCoreDwarfFlavour0Dwarf2LSize, false);
304 break;
305 }
306 switch (EHFlavour) {
307 default:
308 llvm_unreachable("Unknown DWARF flavour");
309 case 0:
310 RI->mapDwarfRegsToLLVMRegs(XCoreEHFlavour0Dwarf2L, XCoreEHFlavour0Dwarf2LSize, true);
311 break;
312 }
313 switch (DwarfFlavour) {
314 default:
315 llvm_unreachable("Unknown DWARF flavour");
316 case 0:
317 RI->mapLLVMRegsToDwarfRegs(XCoreDwarfFlavour0L2Dwarf, XCoreDwarfFlavour0L2DwarfSize, false);
318 break;
319 }
320 switch (EHFlavour) {
321 default:
322 llvm_unreachable("Unknown DWARF flavour");
323 case 0:
324 RI->mapLLVMRegsToDwarfRegs(XCoreEHFlavour0L2Dwarf, XCoreEHFlavour0L2DwarfSize, true);
325 break;
326 }
327}
328
329} // end namespace llvm
330
331#endif // GET_REGINFO_MC_DESC
332
333/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
334|* *|
335|* Register Information Header Fragment *|
336|* *|
337|* Automatically generated file, do not edit! *|
338|* *|
339\*===----------------------------------------------------------------------===*/
340
341
342#ifdef GET_REGINFO_HEADER
343#undef GET_REGINFO_HEADER
344
345#include "llvm/CodeGen/TargetRegisterInfo.h"
346
347namespace llvm {
348
349class XCoreFrameLowering;
350
351struct XCoreGenRegisterInfo : public TargetRegisterInfo {
352 explicit XCoreGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
353 unsigned PC = 0, unsigned HwMode = 0);
354 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
355 unsigned getRegUnitWeight(unsigned RegUnit) const override;
356 unsigned getNumRegPressureSets() const override;
357 const char *getRegPressureSetName(unsigned Idx) const override;
358 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
359 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
360 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
361 ArrayRef<const char *> getRegMaskNames() const override;
362 ArrayRef<const uint32_t *> getRegMasks() const override;
363 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
364 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
365 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
366 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
367 bool isConstantPhysReg(MCRegister PhysReg) const override final;
368 /// Devirtualized TargetFrameLowering.
369 static const XCoreFrameLowering *getFrameLowering(
370 const MachineFunction &MF);
371};
372
373namespace XCore { // Register classes
374 extern const TargetRegisterClass RRegsRegClass;
375 extern const TargetRegisterClass GRRegsRegClass;
376} // end namespace XCore
377
378} // end namespace llvm
379
380#endif // GET_REGINFO_HEADER
381
382/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
383|* *|
384|* Target Register and Register Classes Information *|
385|* *|
386|* Automatically generated file, do not edit! *|
387|* *|
388\*===----------------------------------------------------------------------===*/
389
390
391#ifdef GET_REGINFO_TARGET_DESC
392#undef GET_REGINFO_TARGET_DESC
393
394namespace llvm {
395
396extern const MCRegisterClass XCoreMCRegisterClasses[];
397
398static const MVT::SimpleValueType VTLists[] = {
399 /* 0 */ MVT::i32, MVT::Other,
400};
401
402static const char *SubRegIndexNameTable[] = { "" };
403
404static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
405 { 65535, 65535 },
406};
407
408
409static const LaneBitmask SubRegIndexLaneMaskTable[] = {
410 LaneBitmask::getAll(),
411 };
412
413
414
415static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
416 // Mode = 0 (Default)
417 { 32, 32, 32, /*VTLists+*/0 }, // RRegs
418 { 32, 32, 32, /*VTLists+*/0 }, // GRRegs
419};
420static const uint32_t RRegsSubClassMask[] = {
421 0x00000003,
422};
423
424static const uint32_t GRRegsSubClassMask[] = {
425 0x00000002,
426};
427
428static const uint16_t SuperRegIdxSeqs[] = {
429 /* 0 */ 0,
430};
431
432static unsigned const GRRegsSuperclasses[] = {
433 XCore::RRegsRegClassID,
434};
435
436
437namespace XCore { // Register class instances
438 extern const TargetRegisterClass RRegsRegClass = {
439 &XCoreMCRegisterClasses[RRegsRegClassID],
440 RRegsSubClassMask,
441 SuperRegIdxSeqs + 0,
442 LaneBitmask(0x0000000000000001),
443 0,
444 false,
445 0x00, /* TSFlags */
446 false, /* HasDisjunctSubRegs */
447 false, /* CoveredBySubRegs */
448 nullptr, 0,
449 nullptr
450 };
451
452 extern const TargetRegisterClass GRRegsRegClass = {
453 &XCoreMCRegisterClasses[GRRegsRegClassID],
454 GRRegsSubClassMask,
455 SuperRegIdxSeqs + 0,
456 LaneBitmask(0x0000000000000001),
457 0,
458 false,
459 0x00, /* TSFlags */
460 false, /* HasDisjunctSubRegs */
461 false, /* CoveredBySubRegs */
462 GRRegsSuperclasses, 1,
463 nullptr
464 };
465
466} // end namespace XCore
467
468namespace {
469 const TargetRegisterClass *const RegisterClasses[] = {
470 &XCore::RRegsRegClass,
471 &XCore::GRRegsRegClass,
472 };
473} // end anonymous namespace
474
475static const uint8_t CostPerUseTable[] = {
4760, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
477
478
479static const bool InAllocatableClassTable[] = {
480false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
481
482
483static const TargetRegisterInfoDesc XCoreRegInfoDesc = { // Extra Descriptors
484CostPerUseTable, 1, InAllocatableClassTable};
485
486/// Get the weight in units of pressure for this register class.
487const RegClassWeight &XCoreGenRegisterInfo::
488getRegClassWeight(const TargetRegisterClass *RC) const {
489 static const RegClassWeight RCWeightTable[] = {
490 {0, 12}, // RRegs
491 {1, 12}, // GRRegs
492 };
493 return RCWeightTable[RC->getID()];
494}
495
496/// Get the weight in units of pressure for this register unit.
497unsigned XCoreGenRegisterInfo::
498getRegUnitWeight(unsigned RegUnit) const {
499 assert(RegUnit < 16 && "invalid register unit");
500 // All register units have unit weight.
501 return 1;
502}
503
504
505// Get the number of dimensions of register pressure.
506unsigned XCoreGenRegisterInfo::getNumRegPressureSets() const {
507 return 1;
508}
509
510// Get the name of this register unit pressure set.
511const char *XCoreGenRegisterInfo::
512getRegPressureSetName(unsigned Idx) const {
513 static const char *PressureNameTable[] = {
514 "GRRegs",
515 };
516 return PressureNameTable[Idx];
517}
518
519// Get the register unit pressure limit for this dimension.
520// This limit must be adjusted dynamically for reserved registers.
521unsigned XCoreGenRegisterInfo::
522getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
523 static const uint8_t PressureLimitTable[] = {
524 12, // 0: GRRegs
525 };
526 return PressureLimitTable[Idx];
527}
528
529/// Table of pressure sets per register class or unit.
530static const int RCSetsTable[] = {
531 /* 0 */ 0, -1,
532};
533
534/// Get the dimensions of register pressure impacted by this register class.
535/// Returns a -1 terminated array of pressure set IDs
536const int *XCoreGenRegisterInfo::
537getRegClassPressureSets(const TargetRegisterClass *RC) const {
538 static const uint8_t RCSetStartTable[] = {
539 1,0,};
540 return &RCSetsTable[RCSetStartTable[RC->getID()]];
541}
542
543/// Get the dimensions of register pressure impacted by this register unit.
544/// Returns a -1 terminated array of pressure set IDs
545const int *XCoreGenRegisterInfo::
546getRegUnitPressureSets(unsigned RegUnit) const {
547 assert(RegUnit < 16 && "invalid register unit");
548 static const uint8_t RUSetStartTable[] = {
549 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,};
550 return &RCSetsTable[RUSetStartTable[RegUnit]];
551}
552
553extern const MCRegisterDesc XCoreRegDesc[];
554extern const int16_t XCoreRegDiffLists[];
555extern const LaneBitmask XCoreLaneMaskLists[];
556extern const char XCoreRegStrings[];
557extern const char XCoreRegClassStrings[];
558extern const MCPhysReg XCoreRegUnitRoots[][2];
559extern const uint16_t XCoreSubRegIdxLists[];
560extern const uint16_t XCoreRegEncodingTable[];
561// XCore Dwarf<->LLVM register mappings.
562extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[];
563extern const unsigned XCoreDwarfFlavour0Dwarf2LSize;
564
565extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[];
566extern const unsigned XCoreEHFlavour0Dwarf2LSize;
567
568extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[];
569extern const unsigned XCoreDwarfFlavour0L2DwarfSize;
570
571extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[];
572extern const unsigned XCoreEHFlavour0L2DwarfSize;
573
574XCoreGenRegisterInfo::
575XCoreGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
576 unsigned PC, unsigned HwMode)
577 : TargetRegisterInfo(&XCoreRegInfoDesc, RegisterClasses, RegisterClasses+2,
578 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
579 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
580 InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC,
581 XCoreMCRegisterClasses, 2,
582 XCoreRegUnitRoots,
583 16,
584 XCoreRegDiffLists,
585 XCoreLaneMaskLists,
586 XCoreRegStrings,
587 XCoreRegClassStrings,
588 XCoreSubRegIdxLists,
589 1,
590 XCoreRegEncodingTable);
591
592 switch (DwarfFlavour) {
593 default:
594 llvm_unreachable("Unknown DWARF flavour");
595 case 0:
596 mapDwarfRegsToLLVMRegs(XCoreDwarfFlavour0Dwarf2L, XCoreDwarfFlavour0Dwarf2LSize, false);
597 break;
598 }
599 switch (EHFlavour) {
600 default:
601 llvm_unreachable("Unknown DWARF flavour");
602 case 0:
603 mapDwarfRegsToLLVMRegs(XCoreEHFlavour0Dwarf2L, XCoreEHFlavour0Dwarf2LSize, true);
604 break;
605 }
606 switch (DwarfFlavour) {
607 default:
608 llvm_unreachable("Unknown DWARF flavour");
609 case 0:
610 mapLLVMRegsToDwarfRegs(XCoreDwarfFlavour0L2Dwarf, XCoreDwarfFlavour0L2DwarfSize, false);
611 break;
612 }
613 switch (EHFlavour) {
614 default:
615 llvm_unreachable("Unknown DWARF flavour");
616 case 0:
617 mapLLVMRegsToDwarfRegs(XCoreEHFlavour0L2Dwarf, XCoreEHFlavour0L2DwarfSize, true);
618 break;
619 }
620}
621
622
623
624ArrayRef<const uint32_t *> XCoreGenRegisterInfo::getRegMasks() const {
625 return {};
626}
627
628bool XCoreGenRegisterInfo::
629isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
630 return
631 false;
632}
633
634bool XCoreGenRegisterInfo::
635isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
636 return
637 false;
638}
639
640bool XCoreGenRegisterInfo::
641isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
642 return
643 false;
644}
645
646bool XCoreGenRegisterInfo::
647isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
648 return
649 false;
650}
651
652bool XCoreGenRegisterInfo::
653isConstantPhysReg(MCRegister PhysReg) const {
654 return
655 false;
656}
657
658ArrayRef<const char *> XCoreGenRegisterInfo::getRegMaskNames() const {
659 return {};
660}
661
662const XCoreFrameLowering *
663XCoreGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
664 return static_cast<const XCoreFrameLowering *>(
665 MF.getSubtarget().getFrameLowering());
666}
667
668} // end namespace llvm
669
670#endif // GET_REGINFO_TARGET_DESC
671
672