1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14} // end namespace llvm
15
16#endif // GET_SUBTARGETINFO_ENUM
17
18
19#ifdef GET_SUBTARGETINFO_MACRO
20#undef GET_SUBTARGETINFO_MACRO
21#endif // GET_SUBTARGETINFO_MACRO
22
23
24#ifdef GET_SUBTARGETINFO_MC_DESC
25#undef GET_SUBTARGETINFO_MC_DESC
26
27namespace llvm {
28
29#ifdef DBGFIELD
30#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
31#endif
32#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
33#define DBGFIELD(x) x,
34#define DBGVAL_OR_NULLPTR(x) x
35#else
36#define DBGFIELD(x)
37#define DBGVAL_OR_NULLPTR(x) nullptr
38#endif
39
40// ===============================================================
41// Data tables for the new per-operand machine model.
42
43// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
44extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[] = {
45 { 0, 0, 0 }, // Invalid
46}; // XCoreWriteProcResTable
47
48// {Cycles, WriteResourceID}
49extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[] = {
50 { 0, 0}, // Invalid
51}; // XCoreWriteLatencyTable
52
53// {UseIdx, WriteResourceID, Cycles}
54extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[] = {
55 {0, 0, 0}, // Invalid
56}; // XCoreReadAdvanceTable
57
58#ifdef __GNUC__
59#pragma GCC diagnostic push
60#pragma GCC diagnostic ignored "-Woverlength-strings"
61#endif
62static constexpr char XCoreSchedClassNamesStorage[] =
63 "\0"
64 "InvalidSchedClass\0"
65 ;
66#ifdef __GNUC__
67#pragma GCC diagnostic pop
68#endif
69
70static constexpr llvm::StringTable XCoreSchedClassNames =
71 XCoreSchedClassNamesStorage;
72
73static const llvm::MCSchedModel NoSchedModel = {
74 MCSchedModel::DefaultIssueWidth,
75 MCSchedModel::DefaultMicroOpBufferSize,
76 MCSchedModel::DefaultLoopMicroOpBufferSize,
77 MCSchedModel::DefaultLoadLatency,
78 MCSchedModel::DefaultHighLatency,
79 MCSchedModel::DefaultMispredictPenalty,
80 false, // PostRAScheduler
81 false, // CompleteModel
82 false, // EnableIntervals
83 0, // Processor ID
84 nullptr, nullptr, 0, 0, // No instruction-level machine model.
85 DBGVAL_OR_NULLPTR(&XCoreSchedClassNames), // SchedClassNames
86 nullptr, // No Itinerary
87 nullptr // No extra processor descriptor
88};
89
90#undef DBGFIELD
91
92#undef DBGVAL_OR_NULLPTR
93
94// Sorted (by key) array of values for CPU subtype.
95extern const llvm::SubtargetSubTypeKV XCoreSubTypeKV[] = {
96 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
97 { "xs1b-generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
98};
99
100// Sorted array of names of CPU subtypes, including aliases.
101extern const llvm::StringRef XCoreNames[] = {
102"generic",
103"xs1b-generic"};
104
105namespace XCore_MC {
106unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
107 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
108 // Don't know how to resolve this scheduling class.
109 return 0;
110}
111} // end namespace XCore_MC
112
113struct XCoreGenMCSubtargetInfo : public MCSubtargetInfo {
114 XCoreGenMCSubtargetInfo(const Triple &TT,
115 StringRef CPU, StringRef TuneCPU, StringRef FS,
116 ArrayRef<StringRef> PN,
117 ArrayRef<SubtargetFeatureKV> PF,
118 ArrayRef<SubtargetSubTypeKV> PD,
119 const MCWriteProcResEntry *WPR,
120 const MCWriteLatencyEntry *WL,
121 const MCReadAdvanceEntry *RA, const InstrStage *IS,
122 const unsigned *OC, const unsigned *FP) :
123 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
124 WPR, WL, RA, IS, OC, FP) { }
125
126 unsigned resolveVariantSchedClass(unsigned SchedClass,
127 const MCInst *MI, const MCInstrInfo *MCII,
128 unsigned CPUID) const override {
129 return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
130 }
131};
132
133static inline MCSubtargetInfo *createXCoreMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
134 return new XCoreGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, XCoreNames, {}, XCoreSubTypeKV,
135 XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
136 nullptr, nullptr, nullptr);
137}
138
139} // end namespace llvm
140
141#endif // GET_SUBTARGETINFO_MC_DESC
142
143
144#ifdef GET_SUBTARGETINFO_TARGET_DESC
145#undef GET_SUBTARGETINFO_TARGET_DESC
146
147#include "llvm/ADT/BitmaskEnum.h"
148#include "llvm/Support/Debug.h"
149#include "llvm/Support/raw_ostream.h"
150
151// ParseSubtargetFeatures - Parses features string setting specified
152// subtarget options.
153void llvm::XCoreSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
154 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
155 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
156 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
157}
158#endif // GET_SUBTARGETINFO_TARGET_DESC
159
160
161#ifdef GET_SUBTARGETINFO_HEADER
162#undef GET_SUBTARGETINFO_HEADER
163
164namespace llvm {
165class DFAPacketizer;
166namespace XCore_MC {
167unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
168} // end namespace XCore_MC
169
170struct XCoreGenSubtargetInfo : public TargetSubtargetInfo {
171 explicit XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
172public:
173 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
174 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
175 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
176};
177} // end namespace llvm
178
179#endif // GET_SUBTARGETINFO_HEADER
180
181
182#ifdef GET_SUBTARGETINFO_CTOR
183#undef GET_SUBTARGETINFO_CTOR
184
185#include "llvm/CodeGen/TargetSchedule.h"
186
187namespace llvm {
188extern const llvm::StringRef XCoreNames[];
189extern const llvm::SubtargetFeatureKV XCoreFeatureKV[];
190extern const llvm::SubtargetSubTypeKV XCoreSubTypeKV[];
191extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[];
192extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[];
193extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[];
194XCoreGenSubtargetInfo::XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
195 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(XCoreNames, 2), {}, ArrayRef(XCoreSubTypeKV, 2),
196 XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
197 nullptr, nullptr, nullptr) {}
198
199unsigned XCoreGenSubtargetInfo
200::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
201 report_fatal_error("Expected a variant SchedClass");
202} // XCoreGenSubtargetInfo::resolveSchedClass
203
204unsigned XCoreGenSubtargetInfo
205::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
206 return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
207} // XCoreGenSubtargetInfo::resolveVariantSchedClass
208
209} // end namespace llvm
210
211#endif // GET_SUBTARGETINFO_CTOR
212
213
214#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
215#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
216
217#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
218
219
220#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
221#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
222
223#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
224
225