1//===--- RISCV.cpp - RISC-V Helpers for Tools -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "RISCV.h"
10#include "../Clang.h"
11#include "clang/Driver/CommonArgs.h"
12#include "clang/Driver/Driver.h"
13#include "clang/Driver/Options.h"
14#include "llvm/Option/ArgList.h"
15#include "llvm/Support/Error.h"
16#include "llvm/TargetParser/Host.h"
17#include "llvm/TargetParser/RISCVISAInfo.h"
18#include "llvm/TargetParser/RISCVTargetParser.h"
19
20using namespace clang::driver;
21using namespace clang::driver::tools;
22using namespace clang;
23using namespace llvm::opt;
24
25// Returns false if an error is diagnosed.
26static bool getArchFeatures(const Driver &D, StringRef Arch,
27 std::vector<StringRef> &Features,
28 const ArgList &Args) {
29 bool EnableExperimentalExtensions =
30 Args.hasArg(Ids: options::OPT_menable_experimental_extensions);
31 auto ISAInfo =
32 llvm::RISCVISAInfo::parseArchString(Arch, EnableExperimentalExtension: EnableExperimentalExtensions);
33 if (!ISAInfo) {
34 handleAllErrors(E: ISAInfo.takeError(), Handlers: [&](llvm::StringError &ErrMsg) {
35 D.Diag(DiagID: diag::err_drv_invalid_riscv_arch_name)
36 << Arch << ErrMsg.getMessage();
37 });
38
39 return false;
40 }
41
42 for (const std::string &Str : (*ISAInfo)->toFeatures(/*AddAllExtension=*/AddAllExtensions: true,
43 /*IgnoreUnknown=*/false))
44 Features.push_back(x: Args.MakeArgString(Str));
45
46 if (EnableExperimentalExtensions)
47 Features.push_back(x: Args.MakeArgString(Str: "+experimental"));
48
49 return true;
50}
51
52// Get features except standard extension feature
53static void getRISCFeaturesFromMcpu(const Driver &D, const Arg *A,
54 const llvm::Triple &Triple,
55 StringRef Mcpu,
56 std::vector<StringRef> &Features) {
57 bool Is64Bit = Triple.isRISCV64();
58 if (!llvm::RISCV::parseCPU(CPU: Mcpu, IsRV64: Is64Bit)) {
59 // Try inverting Is64Bit in case the CPU is valid, but for the wrong target.
60 if (llvm::RISCV::parseCPU(CPU: Mcpu, IsRV64: !Is64Bit))
61 D.Diag(DiagID: clang::diag::err_drv_invalid_riscv_cpu_name_for_target)
62 << Mcpu << Is64Bit;
63 else
64 D.Diag(DiagID: clang::diag::err_drv_unsupported_option_argument)
65 << A->getSpelling() << Mcpu;
66 }
67}
68
69void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
70 const ArgList &Args,
71 std::vector<StringRef> &Features) {
72 std::string MArch = getRISCVArch(Args, Triple);
73
74 if (!getArchFeatures(D, Arch: MArch, Features, Args))
75 return;
76
77 bool CPUFastScalarUnaligned = false;
78 bool CPUFastVectorUnaligned = false;
79
80 // If users give march and mcpu, get std extension feature from MArch
81 // and other features (ex. mirco architecture feature) from mcpu
82 if (Arg *A = Args.getLastArg(Ids: options::OPT_mcpu_EQ)) {
83 StringRef CPU = A->getValue();
84 if (CPU == "native")
85 CPU = llvm::sys::getHostCPUName();
86
87 getRISCFeaturesFromMcpu(D, A, Triple, Mcpu: CPU, Features);
88
89 if (llvm::RISCV::hasFastScalarUnalignedAccess(CPU))
90 CPUFastScalarUnaligned = true;
91 if (llvm::RISCV::hasFastVectorUnalignedAccess(CPU))
92 CPUFastVectorUnaligned = true;
93 }
94
95// Handle features corresponding to "-ffixed-X" options
96#define RESERVE_REG(REG) \
97 if (Args.hasArg(options::OPT_ffixed_##REG)) \
98 Features.push_back("+reserve-" #REG);
99 RESERVE_REG(x1)
100 RESERVE_REG(x2)
101 RESERVE_REG(x3)
102 RESERVE_REG(x4)
103 RESERVE_REG(x5)
104 RESERVE_REG(x6)
105 RESERVE_REG(x7)
106 RESERVE_REG(x8)
107 RESERVE_REG(x9)
108 RESERVE_REG(x10)
109 RESERVE_REG(x11)
110 RESERVE_REG(x12)
111 RESERVE_REG(x13)
112 RESERVE_REG(x14)
113 RESERVE_REG(x15)
114 RESERVE_REG(x16)
115 RESERVE_REG(x17)
116 RESERVE_REG(x18)
117 RESERVE_REG(x19)
118 RESERVE_REG(x20)
119 RESERVE_REG(x21)
120 RESERVE_REG(x22)
121 RESERVE_REG(x23)
122 RESERVE_REG(x24)
123 RESERVE_REG(x25)
124 RESERVE_REG(x26)
125 RESERVE_REG(x27)
126 RESERVE_REG(x28)
127 RESERVE_REG(x29)
128 RESERVE_REG(x30)
129 RESERVE_REG(x31)
130#undef RESERVE_REG
131
132 // -mrelax is default, unless -mno-relax is specified.
133 if (Args.hasFlag(Pos: options::OPT_mrelax, Neg: options::OPT_mno_relax, Default: true)) {
134 Features.push_back(x: "+relax");
135 // -gsplit-dwarf -mrelax requires DW_AT_high_pc/DW_AT_ranges/... indexing
136 // into .debug_addr, which is currently not implemented.
137 Arg *A;
138 if (getDebugFissionKind(D, Args, Arg&: A) != DwarfFissionKind::None)
139 D.Diag(DiagID: clang::diag::err_drv_riscv_unsupported_with_linker_relaxation)
140 << A->getAsString(Args);
141 } else {
142 Features.push_back(x: "-relax");
143 }
144
145 // If -mstrict-align, -mno-strict-align, -mscalar-strict-align, or
146 // -mno-scalar-strict-align is passed, use it. Otherwise, the
147 // unaligned-scalar-mem is enabled if the CPU supports it or the target is
148 // Android.
149 if (const Arg *A = Args.getLastArg(
150 Ids: options::OPT_mno_strict_align, Ids: options::OPT_mscalar_strict_align,
151 Ids: options::OPT_mstrict_align, Ids: options::OPT_mno_scalar_strict_align)) {
152 if (A->getOption().matches(ID: options::OPT_mno_strict_align) ||
153 A->getOption().matches(ID: options::OPT_mno_scalar_strict_align)) {
154 Features.push_back(x: "+unaligned-scalar-mem");
155 } else {
156 Features.push_back(x: "-unaligned-scalar-mem");
157 }
158 } else if (CPUFastScalarUnaligned || Triple.isAndroid()) {
159 Features.push_back(x: "+unaligned-scalar-mem");
160 }
161
162 // If -mstrict-align, -mno-strict-align, -mvector-strict-align, or
163 // -mno-vector-strict-align is passed, use it. Otherwise, the
164 // unaligned-vector-mem is enabled if the CPU supports it or the target is
165 // Android.
166 if (const Arg *A = Args.getLastArg(
167 Ids: options::OPT_mno_strict_align, Ids: options::OPT_mvector_strict_align,
168 Ids: options::OPT_mstrict_align, Ids: options::OPT_mno_vector_strict_align)) {
169 if (A->getOption().matches(ID: options::OPT_mno_strict_align) ||
170 A->getOption().matches(ID: options::OPT_mno_vector_strict_align)) {
171 Features.push_back(x: "+unaligned-vector-mem");
172 } else {
173 Features.push_back(x: "-unaligned-vector-mem");
174 }
175 } else if (CPUFastVectorUnaligned || Triple.isAndroid()) {
176 Features.push_back(x: "+unaligned-vector-mem");
177 }
178
179 // Now add any that the user explicitly requested on the command line,
180 // which may override the defaults.
181 handleTargetFeaturesGroup(D, Triple, Args, Features,
182 Group: options::OPT_m_riscv_Features_Group);
183}
184
185StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
186 assert(Triple.isRISCV() && "Unexpected triple");
187
188 // GCC's logic around choosing a default `-mabi=` is complex. If GCC is not
189 // configured using `--with-abi=`, then the logic for the default choice is
190 // defined in config.gcc. This function is based on the logic in GCC 9.2.0.
191 //
192 // The logic used in GCC 9.2.0 is the following, in order:
193 // 1. Explicit choices using `--with-abi=`
194 // 2. A default based on `--with-arch=`, if provided
195 // 3. A default based on the target triple's arch
196 //
197 // The logic in config.gcc is a little circular but it is not inconsistent.
198 //
199 // Clang does not have `--with-arch=` or `--with-abi=`, so we use `-march=`
200 // and `-mabi=` respectively instead.
201 //
202 // In order to make chosing logic more clear, Clang uses the following logic,
203 // in order:
204 // 1. Explicit choices using `-mabi=`
205 // 2. A default based on the architecture as determined by getRISCVArch
206 // 3. Choose a default based on the triple
207
208 // 1. If `-mabi=` is specified, use it.
209 if (const Arg *A = Args.getLastArg(Ids: options::OPT_mabi_EQ))
210 return A->getValue();
211
212 // 2. Choose a default based on the target architecture.
213 //
214 // rv32g | rv32*d -> ilp32d
215 // rv32e -> ilp32e
216 // rv32* -> ilp32
217 // rv64g | rv64*d -> lp64d
218 // rv64e -> lp64e
219 // rv64* -> lp64
220 std::string Arch = getRISCVArch(Args, Triple);
221
222 auto ParseResult = llvm::RISCVISAInfo::parseArchString(
223 Arch, /* EnableExperimentalExtension */ true);
224 // Ignore parsing error, just go 3rd step.
225 if (!llvm::errorToBool(Err: ParseResult.takeError()))
226 return (*ParseResult)->computeDefaultABI();
227
228 // 3. Choose a default based on the triple
229 //
230 // We deviate from GCC's defaults here:
231 // - On `riscv{XLEN}-unknown-elf` we use the integer calling convention only.
232 // - On all other OSs we use the double floating point calling convention.
233 if (Triple.isRISCV32()) {
234 if (Triple.getOS() == llvm::Triple::UnknownOS)
235 return "ilp32";
236 else
237 return "ilp32d";
238 } else {
239 if (Triple.getOS() == llvm::Triple::UnknownOS)
240 return "lp64";
241 else
242 return "lp64d";
243 }
244}
245
246std::string riscv::getRISCVArch(const llvm::opt::ArgList &Args,
247 const llvm::Triple &Triple) {
248 assert(Triple.isRISCV() && "Unexpected triple");
249
250 // GCC's logic around choosing a default `-march=` is complex. If GCC is not
251 // configured using `--with-arch=`, then the logic for the default choice is
252 // defined in config.gcc. This function is based on the logic in GCC 9.2.0. We
253 // deviate from GCC's default on additional `-mcpu` option (GCC does not
254 // support `-mcpu`) and baremetal targets (UnknownOS) where neither `-march`
255 // nor `-mabi` is specified.
256 //
257 // The logic used in GCC 9.2.0 is the following, in order:
258 // 1. Explicit choices using `--with-arch=`
259 // 2. A default based on `--with-abi=`, if provided
260 // 3. A default based on the target triple's arch
261 //
262 // The logic in config.gcc is a little circular but it is not inconsistent.
263 //
264 // Clang does not have `--with-arch=` or `--with-abi=`, so we use `-march=`
265 // and `-mabi=` respectively instead.
266 //
267 // Clang uses the following logic, in order:
268 // 1. Explicit choices using `-march=`
269 // 2. Based on `-mcpu` if the target CPU has a default ISA string
270 // 3. A default based on `-mabi`, if provided
271 // 4. A default based on the target triple's arch
272 //
273 // Clang does not yet support MULTILIB_REUSE, so we use `rv{XLEN}imafdc`
274 // instead of `rv{XLEN}gc` though they are (currently) equivalent.
275
276 // 1. If `-march=` is specified, use it.
277 if (const Arg *A = Args.getLastArg(Ids: options::OPT_march_EQ))
278 return A->getValue();
279
280 // 2. Get march (isa string) based on `-mcpu=`
281 if (const Arg *A = Args.getLastArg(Ids: options::OPT_mcpu_EQ)) {
282 StringRef CPU = A->getValue();
283 if (CPU == "native") {
284 CPU = llvm::sys::getHostCPUName();
285 // If the target cpu is unrecognized, use target features.
286 if (CPU.starts_with(Prefix: "generic")) {
287 auto FeatureMap = llvm::sys::getHostCPUFeatures();
288 // hwprobe may be unavailable on older Linux versions.
289 if (!FeatureMap.empty()) {
290 std::vector<std::string> Features;
291 for (auto &F : FeatureMap)
292 Features.push_back(x: ((F.second ? "+" : "-") + F.first()).str());
293 auto ParseResult = llvm::RISCVISAInfo::parseFeatures(
294 XLen: Triple.isRISCV32() ? 32 : 64, Features);
295 if (ParseResult)
296 return (*ParseResult)->toString();
297 }
298 }
299 }
300
301 StringRef MArch = llvm::RISCV::getMArchFromMcpu(CPU);
302 // Bypass if target cpu's default march is empty.
303 if (MArch != "")
304 return MArch.str();
305 }
306
307 // 3. Choose a default based on `-mabi=`
308 //
309 // ilp32e -> rv32e
310 // lp64e -> rv64e
311 // ilp32 | ilp32f | ilp32d -> rv32imafdc
312 // lp64 | lp64f | lp64d -> rv64imafdc
313 if (const Arg *A = Args.getLastArg(Ids: options::OPT_mabi_EQ)) {
314 StringRef MABI = A->getValue();
315
316 if (MABI.equals_insensitive(RHS: "ilp32e"))
317 return "rv32e";
318 if (MABI.equals_insensitive(RHS: "lp64e"))
319 return "rv64e";
320 if (MABI.starts_with_insensitive(Prefix: "ilp32"))
321 return "rv32imafdc";
322 if (MABI.starts_with_insensitive(Prefix: "lp64")) {
323 if (Triple.isAndroid())
324 return "rv64imafdcv_zba_zbb_zbs";
325 if (Triple.isOSFuchsia())
326 return "rva22u64_v";
327 return "rv64imafdc";
328 }
329 }
330
331 // 4. Choose a default based on the triple
332 //
333 // We deviate from GCC's defaults here:
334 // - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
335 // - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
336 if (Triple.isRISCV32()) {
337 if (Triple.getOS() == llvm::Triple::UnknownOS)
338 return "rv32imac";
339 return "rv32imafdc";
340 }
341
342 if (Triple.getOS() == llvm::Triple::UnknownOS)
343 return "rv64imac";
344 if (Triple.isAndroid())
345 return "rv64imafdcv_zba_zbb_zbs";
346 if (Triple.isOSFuchsia())
347 return "rva22u64_v";
348 return "rv64imafdc";
349}
350
351std::string riscv::getRISCVTargetCPU(const llvm::opt::ArgList &Args,
352 const llvm::Triple &Triple) {
353 std::string CPU;
354 // If we have -mcpu, use that.
355 if (const Arg *A = Args.getLastArg(Ids: options::OPT_mcpu_EQ))
356 CPU = A->getValue();
357
358 // Handle CPU name is 'native'.
359 if (CPU == "native")
360 CPU = llvm::sys::getHostCPUName();
361
362 if (!CPU.empty())
363 return CPU;
364
365 return Triple.isRISCV64() ? "generic-rv64" : "generic-rv32";
366}
367