1//===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file simulates the hardware responsible for retiring instructions.
11///
12//===----------------------------------------------------------------------===//
13
14#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
15#include "llvm/Support/Debug.h"
16
17#define DEBUG_TYPE "llvm-mca"
18
19namespace llvm {
20namespace mca {
21
22RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)
23 : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
24 AvailableEntries(SM.isOutOfOrder() ? SM.MicroOpBufferSize : 0),
25 MaxRetirePerCycle(0) {
26 assert(SM.isOutOfOrder() &&
27 "RetireControlUnit is not available for in-order processors");
28 // Check if the scheduling model provides extra information about the machine
29 // processor. If so, then use that information to set the reorder buffer size
30 // and the maximum number of instructions retired per cycle.
31 if (SM.hasExtraProcessorInfo()) {
32 const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
33 if (EPI.ReorderBufferSize)
34 AvailableEntries = EPI.ReorderBufferSize;
35 MaxRetirePerCycle = EPI.MaxRetirePerCycle;
36 }
37 NumROBEntries = AvailableEntries;
38 assert(NumROBEntries && "Invalid reorder buffer size!");
39 Queue.resize(new_size: 2 * NumROBEntries);
40}
41
42// Reserves a number of slots, and returns a new token.
43unsigned RetireControlUnit::dispatch(const InstRef &IR) {
44 const Instruction &Inst = *IR.getInstruction();
45 unsigned Entries = normalizeQuantity(Quantity: Inst.getNumMicroOps());
46 assert((AvailableEntries >= Entries) && "Reorder Buffer unavailable!");
47
48 unsigned TokenID = NextAvailableSlotIdx;
49 Queue[NextAvailableSlotIdx] = {.IR: IR, .NumSlots: Entries, .Executed: false};
50 NextAvailableSlotIdx += std::max(a: 1U, b: Entries);
51 NextAvailableSlotIdx %= Queue.size();
52 assert(TokenID < UnhandledTokenID && "Invalid token ID");
53
54 AvailableEntries -= Entries;
55 return TokenID;
56}
57
58const RetireControlUnit::RUToken &RetireControlUnit::getCurrentToken() const {
59 const RetireControlUnit::RUToken &Current = Queue[CurrentInstructionSlotIdx];
60#ifndef NDEBUG
61 const Instruction *Inst = Current.IR.getInstruction();
62 assert(Inst && "Invalid RUToken in the RCU queue.");
63#endif
64 return Current;
65}
66
67unsigned RetireControlUnit::computeNextSlotIdx() const {
68 const RetireControlUnit::RUToken &Current = getCurrentToken();
69 unsigned NextSlotIdx = CurrentInstructionSlotIdx + std::max(a: 1U, b: Current.NumSlots);
70 return NextSlotIdx % Queue.size();
71}
72
73const RetireControlUnit::RUToken &RetireControlUnit::peekNextToken() const {
74 return Queue[computeNextSlotIdx()];
75}
76
77void RetireControlUnit::consumeCurrentToken() {
78 RetireControlUnit::RUToken &Current = Queue[CurrentInstructionSlotIdx];
79 Current.IR.getInstruction()->retire();
80
81 // Update the slot index to be the next item in the circular queue.
82 CurrentInstructionSlotIdx += std::max(a: 1U, b: Current.NumSlots);
83 CurrentInstructionSlotIdx %= Queue.size();
84 AvailableEntries += Current.NumSlots;
85 Current = { .IR: InstRef(), .NumSlots: 0U, .Executed: false };
86}
87
88void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
89 assert(Queue.size() > TokenID);
90 assert(Queue[TokenID].IR.getInstruction() && "Instruction was not dispatched!");
91 assert(Queue[TokenID].Executed == false && "Instruction already executed!");
92 Queue[TokenID].Executed = true;
93}
94
95#ifndef NDEBUG
96void RetireControlUnit::dump() const {
97 dbgs() << "Retire Unit: { Total ROB Entries =" << NumROBEntries
98 << ", Available ROB entries=" << AvailableEntries << " }\n";
99}
100#endif
101
102} // namespace mca
103} // namespace llvm
104