1//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12
13#include "llvm/CodeGen/MachinePassManager.h"
14#include "llvm/IR/PassManager.h"
15#include "llvm/Pass.h"
16#include "llvm/Support/AMDGPUAddrSpace.h"
17#include "llvm/Support/CodeGen.h"
18
19namespace llvm {
20
21class AMDGPUTargetMachine;
22class GCNTargetMachine;
23class TargetMachine;
24
25// GlobalISel passes
26void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
27FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
28void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
29FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
30FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
31void initializeAMDGPURegBankCombinerPass(PassRegistry &);
32FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
33FunctionPass *createAMDGPURegBankSelectPass();
34FunctionPass *createAMDGPURegBankLegalizePass();
35
36// SI Passes
37FunctionPass *createGCNDPPCombinePass();
38FunctionPass *createSIAnnotateControlFlowLegacyPass();
39FunctionPass *createSIFoldOperandsLegacyPass();
40FunctionPass *createSIPeepholeSDWALegacyPass();
41FunctionPass *createSILowerI1CopiesLegacyPass();
42FunctionPass *createSIShrinkInstructionsLegacyPass();
43FunctionPass *createSILoadStoreOptimizerLegacyPass();
44FunctionPass *createSIWholeQuadModeLegacyPass();
45FunctionPass *createSIFixControlFlowLiveIntervalsPass();
46FunctionPass *createSIOptimizeExecMaskingPreRAPass();
47FunctionPass *createSIOptimizeVGPRLiveRangeLegacyPass();
48FunctionPass *createSIFixSGPRCopiesLegacyPass();
49FunctionPass *createLowerWWMCopiesPass();
50FunctionPass *createSIMemoryLegalizerPass();
51FunctionPass *createSIInsertWaitcntsPass();
52FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
53FunctionPass *createSIFormMemoryClausesLegacyPass();
54
55FunctionPass *createSIPostRABundlerPass();
56FunctionPass *createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *);
57ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
58FunctionPass *createAMDGPUCodeGenPreparePass();
59FunctionPass *createAMDGPULateCodeGenPrepareLegacyPass();
60FunctionPass *createAMDGPUReserveWWMRegsPass();
61FunctionPass *createAMDGPURewriteOutArgumentsPass();
62ModulePass *
63createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
64ModulePass *createAMDGPULowerBufferFatPointersPass();
65FunctionPass *createSIModeRegisterPass();
66FunctionPass *createGCNPreRAOptimizationsLegacyPass();
67FunctionPass *createAMDGPUPreloadKernArgPrologLegacyPass();
68ModulePass *createAMDGPUPreloadKernelArgumentsLegacyPass(const TargetMachine *);
69
70struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
71 AMDGPUSimplifyLibCallsPass() {}
72 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
73};
74
75struct AMDGPUImageIntrinsicOptimizerPass
76 : PassInfoMixin<AMDGPUImageIntrinsicOptimizerPass> {
77 AMDGPUImageIntrinsicOptimizerPass(TargetMachine &TM) : TM(TM) {}
78 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
79
80private:
81 TargetMachine &TM;
82};
83
84struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
85 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
86};
87
88class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {
89public:
90 SILowerI1CopiesPass() = default;
91 PreservedAnalyses run(MachineFunction &MF,
92 MachineFunctionAnalysisManager &MFAM);
93};
94
95void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
96
97void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
98
99void initializeAMDGPUAsmPrinterPass(PassRegistry &);
100
101// DPP/Iterative option enables the atomic optimizer with given strategy
102// whereas None disables the atomic optimizer.
103enum class ScanOptions { DPP, Iterative, None };
104FunctionPass *createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy);
105void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
106extern char &AMDGPUAtomicOptimizerID;
107
108ModulePass *createAMDGPUCtorDtorLoweringLegacyPass();
109void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &);
110extern char &AMDGPUCtorDtorLoweringLegacyPassID;
111
112FunctionPass *createAMDGPULowerKernelArgumentsPass();
113void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
114extern char &AMDGPULowerKernelArgumentsID;
115
116FunctionPass *createAMDGPUPromoteKernelArgumentsPass();
117void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &);
118extern char &AMDGPUPromoteKernelArgumentsID;
119
120struct AMDGPUPromoteKernelArgumentsPass
121 : PassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
122 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
123};
124
125ModulePass *createAMDGPULowerKernelAttributesPass();
126void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
127extern char &AMDGPULowerKernelAttributesID;
128
129struct AMDGPULowerKernelAttributesPass
130 : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
131 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
132};
133
134void initializeAMDGPULowerModuleLDSLegacyPass(PassRegistry &);
135extern char &AMDGPULowerModuleLDSLegacyPassID;
136
137struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
138 const AMDGPUTargetMachine &TM;
139 AMDGPULowerModuleLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
140
141 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
142};
143
144void initializeAMDGPULowerBufferFatPointersPass(PassRegistry &);
145extern char &AMDGPULowerBufferFatPointersID;
146
147struct AMDGPULowerBufferFatPointersPass
148 : PassInfoMixin<AMDGPULowerBufferFatPointersPass> {
149 AMDGPULowerBufferFatPointersPass(const TargetMachine &TM) : TM(TM) {}
150 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
151
152private:
153 const TargetMachine &TM;
154};
155
156void initializeAMDGPUReserveWWMRegsLegacyPass(PassRegistry &);
157extern char &AMDGPUReserveWWMRegsLegacyID;
158
159void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
160extern char &AMDGPURewriteOutArgumentsID;
161
162void initializeGCNDPPCombineLegacyPass(PassRegistry &);
163extern char &GCNDPPCombineLegacyID;
164
165void initializeSIFoldOperandsLegacyPass(PassRegistry &);
166extern char &SIFoldOperandsLegacyID;
167
168void initializeSIPeepholeSDWALegacyPass(PassRegistry &);
169extern char &SIPeepholeSDWALegacyID;
170
171void initializeSIShrinkInstructionsLegacyPass(PassRegistry &);
172extern char &SIShrinkInstructionsLegacyID;
173
174void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &);
175extern char &SIFixSGPRCopiesLegacyID;
176
177void initializeSIFixVGPRCopiesLegacyPass(PassRegistry &);
178extern char &SIFixVGPRCopiesID;
179
180void initializeSILowerWWMCopiesLegacyPass(PassRegistry &);
181extern char &SILowerWWMCopiesLegacyID;
182
183void initializeSILowerI1CopiesLegacyPass(PassRegistry &);
184extern char &SILowerI1CopiesLegacyID;
185
186void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &);
187extern char &AMDGPUGlobalISelDivergenceLoweringID;
188
189void initializeAMDGPURegBankSelectPass(PassRegistry &);
190extern char &AMDGPURegBankSelectID;
191
192void initializeAMDGPURegBankLegalizePass(PassRegistry &);
193extern char &AMDGPURegBankLegalizeID;
194
195void initializeAMDGPUMarkLastScratchLoadLegacyPass(PassRegistry &);
196extern char &AMDGPUMarkLastScratchLoadID;
197
198void initializeSILowerSGPRSpillsLegacyPass(PassRegistry &);
199extern char &SILowerSGPRSpillsLegacyID;
200
201void initializeSILoadStoreOptimizerLegacyPass(PassRegistry &);
202extern char &SILoadStoreOptimizerLegacyID;
203
204void initializeSIWholeQuadModeLegacyPass(PassRegistry &);
205extern char &SIWholeQuadModeID;
206
207void initializeSILowerControlFlowLegacyPass(PassRegistry &);
208extern char &SILowerControlFlowLegacyID;
209
210void initializeSIPreEmitPeepholeLegacyPass(PassRegistry &);
211extern char &SIPreEmitPeepholeID;
212
213void initializeSILateBranchLoweringLegacyPass(PassRegistry &);
214extern char &SILateBranchLoweringPassID;
215
216void initializeSIOptimizeExecMaskingLegacyPass(PassRegistry &);
217extern char &SIOptimizeExecMaskingLegacyID;
218
219void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
220extern char &SIPreAllocateWWMRegsLegacyID;
221
222void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
223extern char &AMDGPUImageIntrinsicOptimizerID;
224
225void initializeAMDGPUPerfHintAnalysisLegacyPass(PassRegistry &);
226extern char &AMDGPUPerfHintAnalysisLegacyID;
227
228void initializeGCNRegPressurePrinterPass(PassRegistry &);
229extern char &GCNRegPressurePrinterID;
230
231void initializeAMDGPUPreloadKernArgPrologLegacyPass(PassRegistry &);
232extern char &AMDGPUPreloadKernArgPrologLegacyID;
233
234void initializeAMDGPUPreloadKernelArgumentsLegacyPass(PassRegistry &);
235extern char &AMDGPUPreloadKernelArgumentsLegacyID;
236
237// Passes common to R600 and SI
238FunctionPass *createAMDGPUPromoteAlloca();
239void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
240extern char &AMDGPUPromoteAllocaID;
241
242struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
243 AMDGPUPromoteAllocaPass(TargetMachine &TM) : TM(TM) {}
244 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
245
246private:
247 TargetMachine &TM;
248};
249
250struct AMDGPUPromoteAllocaToVectorPass
251 : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
252 AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM) : TM(TM) {}
253 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
254
255private:
256 TargetMachine &TM;
257};
258
259struct AMDGPUAtomicOptimizerPass : PassInfoMixin<AMDGPUAtomicOptimizerPass> {
260 AMDGPUAtomicOptimizerPass(TargetMachine &TM, ScanOptions ScanImpl)
261 : TM(TM), ScanImpl(ScanImpl) {}
262 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
263
264private:
265 TargetMachine &TM;
266 ScanOptions ScanImpl;
267};
268
269struct AMDGPUInsertDelayAluPass
270 : public PassInfoMixin<AMDGPUInsertDelayAluPass> {
271 PreservedAnalyses run(MachineFunction &F,
272 MachineFunctionAnalysisManager &MFAM);
273};
274
275Pass *createAMDGPUStructurizeCFGPass();
276FunctionPass *createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel);
277ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
278
279struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
280 AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
281 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
282
283private:
284 bool GlobalOpt;
285};
286
287void initializeAMDGPUSwLowerLDSLegacyPass(PassRegistry &);
288extern char &AMDGPUSwLowerLDSLegacyPassID;
289ModulePass *
290createAMDGPUSwLowerLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
291
292struct AMDGPUSwLowerLDSPass : PassInfoMixin<AMDGPUSwLowerLDSPass> {
293 const AMDGPUTargetMachine &TM;
294 AMDGPUSwLowerLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
295 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
296};
297
298class AMDGPUCodeGenPreparePass
299 : public PassInfoMixin<AMDGPUCodeGenPreparePass> {
300private:
301 TargetMachine &TM;
302
303public:
304 AMDGPUCodeGenPreparePass(TargetMachine &TM) : TM(TM){};
305 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
306};
307
308class AMDGPULateCodeGenPreparePass
309 : public PassInfoMixin<AMDGPULateCodeGenPreparePass> {
310private:
311 const GCNTargetMachine &TM;
312
313public:
314 AMDGPULateCodeGenPreparePass(const GCNTargetMachine &TM) : TM(TM) {};
315 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
316};
317
318class AMDGPULowerKernelArgumentsPass
319 : public PassInfoMixin<AMDGPULowerKernelArgumentsPass> {
320private:
321 TargetMachine &TM;
322
323public:
324 AMDGPULowerKernelArgumentsPass(TargetMachine &TM) : TM(TM){};
325 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
326};
327
328struct AMDGPUAttributorOptions {
329 bool IsClosedWorld = false;
330};
331
332class AMDGPUAttributorPass : public PassInfoMixin<AMDGPUAttributorPass> {
333private:
334 TargetMachine &TM;
335
336 AMDGPUAttributorOptions Options;
337
338 const ThinOrFullLTOPhase LTOPhase;
339
340public:
341 AMDGPUAttributorPass(TargetMachine &TM, AMDGPUAttributorOptions Options,
342 ThinOrFullLTOPhase LTOPhase = ThinOrFullLTOPhase::None)
343 : TM(TM), Options(Options), LTOPhase(LTOPhase) {};
344 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
345};
346
347class AMDGPUPreloadKernelArgumentsPass
348 : public PassInfoMixin<AMDGPUPreloadKernelArgumentsPass> {
349 const TargetMachine &TM;
350
351public:
352 explicit AMDGPUPreloadKernelArgumentsPass(const TargetMachine &TM) : TM(TM) {}
353
354 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
355};
356
357class AMDGPUAnnotateUniformValuesPass
358 : public PassInfoMixin<AMDGPUAnnotateUniformValuesPass> {
359public:
360 AMDGPUAnnotateUniformValuesPass() {}
361 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
362};
363
364class SIModeRegisterPass : public PassInfoMixin<SIModeRegisterPass> {
365public:
366 SIModeRegisterPass() {}
367 PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM);
368};
369
370class SIMemoryLegalizerPass : public PassInfoMixin<SIMemoryLegalizerPass> {
371public:
372 PreservedAnalyses run(MachineFunction &MF,
373 MachineFunctionAnalysisManager &MFAM);
374 static bool isRequired() { return true; }
375};
376
377class GCNCreateVOPDPass : public PassInfoMixin<GCNCreateVOPDPass> {
378public:
379 PreservedAnalyses run(MachineFunction &MF,
380 MachineFunctionAnalysisManager &AM);
381};
382
383class AMDGPUMarkLastScratchLoadPass
384 : public PassInfoMixin<AMDGPUMarkLastScratchLoadPass> {
385public:
386 PreservedAnalyses run(MachineFunction &MF,
387 MachineFunctionAnalysisManager &AM);
388};
389
390class SIInsertWaitcntsPass : public PassInfoMixin<SIInsertWaitcntsPass> {
391public:
392 PreservedAnalyses run(MachineFunction &MF,
393 MachineFunctionAnalysisManager &MFAM);
394 static bool isRequired() { return true; }
395};
396
397class SIInsertHardClausesPass : public PassInfoMixin<SIInsertHardClausesPass> {
398public:
399 PreservedAnalyses run(MachineFunction &MF,
400 MachineFunctionAnalysisManager &MFAM);
401};
402
403class SILateBranchLoweringPass
404 : public PassInfoMixin<SILateBranchLoweringPass> {
405public:
406 PreservedAnalyses run(MachineFunction &MF,
407 MachineFunctionAnalysisManager &MFAM);
408 static bool isRequired() { return true; }
409};
410
411class SIPreEmitPeepholePass : public PassInfoMixin<SIPreEmitPeepholePass> {
412public:
413 PreservedAnalyses run(MachineFunction &MF,
414 MachineFunctionAnalysisManager &MFAM);
415 static bool isRequired() { return true; }
416};
417
418class AMDGPUSetWavePriorityPass
419 : public PassInfoMixin<AMDGPUSetWavePriorityPass> {
420public:
421 PreservedAnalyses run(MachineFunction &MF,
422 MachineFunctionAnalysisManager &MFAM);
423};
424
425FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
426
427ModulePass *createAMDGPUPrintfRuntimeBinding();
428void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
429extern char &AMDGPUPrintfRuntimeBindingID;
430
431void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &);
432extern char &AMDGPUResourceUsageAnalysisID;
433
434struct AMDGPUPrintfRuntimeBindingPass
435 : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
436 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
437};
438
439struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
440 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
441};
442
443void initializeSIOptimizeExecMaskingPreRALegacyPass(PassRegistry &);
444extern char &SIOptimizeExecMaskingPreRAID;
445
446void initializeSIOptimizeVGPRLiveRangeLegacyPass(PassRegistry &);
447extern char &SIOptimizeVGPRLiveRangeLegacyID;
448
449void initializeAMDGPUAnnotateUniformValuesLegacyPass(PassRegistry &);
450extern char &AMDGPUAnnotateUniformValuesLegacyPassID;
451
452void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
453extern char &AMDGPUCodeGenPrepareID;
454
455void initializeAMDGPURemoveIncompatibleFunctionsLegacyPass(PassRegistry &);
456extern char &AMDGPURemoveIncompatibleFunctionsID;
457
458void initializeAMDGPULateCodeGenPrepareLegacyPass(PassRegistry &);
459extern char &AMDGPULateCodeGenPrepareLegacyID;
460
461FunctionPass *createAMDGPURewriteUndefForPHILegacyPass();
462void initializeAMDGPURewriteUndefForPHILegacyPass(PassRegistry &);
463extern char &AMDGPURewriteUndefForPHILegacyPassID;
464
465class AMDGPURewriteUndefForPHIPass
466 : public PassInfoMixin<AMDGPURewriteUndefForPHIPass> {
467public:
468 AMDGPURewriteUndefForPHIPass() = default;
469 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
470};
471
472class SIAnnotateControlFlowPass
473 : public PassInfoMixin<SIAnnotateControlFlowPass> {
474private:
475 const AMDGPUTargetMachine &TM;
476
477public:
478 SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
479 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
480};
481
482void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &);
483extern char &SIAnnotateControlFlowLegacyPassID;
484
485void initializeSIMemoryLegalizerLegacyPass(PassRegistry &);
486extern char &SIMemoryLegalizerID;
487
488void initializeSIModeRegisterLegacyPass(PassRegistry &);
489extern char &SIModeRegisterID;
490
491void initializeAMDGPUInsertDelayAluLegacyPass(PassRegistry &);
492extern char &AMDGPUInsertDelayAluID;
493
494void initializeSIInsertHardClausesLegacyPass(PassRegistry &);
495extern char &SIInsertHardClausesID;
496
497void initializeSIInsertWaitcntsLegacyPass(PassRegistry &);
498extern char &SIInsertWaitcntsID;
499
500void initializeSIFormMemoryClausesLegacyPass(PassRegistry &);
501extern char &SIFormMemoryClausesID;
502
503void initializeSIPostRABundlerLegacyPass(PassRegistry &);
504extern char &SIPostRABundlerLegacyID;
505
506void initializeGCNCreateVOPDLegacyPass(PassRegistry &);
507extern char &GCNCreateVOPDID;
508
509void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
510extern char &AMDGPUUnifyDivergentExitNodesID;
511
512ImmutablePass *createAMDGPUAAWrapperPass();
513void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
514ImmutablePass *createAMDGPUExternalAAWrapperPass();
515void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
516
517void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
518
519ModulePass *createAMDGPUExportKernelRuntimeHandlesLegacyPass();
520void initializeAMDGPUExportKernelRuntimeHandlesLegacyPass(PassRegistry &);
521extern char &AMDGPUExportKernelRuntimeHandlesLegacyID;
522
523void initializeGCNNSAReassignLegacyPass(PassRegistry &);
524extern char &GCNNSAReassignID;
525
526void initializeGCNPreRALongBranchRegLegacyPass(PassRegistry &);
527extern char &GCNPreRALongBranchRegID;
528
529void initializeGCNPreRAOptimizationsLegacyPass(PassRegistry &);
530extern char &GCNPreRAOptimizationsID;
531
532FunctionPass *createAMDGPUSetWavePriorityPass();
533void initializeAMDGPUSetWavePriorityLegacyPass(PassRegistry &);
534
535void initializeGCNRewritePartialRegUsesLegacyPass(llvm::PassRegistry &);
536extern char &GCNRewritePartialRegUsesID;
537
538void initializeAMDGPUWaitSGPRHazardsLegacyPass(PassRegistry &);
539extern char &AMDGPUWaitSGPRHazardsLegacyID;
540
541class AMDGPURewriteAGPRCopyMFMAPass
542 : public PassInfoMixin<AMDGPURewriteAGPRCopyMFMAPass> {
543public:
544 AMDGPURewriteAGPRCopyMFMAPass() = default;
545 PreservedAnalyses run(MachineFunction &MF,
546 MachineFunctionAnalysisManager &MFAM);
547};
548
549void initializeAMDGPURewriteAGPRCopyMFMALegacyPass(PassRegistry &);
550extern char &AMDGPURewriteAGPRCopyMFMALegacyID;
551
552namespace AMDGPU {
553enum TargetIndex {
554 TI_CONSTDATA_START,
555 TI_SCRATCH_RSRC_DWORD0,
556 TI_SCRATCH_RSRC_DWORD1,
557 TI_SCRATCH_RSRC_DWORD2,
558 TI_SCRATCH_RSRC_DWORD3
559};
560
561static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
562 if (AS1 > AMDGPUAS::MAX_AMDGPU_ADDRESS || AS2 > AMDGPUAS::MAX_AMDGPU_ADDRESS)
563 return true;
564
565 // clang-format off
566 static const bool ASAliasRules[][AMDGPUAS::MAX_AMDGPU_ADDRESS + 1] = {
567 /* Flat Global Region Local Constant Private Const32 BufFatPtr BufRsrc BufStrdPtr */
568 /* Flat */ {true, true, false, true, true, true, true, true, true, true},
569 /* Global */ {true, true, false, false, true, false, true, true, true, true},
570 /* Region */ {false, false, true, false, false, false, false, false, false, false},
571 /* Local */ {true, false, false, true, false, false, false, false, false, false},
572 /* Constant */ {true, true, false, false, false, false, true, true, true, true},
573 /* Private */ {true, false, false, false, false, true, false, false, false, false},
574 /* Constant 32-bit */ {true, true, false, false, true, false, false, true, true, true},
575 /* Buffer Fat Ptr */ {true, true, false, false, true, false, true, true, true, true},
576 /* Buffer Resource */ {true, true, false, false, true, false, true, true, true, true},
577 /* Buffer Strided Ptr */ {true, true, false, false, true, false, true, true, true, true},
578 };
579 // clang-format on
580 static_assert(std::size(ASAliasRules) == AMDGPUAS::MAX_AMDGPU_ADDRESS + 1);
581
582 return ASAliasRules[AS1][AS2];
583}
584
585}
586
587} // End namespace llvm
588
589#endif
590