1//===- R600TargetTransformInfo.h - R600 specific TTI --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file a TargetTransformInfoImplBase conforming object specific to the
11/// R600 target machine. It uses the target's detailed information to
12/// provide more precise answers to certain TTI queries, while letting the
13/// target independent and default TTI implementations handle the rest.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
18#define LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
19
20#include "AMDGPUTargetTransformInfo.h"
21#include "llvm/CodeGen/BasicTTIImpl.h"
22
23namespace llvm {
24
25class R600Subtarget;
26class AMDGPUTargetLowering;
27
28class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {
29 using BaseT = BasicTTIImplBase<R600TTIImpl>;
30 using TTI = TargetTransformInfo;
31
32 friend BaseT;
33
34 const R600Subtarget *ST;
35 const AMDGPUTargetLowering *TLI;
36 AMDGPUTTIImpl CommonTTI;
37
38public:
39 explicit R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
40
41 const R600Subtarget *getST() const { return ST; }
42 const AMDGPUTargetLowering *getTLI() const { return TLI; }
43
44 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
45 TTI::UnrollingPreferences &UP,
46 OptimizationRemarkEmitter *ORE) const override;
47 void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
48 TTI::PeelingPreferences &PP) const override;
49 unsigned getHardwareNumberOfRegisters(bool Vec) const;
50 unsigned getNumberOfRegisters(unsigned ClassID) const override;
51 TypeSize
52 getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const override;
53 unsigned getMinVectorRegisterBitWidth() const override;
54 unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override;
55 bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
56 unsigned AddrSpace) const;
57 bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
58 unsigned AddrSpace) const override;
59 bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
60 unsigned AddrSpace) const override;
61 unsigned getMaxInterleaveFactor(ElementCount VF) const override;
62 InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
63 const Instruction *I = nullptr) const override;
64 using BaseT::getVectorInstrCost;
65 InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
66 TTI::TargetCostKind CostKind,
67 unsigned Index, const Value *Op0,
68 const Value *Op1) const override;
69};
70
71} // end namespace llvm
72
73#endif // LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
74