1//===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
14#define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
15
16#include "ARMBaseInstrInfo.h"
17#include "ThumbRegisterInfo.h"
18
19namespace llvm {
20class ARMSubtarget;
21
22class Thumb2InstrInfo : public ARMBaseInstrInfo {
23 ThumbRegisterInfo RI;
24public:
25 explicit Thumb2InstrInfo(const ARMSubtarget &STI);
26
27 /// Return the noop instruction to use for a noop.
28 MCInst getNop() const override;
29
30 // Return the non-pre/post incrementing version of 'Opc'. Return 0
31 // if there is not such an opcode.
32 unsigned getUnindexedOpcode(unsigned Opc) const override;
33
34 void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
35 MachineBasicBlock *NewDest) const override;
36
37 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MBBI) const override;
39
40 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
41 const DebugLoc &DL, Register DestReg, Register SrcReg,
42 bool KillSrc, bool RenamableDest = false,
43 bool RenamableSrc = false) const override;
44
45 void storeRegToStackSlot(
46 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
47 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
48 const TargetRegisterInfo *TRI, Register VReg,
49 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
50
51 void loadRegFromStackSlot(
52 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
53 Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
54 const TargetRegisterInfo *TRI, Register VReg,
55 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
56
57 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
58 /// such, whenever a client has an instance of instruction info, it should
59 /// always be able to get register info as well (through this method).
60 ///
61 const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
62
63 MachineInstr *optimizeSelect(MachineInstr &MI,
64 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
65 bool) const override;
66
67 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
68 unsigned OpIdx1,
69 unsigned OpIdx2) const override;
70
71 bool isSchedulingBoundary(const MachineInstr &MI,
72 const MachineBasicBlock *MBB,
73 const MachineFunction &MF) const override;
74
75private:
76 void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
77};
78
79/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
80/// to llvm::getInstrPredicate except it returns AL for conditional branch
81/// instructions which are "predicated", but are not in IT blocks.
82ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
83
84// getVPTInstrPredicate: VPT analogue of that, plus a helper function
85// corresponding to MachineInstr::findFirstPredOperandIdx.
86int findFirstVPTPredOperandIdx(const MachineInstr &MI);
87ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI,
88 Register &PredReg);
89inline ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI) {
90 Register PredReg;
91 return getVPTInstrPredicate(MI, PredReg);
92}
93
94// Recomputes the Block Mask of Instr, a VPT or VPST instruction.
95// This rebuilds the block mask of the instruction depending on the predicates
96// of the instructions following it. This should only be used after the
97// MVEVPTBlockInsertion pass has run, and should be used whenever a predicated
98// instruction is added to/removed from the block.
99void recomputeVPTBlockMask(MachineInstr &Instr);
100} // namespace llvm
101
102#endif
103