1//===-- HexagonELFObjectWriter.cpp - Hexagon Target Descriptions ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/HexagonFixupKinds.h"
10#include "MCTargetDesc/HexagonMCExpr.h"
11#include "MCTargetDesc/HexagonMCTargetDesc.h"
12#include "llvm/MC/MCAssembler.h"
13#include "llvm/MC/MCELFObjectWriter.h"
14#include "llvm/MC/MCObjectWriter.h"
15#include "llvm/MC/MCValue.h"
16
17#define DEBUG_TYPE "hexagon-elf-writer"
18
19using namespace llvm;
20using namespace Hexagon;
21
22namespace {
23
24class HexagonELFObjectWriter : public MCELFObjectTargetWriter {
25private:
26 StringRef CPU;
27
28public:
29 HexagonELFObjectWriter(uint8_t OSABI, StringRef C);
30
31 unsigned getRelocType(const MCFixup &, const MCValue &,
32 bool IsPCRel) const override;
33};
34}
35
36HexagonELFObjectWriter::HexagonELFObjectWriter(uint8_t OSABI, StringRef C)
37 : MCELFObjectTargetWriter(/*Is64bit*/ false, OSABI, ELF::EM_HEXAGON,
38 /*HasRelocationAddend*/ true),
39 CPU(C) {}
40
41unsigned HexagonELFObjectWriter::getRelocType(const MCFixup &Fixup,
42 const MCValue &Target,
43 bool IsPCRel) const {
44 auto Variant = HexagonMCExpr::VariantKind(Target.getSpecifier());
45 switch (Variant) {
46 case HexagonMCExpr::VK_GD_GOT:
47 case HexagonMCExpr::VK_LD_GOT:
48 case HexagonMCExpr::VK_GD_PLT:
49 case HexagonMCExpr::VK_LD_PLT:
50 case HexagonMCExpr::VK_IE:
51 case HexagonMCExpr::VK_IE_GOT:
52 case HexagonMCExpr::VK_TPREL:
53 if (auto *SA = Target.getAddSym())
54 cast<MCSymbolELF>(Val: SA)->setType(ELF::STT_TLS);
55 break;
56 default:
57 break;
58 }
59 switch (Fixup.getTargetKind()) {
60 default:
61 report_fatal_error(reason: "Unrecognized relocation type");
62 break;
63 case FK_Data_4:
64 switch (Variant) {
65 case HexagonMCExpr::VK_DTPREL:
66 return ELF::R_HEX_DTPREL_32;
67 case HexagonMCExpr::VK_GOT:
68 return ELF::R_HEX_GOT_32;
69 case HexagonMCExpr::VK_GOTREL:
70 return ELF::R_HEX_GOTREL_32;
71 case HexagonMCExpr::VK_GD_GOT:
72 return ELF::R_HEX_GD_GOT_32;
73 case HexagonMCExpr::VK_IE:
74 return ELF::R_HEX_IE_32;
75 case HexagonMCExpr::VK_IE_GOT:
76 return ELF::R_HEX_IE_GOT_32;
77 case HexagonMCExpr::VK_LD_GOT:
78 return ELF::R_HEX_LD_GOT_32;
79 case HexagonMCExpr::VK_PCREL:
80 return ELF::R_HEX_32_PCREL;
81 case HexagonMCExpr::VK_TPREL:
82 return ELF::R_HEX_TPREL_32;
83 case HexagonMCExpr::VK_None:
84 return IsPCRel ? ELF::R_HEX_32_PCREL : ELF::R_HEX_32;
85 default:
86 report_fatal_error(reason: "Unrecognized variant type");
87 };
88 case FK_PCRel_4:
89 return ELF::R_HEX_32_PCREL;
90 case FK_Data_2:
91 switch(Variant) {
92 case HexagonMCExpr::VK_DTPREL:
93 return ELF::R_HEX_DTPREL_16;
94 case HexagonMCExpr::VK_GOT:
95 return ELF::R_HEX_GOT_16;
96 case HexagonMCExpr::VK_GD_GOT:
97 return ELF::R_HEX_GD_GOT_16;
98 case HexagonMCExpr::VK_IE_GOT:
99 return ELF::R_HEX_IE_GOT_16;
100 case HexagonMCExpr::VK_LD_GOT:
101 return ELF::R_HEX_LD_GOT_16;
102 case HexagonMCExpr::VK_TPREL:
103 return ELF::R_HEX_TPREL_16;
104 case HexagonMCExpr::VK_None:
105 return ELF::R_HEX_16;
106 default:
107 report_fatal_error(reason: "Unrecognized variant type");
108 };
109 case FK_Data_1:
110 return ELF::R_HEX_8;
111 case fixup_Hexagon_B22_PCREL:
112 return ELF::R_HEX_B22_PCREL;
113 case fixup_Hexagon_B15_PCREL:
114 return ELF::R_HEX_B15_PCREL;
115 case fixup_Hexagon_B7_PCREL:
116 return ELF::R_HEX_B7_PCREL;
117 case fixup_Hexagon_LO16:
118 return ELF::R_HEX_LO16;
119 case fixup_Hexagon_HI16:
120 return ELF::R_HEX_HI16;
121 case fixup_Hexagon_32:
122 return ELF::R_HEX_32;
123 case fixup_Hexagon_16:
124 return ELF::R_HEX_16;
125 case fixup_Hexagon_8:
126 return ELF::R_HEX_8;
127 case fixup_Hexagon_GPREL16_0:
128 return ELF::R_HEX_GPREL16_0;
129 case fixup_Hexagon_GPREL16_1:
130 return ELF::R_HEX_GPREL16_1;
131 case fixup_Hexagon_GPREL16_2:
132 return ELF::R_HEX_GPREL16_2;
133 case fixup_Hexagon_GPREL16_3:
134 return ELF::R_HEX_GPREL16_3;
135 case fixup_Hexagon_HL16:
136 return ELF::R_HEX_HL16;
137 case fixup_Hexagon_B13_PCREL:
138 return ELF::R_HEX_B13_PCREL;
139 case fixup_Hexagon_B9_PCREL:
140 return ELF::R_HEX_B9_PCREL;
141 case fixup_Hexagon_B32_PCREL_X:
142 return ELF::R_HEX_B32_PCREL_X;
143 case fixup_Hexagon_32_6_X:
144 return ELF::R_HEX_32_6_X;
145 case fixup_Hexagon_B22_PCREL_X:
146 return ELF::R_HEX_B22_PCREL_X;
147 case fixup_Hexagon_B15_PCREL_X:
148 return ELF::R_HEX_B15_PCREL_X;
149 case fixup_Hexagon_B13_PCREL_X:
150 return ELF::R_HEX_B13_PCREL_X;
151 case fixup_Hexagon_B9_PCREL_X:
152 return ELF::R_HEX_B9_PCREL_X;
153 case fixup_Hexagon_B7_PCREL_X:
154 return ELF::R_HEX_B7_PCREL_X;
155 case fixup_Hexagon_16_X:
156 return ELF::R_HEX_16_X;
157 case fixup_Hexagon_12_X:
158 return ELF::R_HEX_12_X;
159 case fixup_Hexagon_11_X:
160 return ELF::R_HEX_11_X;
161 case fixup_Hexagon_10_X:
162 return ELF::R_HEX_10_X;
163 case fixup_Hexagon_9_X:
164 return ELF::R_HEX_9_X;
165 case fixup_Hexagon_8_X:
166 return ELF::R_HEX_8_X;
167 case fixup_Hexagon_7_X:
168 return ELF::R_HEX_7_X;
169 case fixup_Hexagon_6_X:
170 return ELF::R_HEX_6_X;
171 case fixup_Hexagon_32_PCREL:
172 return ELF::R_HEX_32_PCREL;
173 case fixup_Hexagon_COPY:
174 return ELF::R_HEX_COPY;
175 case fixup_Hexagon_GLOB_DAT:
176 return ELF::R_HEX_GLOB_DAT;
177 case fixup_Hexagon_JMP_SLOT:
178 return ELF::R_HEX_JMP_SLOT;
179 case fixup_Hexagon_RELATIVE:
180 return ELF::R_HEX_RELATIVE;
181 case fixup_Hexagon_PLT_B22_PCREL:
182 return ELF::R_HEX_PLT_B22_PCREL;
183 case fixup_Hexagon_GOTREL_LO16:
184 return ELF::R_HEX_GOTREL_LO16;
185 case fixup_Hexagon_GOTREL_HI16:
186 return ELF::R_HEX_GOTREL_HI16;
187 case fixup_Hexagon_GOTREL_32:
188 return ELF::R_HEX_GOTREL_32;
189 case fixup_Hexagon_GOT_LO16:
190 return ELF::R_HEX_GOT_LO16;
191 case fixup_Hexagon_GOT_HI16:
192 return ELF::R_HEX_GOT_HI16;
193 case fixup_Hexagon_GOT_32:
194 return ELF::R_HEX_GOT_32;
195 case fixup_Hexagon_GOT_16:
196 return ELF::R_HEX_GOT_16;
197 case fixup_Hexagon_DTPMOD_32:
198 return ELF::R_HEX_DTPMOD_32;
199 case fixup_Hexagon_DTPREL_LO16:
200 return ELF::R_HEX_DTPREL_LO16;
201 case fixup_Hexagon_DTPREL_HI16:
202 return ELF::R_HEX_DTPREL_HI16;
203 case fixup_Hexagon_DTPREL_32:
204 return ELF::R_HEX_DTPREL_32;
205 case fixup_Hexagon_DTPREL_16:
206 return ELF::R_HEX_DTPREL_16;
207 case fixup_Hexagon_GD_PLT_B22_PCREL:
208 return ELF::R_HEX_GD_PLT_B22_PCREL;
209 case fixup_Hexagon_LD_PLT_B22_PCREL:
210 return ELF::R_HEX_LD_PLT_B22_PCREL;
211 case fixup_Hexagon_GD_GOT_LO16:
212 return ELF::R_HEX_GD_GOT_LO16;
213 case fixup_Hexagon_GD_GOT_HI16:
214 return ELF::R_HEX_GD_GOT_HI16;
215 case fixup_Hexagon_GD_GOT_32:
216 return ELF::R_HEX_GD_GOT_32;
217 case fixup_Hexagon_GD_GOT_16:
218 return ELF::R_HEX_GD_GOT_16;
219 case fixup_Hexagon_LD_GOT_LO16:
220 return ELF::R_HEX_LD_GOT_LO16;
221 case fixup_Hexagon_LD_GOT_HI16:
222 return ELF::R_HEX_LD_GOT_HI16;
223 case fixup_Hexagon_LD_GOT_32:
224 return ELF::R_HEX_LD_GOT_32;
225 case fixup_Hexagon_LD_GOT_16:
226 return ELF::R_HEX_LD_GOT_16;
227 case fixup_Hexagon_IE_LO16:
228 return ELF::R_HEX_IE_LO16;
229 case fixup_Hexagon_IE_HI16:
230 return ELF::R_HEX_IE_HI16;
231 case fixup_Hexagon_IE_32:
232 return ELF::R_HEX_IE_32;
233 case fixup_Hexagon_IE_GOT_LO16:
234 return ELF::R_HEX_IE_GOT_LO16;
235 case fixup_Hexagon_IE_GOT_HI16:
236 return ELF::R_HEX_IE_GOT_HI16;
237 case fixup_Hexagon_IE_GOT_32:
238 return ELF::R_HEX_IE_GOT_32;
239 case fixup_Hexagon_IE_GOT_16:
240 return ELF::R_HEX_IE_GOT_16;
241 case fixup_Hexagon_TPREL_LO16:
242 return ELF::R_HEX_TPREL_LO16;
243 case fixup_Hexagon_TPREL_HI16:
244 return ELF::R_HEX_TPREL_HI16;
245 case fixup_Hexagon_TPREL_32:
246 return ELF::R_HEX_TPREL_32;
247 case fixup_Hexagon_TPREL_16:
248 return ELF::R_HEX_TPREL_16;
249 case fixup_Hexagon_6_PCREL_X:
250 return ELF::R_HEX_6_PCREL_X;
251 case fixup_Hexagon_GOTREL_32_6_X:
252 return ELF::R_HEX_GOTREL_32_6_X;
253 case fixup_Hexagon_GOTREL_16_X:
254 return ELF::R_HEX_GOTREL_16_X;
255 case fixup_Hexagon_GOTREL_11_X:
256 return ELF::R_HEX_GOTREL_11_X;
257 case fixup_Hexagon_GOT_32_6_X:
258 return ELF::R_HEX_GOT_32_6_X;
259 case fixup_Hexagon_GOT_16_X:
260 return ELF::R_HEX_GOT_16_X;
261 case fixup_Hexagon_GOT_11_X:
262 return ELF::R_HEX_GOT_11_X;
263 case fixup_Hexagon_DTPREL_32_6_X:
264 return ELF::R_HEX_DTPREL_32_6_X;
265 case fixup_Hexagon_DTPREL_16_X:
266 return ELF::R_HEX_DTPREL_16_X;
267 case fixup_Hexagon_DTPREL_11_X:
268 return ELF::R_HEX_DTPREL_11_X;
269 case fixup_Hexagon_GD_GOT_32_6_X:
270 return ELF::R_HEX_GD_GOT_32_6_X;
271 case fixup_Hexagon_GD_GOT_16_X:
272 return ELF::R_HEX_GD_GOT_16_X;
273 case fixup_Hexagon_GD_GOT_11_X:
274 return ELF::R_HEX_GD_GOT_11_X;
275 case fixup_Hexagon_LD_GOT_32_6_X:
276 return ELF::R_HEX_LD_GOT_32_6_X;
277 case fixup_Hexagon_LD_GOT_16_X:
278 return ELF::R_HEX_LD_GOT_16_X;
279 case fixup_Hexagon_LD_GOT_11_X:
280 return ELF::R_HEX_LD_GOT_11_X;
281 case fixup_Hexagon_IE_32_6_X:
282 return ELF::R_HEX_IE_32_6_X;
283 case fixup_Hexagon_IE_16_X:
284 return ELF::R_HEX_IE_16_X;
285 case fixup_Hexagon_IE_GOT_32_6_X:
286 return ELF::R_HEX_IE_GOT_32_6_X;
287 case fixup_Hexagon_IE_GOT_16_X:
288 return ELF::R_HEX_IE_GOT_16_X;
289 case fixup_Hexagon_IE_GOT_11_X:
290 return ELF::R_HEX_IE_GOT_11_X;
291 case fixup_Hexagon_TPREL_32_6_X:
292 return ELF::R_HEX_TPREL_32_6_X;
293 case fixup_Hexagon_TPREL_16_X:
294 return ELF::R_HEX_TPREL_16_X;
295 case fixup_Hexagon_TPREL_11_X:
296 return ELF::R_HEX_TPREL_11_X;
297 case fixup_Hexagon_23_REG:
298 return ELF::R_HEX_23_REG;
299 case fixup_Hexagon_27_REG:
300 return ELF::R_HEX_27_REG;
301 case fixup_Hexagon_GD_PLT_B22_PCREL_X:
302 return ELF::R_HEX_GD_PLT_B22_PCREL_X;
303 case fixup_Hexagon_GD_PLT_B32_PCREL_X:
304 return ELF::R_HEX_GD_PLT_B32_PCREL_X;
305 case fixup_Hexagon_LD_PLT_B22_PCREL_X:
306 return ELF::R_HEX_LD_PLT_B22_PCREL_X;
307 case fixup_Hexagon_LD_PLT_B32_PCREL_X:
308 return ELF::R_HEX_LD_PLT_B32_PCREL_X;
309 }
310}
311
312std::unique_ptr<MCObjectTargetWriter>
313llvm::createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU) {
314 return std::make_unique<HexagonELFObjectWriter>(args&: OSABI, args&: CPU);
315}
316