1//===- Mips16InstrInfo.h - Mips16 Instruction Information -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips16 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
14#define LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
15
16#include "Mips16RegisterInfo.h"
17#include "MipsInstrInfo.h"
18#include "llvm/CodeGen/MachineBasicBlock.h"
19#include "llvm/Support/MathExtras.h"
20#include <cstdint>
21
22namespace llvm {
23
24class MCInstrDesc;
25class MipsSubtarget;
26
27class Mips16InstrInfo : public MipsInstrInfo {
28 const Mips16RegisterInfo RI;
29
30public:
31 explicit Mips16InstrInfo(const MipsSubtarget &STI);
32
33 const MipsRegisterInfo &getRegisterInfo() const override;
34
35 /// isLoadFromStackSlot - If the specified machine instruction is a direct
36 /// load from a stack slot, return the virtual or physical register number of
37 /// the destination along with the FrameIndex of the loaded stack slot. If
38 /// not, return 0. This predicate must return 0 if the instruction has
39 /// any side effects other than loading from the stack slot.
40 Register isLoadFromStackSlot(const MachineInstr &MI,
41 int &FrameIndex) const override;
42
43 /// isStoreToStackSlot - If the specified machine instruction is a direct
44 /// store to a stack slot, return the virtual or physical register number of
45 /// the source reg along with the FrameIndex of the loaded stack slot. If
46 /// not, return 0. This predicate must return 0 if the instruction has
47 /// any side effects other than storing to the stack slot.
48 Register isStoreToStackSlot(const MachineInstr &MI,
49 int &FrameIndex) const override;
50
51 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
52 const DebugLoc &DL, Register DestReg, Register SrcReg,
53 bool KillSrc, bool RenamableDest = false,
54 bool RenamableSrc = false) const override;
55
56 void storeRegToStack(
57 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
58 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
59 const TargetRegisterInfo *TRI, int64_t Offset,
60 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
61
62 void loadRegFromStack(
63 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
64 Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
65 const TargetRegisterInfo *TRI, int64_t Offset,
66 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
67
68 bool expandPostRAPseudo(MachineInstr &MI) const override;
69
70 unsigned getOppositeBranchOpc(unsigned Opc) const override;
71
72 // Adjust SP by FrameSize bytes. Save RA, S0, S1
73 void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator I) const;
75
76 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
77 void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator I) const;
79
80 /// Adjust SP by Amount bytes.
81 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator I) const override;
83
84 /// Emit a series of instructions to load an immediate.
85 // This is to adjust some FrameReg. We return the new register to be used
86 // in place of FrameReg and the adjusted immediate field (&NewImm)
87 unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator II, const DebugLoc &DL,
89 unsigned &NewImm) const;
90
91 static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
92
93 static bool validSpImm8(int offset) {
94 return ((offset & 7) == 0) && isInt<11>(x: offset);
95 }
96
97 // build the proper one based on the Imm field
98
99 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
100
101 void BuildAddiuSpImm
102 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
103
104protected:
105 /// If the specific machine instruction is a instruction that moves/copies
106 /// value from one register to another register return destination and source
107 /// registers as machine operands.
108 std::optional<DestSourcePair>
109 isCopyInstrImpl(const MachineInstr &MI) const override;
110
111private:
112 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
113
114 void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
115 unsigned Opc) const;
116
117 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
118 void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
119 MachineBasicBlock::iterator I,
120 unsigned Reg1, unsigned Reg2) const;
121
122 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
123 void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
124 MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator I) const;
126};
127
128} // end namespace llvm
129
130#endif // LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
131