1//===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
15
16#include "MipsInstrInfo.h"
17#include "MipsSERegisterInfo.h"
18
19namespace llvm {
20
21class MipsSEInstrInfo : public MipsInstrInfo {
22 const MipsSERegisterInfo RI;
23
24public:
25 explicit MipsSEInstrInfo(const MipsSubtarget &STI);
26
27 const MipsRegisterInfo &getRegisterInfo() const override;
28
29 /// isLoadFromStackSlot - If the specified machine instruction is a direct
30 /// load from a stack slot, return the virtual or physical register number of
31 /// the destination along with the FrameIndex of the loaded stack slot. If
32 /// not, return 0. This predicate must return 0 if the instruction has
33 /// any side effects other than loading from the stack slot.
34 Register isLoadFromStackSlot(const MachineInstr &MI,
35 int &FrameIndex) const override;
36
37 /// isStoreToStackSlot - If the specified machine instruction is a direct
38 /// store to a stack slot, return the virtual or physical register number of
39 /// the source reg along with the FrameIndex of the loaded stack slot. If
40 /// not, return 0. This predicate must return 0 if the instruction has
41 /// any side effects other than storing to the stack slot.
42 Register isStoreToStackSlot(const MachineInstr &MI,
43 int &FrameIndex) const override;
44
45 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
46 const DebugLoc &DL, Register DestReg, Register SrcReg,
47 bool KillSrc, bool RenamableDest = false,
48 bool RenamableSrc = false) const override;
49
50 void storeRegToStack(
51 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
52 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
53 const TargetRegisterInfo *TRI, int64_t Offset,
54 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
55
56 void loadRegFromStack(
57 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
58 int FrameIndex, const TargetRegisterClass *RC,
59 const TargetRegisterInfo *TRI, int64_t Offset,
60 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
61
62 bool expandPostRAPseudo(MachineInstr &MI) const override;
63
64 bool isBranchWithImm(unsigned Opc) const override;
65
66 unsigned getOppositeBranchOpc(unsigned Opc) const override;
67
68 /// Adjust SP by Amount bytes.
69 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator I) const override;
71
72 /// Emit a series of instructions to load an immediate. If NewImm is a
73 /// non-NULL parameter, the last instruction is not emitted, but instead
74 /// its immediate operand is returned in NewImm.
75 unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
76 MachineBasicBlock::iterator II, const DebugLoc &DL,
77 unsigned *NewImm) const;
78
79protected:
80 /// If the specific machine instruction is a instruction that moves/copies
81 /// value from one register to another register return destination and source
82 /// registers as machine operands.
83 std::optional<DestSourcePair>
84 isCopyInstrImpl(const MachineInstr &MI) const override;
85
86private:
87 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
88
89 void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
90
91 void expandERet(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
92
93 std::pair<bool, bool> compareOpndSize(unsigned Opc,
94 const MachineFunction &MF) const;
95
96 void expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
97 unsigned NewOpc) const;
98
99 void expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
100 unsigned LoOpc, unsigned HiOpc,
101 bool HasExplicitDef) const;
102
103 /// Expand pseudo Int-to-FP conversion instructions.
104 ///
105 /// For example, the following pseudo instruction
106 /// PseudoCVT_D32_W D2, A5
107 /// gets expanded into these two instructions:
108 /// MTC1 F4, A5
109 /// CVT_D32_W D2, F4
110 ///
111 /// We do this expansion post-RA to avoid inserting a floating point copy
112 /// instruction between MTC1 and CVT_D32_W.
113 void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
114 unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
115
116 void expandExtractElementF64(MachineBasicBlock &MBB,
117 MachineBasicBlock::iterator I, bool isMicroMips,
118 bool FP64) const;
119 void expandBuildPairF64(MachineBasicBlock &MBB,
120 MachineBasicBlock::iterator I, bool isMicroMips,
121 bool FP64) const;
122 void expandEhReturn(MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator I) const;
124};
125
126}
127
128#endif
129