1//===- PPCLegalizerInfo.h ----------------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the Machinelegalizer class for PowerPC
10//===----------------------------------------------------------------------===//
11
12#include "PPCLegalizerInfo.h"
13
14#define DEBUG_TYPE "ppc-legalinfo"
15
16using namespace llvm;
17using namespace LegalizeActions;
18using namespace LegalizeMutations;
19using namespace LegalityPredicates;
20
21static LegalityPredicate isRegisterType(unsigned TypeIdx) {
22 return [=](const LegalityQuery &Query) {
23 const LLT QueryTy = Query.Types[TypeIdx];
24 unsigned TypeSize = QueryTy.getSizeInBits();
25
26 if (TypeSize % 32 == 1 || TypeSize > 128)
27 return false;
28
29 // Check if this is a legal PowerPC vector type.
30 if (QueryTy.isVector()) {
31 const int EltSize = QueryTy.getElementType().getSizeInBits();
32 return (EltSize == 8 || EltSize == 16 || EltSize == 32 || EltSize == 64);
33 }
34
35 return true;
36 };
37}
38
39PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
40 using namespace TargetOpcode;
41 const LLT P0 = LLT::pointer(AddressSpace: 0, SizeInBits: 64);
42 const LLT S1 = LLT::scalar(SizeInBits: 1);
43 const LLT S8 = LLT::scalar(SizeInBits: 8);
44 const LLT S16 = LLT::scalar(SizeInBits: 16);
45 const LLT S32 = LLT::scalar(SizeInBits: 32);
46 const LLT S64 = LLT::scalar(SizeInBits: 64);
47 const LLT V16S8 = LLT::fixed_vector(NumElements: 16, ScalarSizeInBits: 8);
48 const LLT V8S16 = LLT::fixed_vector(NumElements: 8, ScalarSizeInBits: 16);
49 const LLT V4S32 = LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 32);
50 const LLT V2S64 = LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 64);
51 getActionDefinitionsBuilder(Opcode: G_IMPLICIT_DEF).legalFor(Types: {S64});
52 getActionDefinitionsBuilder(Opcode: G_CONSTANT)
53 .legalFor(Types: {S32, S64})
54 .clampScalar(TypeIdx: 0, MinTy: S64, MaxTy: S64);
55 getActionDefinitionsBuilder(Opcodes: {G_ZEXT, G_SEXT, G_ANYEXT})
56 .legalForCartesianProduct(Types0: {S64}, Types1: {S1, S8, S16, S32})
57 .clampScalar(TypeIdx: 0, MinTy: S64, MaxTy: S64);
58 getActionDefinitionsBuilder(Opcodes: {G_AND, G_OR, G_XOR})
59 .legalFor(Types: {S64, V4S32})
60 .clampScalar(TypeIdx: 0, MinTy: S64, MaxTy: S64)
61 .bitcastIf(Predicate: typeIsNot(TypeIdx: 0, Type: V4S32), Mutation: changeTo(TypeIdx: 0, Ty: V4S32));
62 getActionDefinitionsBuilder(Opcodes: {G_ADD, G_SUB})
63 .legalFor(Types: {S64, V16S8, V8S16, V4S32, V2S64})
64 .clampScalar(TypeIdx: 0, MinTy: S64, MaxTy: S64);
65 getActionDefinitionsBuilder(Opcode: G_BITCAST)
66 .legalIf(Predicate: all(P0: isRegisterType(TypeIdx: 0), P1: isRegisterType(TypeIdx: 1)))
67 .lower();
68
69 getActionDefinitionsBuilder(Opcodes: {G_FADD, G_FSUB, G_FMUL, G_FDIV})
70 .legalFor(Types: {S32, S64, V4S32, V2S64});
71
72 getActionDefinitionsBuilder(Opcode: G_FCMP).legalForCartesianProduct(Types0: {S1},
73 Types1: {S32, S64});
74
75 getActionDefinitionsBuilder(Opcodes: {G_FPTOSI, G_FPTOUI})
76 .legalForCartesianProduct(Types0: {S64}, Types1: {S32, S64});
77
78 getActionDefinitionsBuilder(Opcodes: {G_SITOFP, G_UITOFP})
79 .legalForCartesianProduct(Types0: {S32, S64}, Types1: {S64});
80
81 getActionDefinitionsBuilder(Opcodes: {G_LOAD, G_STORE})
82 .legalForTypesWithMemDesc(TypesAndMemDesc: {{.Type0: S64, .Type1: P0, .MemTy: S64, .Align: 8}, {.Type0: S32, .Type1: P0, .MemTy: S32, .Align: 4}});
83
84 getActionDefinitionsBuilder(Opcode: G_FCONSTANT).lowerFor(Types: {S32, S64});
85 getActionDefinitionsBuilder(Opcode: G_CONSTANT_POOL).legalFor(Types: {P0});
86
87 getLegacyLegalizerInfo().computeTables();
88}
89