1//===-- RISCVFixupKinds.h - RISC-V Specific Fixup Entries -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H
10#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H
11
12#include "llvm/BinaryFormat/ELF.h"
13#include "llvm/MC/MCFixup.h"
14#include <utility>
15
16#undef RISCV
17
18namespace llvm::RISCV {
19enum Fixups {
20 // 20-bit fixup corresponding to %hi(foo) for instructions like lui
21 fixup_riscv_hi20 = FirstTargetFixupKind,
22 // 12-bit fixup corresponding to %lo(foo) for instructions like addi
23 fixup_riscv_lo12_i,
24 // 12-bit fixup corresponding to foo-bar for instructions like addi
25 fixup_riscv_12_i,
26 // 12-bit fixup corresponding to %lo(foo) for the S-type store instructions
27 fixup_riscv_lo12_s,
28 // 20-bit fixup corresponding to %pcrel_hi(foo) for instructions like auipc
29 fixup_riscv_pcrel_hi20,
30 // 12-bit fixup corresponding to %pcrel_lo(foo) for instructions like addi
31 fixup_riscv_pcrel_lo12_i,
32 // 12-bit fixup corresponding to %pcrel_lo(foo) for the S-type store
33 // instructions
34 fixup_riscv_pcrel_lo12_s,
35 // 20-bit fixup for symbol references in the jal instruction
36 fixup_riscv_jal,
37 // 12-bit fixup for symbol references in the branch instructions
38 fixup_riscv_branch,
39 // 11-bit fixup for symbol references in the compressed jump instruction
40 fixup_riscv_rvc_jump,
41 // 8-bit fixup for symbol references in the compressed branch instruction
42 fixup_riscv_rvc_branch,
43 // Fixup representing a legacy no-pic function call attached to the auipc
44 // instruction in a pair composed of adjacent auipc+jalr instructions.
45 fixup_riscv_call,
46 // Fixup representing a function call attached to the auipc instruction in a
47 // pair composed of adjacent auipc+jalr instructions.
48 fixup_riscv_call_plt,
49 // 12-bit fixup for symbol references in the 48-bit Xqcibi branch immediate
50 // instructions
51 fixup_riscv_qc_e_branch,
52 // 32-bit fixup for symbol references in the 48-bit qc.e.li instruction
53 fixup_riscv_qc_e_32,
54 // 20-bit fixup for symbol references in the 32-bit qc.li instruction
55 fixup_riscv_qc_abs20_u,
56 // 32-bit fixup for symbol references in the 48-bit qc.j/qc.jal instructions
57 fixup_riscv_qc_e_call_plt,
58
59 // Andes specific fixups
60 // 10-bit fixup for symbol references in the xandesperf branch instruction
61 fixup_riscv_nds_branch_10,
62
63 // Used as a sentinel, must be the last
64 fixup_riscv_invalid,
65 NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind
66};
67
68static inline std::pair<MCFixupKind, MCFixupKind>
69getRelocPairForSize(unsigned Size) {
70 switch (Size) {
71 default:
72 llvm_unreachable("unsupported fixup size");
73 case 1:
74 return std::make_pair(
75 x: MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_ADD8),
76 y: MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_SUB8));
77 case 2:
78 return std::make_pair(
79 x: MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_ADD16),
80 y: MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_SUB16));
81 case 4:
82 return std::make_pair(
83 x: MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_ADD32),
84 y: MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_SUB32));
85 case 8:
86 return std::make_pair(
87 x: MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_ADD64),
88 y: MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_SUB64));
89 }
90}
91
92} // end namespace llvm::RISCV
93
94#endif
95