| 1 | //===-- Sparc.h - Top-level interface for Sparc representation --*- C++ -*-===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // |
| 9 | // This file contains the entry points for global functions defined in the LLVM |
| 10 | // Sparc back-end. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef LLVM_LIB_TARGET_SPARC_SPARC_H |
| 15 | #define LLVM_LIB_TARGET_SPARC_SPARC_H |
| 16 | |
| 17 | #include "MCTargetDesc/SparcMCTargetDesc.h" |
| 18 | #include "llvm/Support/ErrorHandling.h" |
| 19 | #include "llvm/Target/TargetMachine.h" |
| 20 | |
| 21 | namespace llvm { |
| 22 | class AsmPrinter; |
| 23 | class FunctionPass; |
| 24 | class MCInst; |
| 25 | class MachineInstr; |
| 26 | class PassRegistry; |
| 27 | class SparcTargetMachine; |
| 28 | |
| 29 | FunctionPass *createSparcISelDag(SparcTargetMachine &TM); |
| 30 | FunctionPass *createSparcDelaySlotFillerPass(); |
| 31 | |
| 32 | void initializeSparcAsmPrinterPass(PassRegistry &); |
| 33 | void initializeSparcDAGToDAGISelLegacyPass(PassRegistry &); |
| 34 | void initializeErrataWorkaroundPass(PassRegistry &); |
| 35 | } // namespace llvm |
| 36 | |
| 37 | namespace llvm { |
| 38 | // Enums corresponding to Sparc condition codes, both icc's and fcc's. These |
| 39 | // values must be kept in sync with the ones in the .td file. |
| 40 | namespace SPCC { |
| 41 | enum CondCodes { |
| 42 | ICC_A = 8, // Always |
| 43 | ICC_N = 0, // Never |
| 44 | ICC_NE = 9, // Not Equal |
| 45 | ICC_E = 1, // Equal |
| 46 | ICC_G = 10, // Greater |
| 47 | ICC_LE = 2, // Less or Equal |
| 48 | ICC_GE = 11, // Greater or Equal |
| 49 | ICC_L = 3, // Less |
| 50 | ICC_GU = 12, // Greater Unsigned |
| 51 | ICC_LEU = 4, // Less or Equal Unsigned |
| 52 | ICC_CC = 13, // Carry Clear/Great or Equal Unsigned |
| 53 | ICC_CS = 5, // Carry Set/Less Unsigned |
| 54 | ICC_POS = 14, // Positive |
| 55 | ICC_NEG = 6, // Negative |
| 56 | ICC_VC = 15, // Overflow Clear |
| 57 | ICC_VS = 7, // Overflow Set |
| 58 | |
| 59 | FCC_BEGIN = 16, |
| 60 | FCC_A = 8 + FCC_BEGIN, // Always |
| 61 | FCC_N = 0 + FCC_BEGIN, // Never |
| 62 | FCC_U = 7 + FCC_BEGIN, // Unordered |
| 63 | FCC_G = 6 + FCC_BEGIN, // Greater |
| 64 | FCC_UG = 5 + FCC_BEGIN, // Unordered or Greater |
| 65 | FCC_L = 4 + FCC_BEGIN, // Less |
| 66 | FCC_UL = 3 + FCC_BEGIN, // Unordered or Less |
| 67 | FCC_LG = 2 + FCC_BEGIN, // Less or Greater |
| 68 | FCC_NE = 1 + FCC_BEGIN, // Not Equal |
| 69 | FCC_E = 9 + FCC_BEGIN, // Equal |
| 70 | FCC_UE = 10 + FCC_BEGIN, // Unordered or Equal |
| 71 | FCC_GE = 11 + FCC_BEGIN, // Greater or Equal |
| 72 | FCC_UGE = 12 + FCC_BEGIN, // Unordered or Greater or Equal |
| 73 | FCC_LE = 13 + FCC_BEGIN, // Less or Equal |
| 74 | FCC_ULE = 14 + FCC_BEGIN, // Unordered or Less or Equal |
| 75 | FCC_O = 15 + FCC_BEGIN, // Ordered |
| 76 | |
| 77 | CPCC_BEGIN = 32, |
| 78 | CPCC_A = 8 + CPCC_BEGIN, // Always |
| 79 | CPCC_N = 0 + CPCC_BEGIN, // Never |
| 80 | CPCC_3 = 7 + CPCC_BEGIN, |
| 81 | CPCC_2 = 6 + CPCC_BEGIN, |
| 82 | CPCC_23 = 5 + CPCC_BEGIN, |
| 83 | CPCC_1 = 4 + CPCC_BEGIN, |
| 84 | CPCC_13 = 3 + CPCC_BEGIN, |
| 85 | CPCC_12 = 2 + CPCC_BEGIN, |
| 86 | CPCC_123 = 1 + CPCC_BEGIN, |
| 87 | CPCC_0 = 9 + CPCC_BEGIN, |
| 88 | CPCC_03 = 10 + CPCC_BEGIN, |
| 89 | CPCC_02 = 11 + CPCC_BEGIN, |
| 90 | CPCC_023 = 12 + CPCC_BEGIN, |
| 91 | CPCC_01 = 13 + CPCC_BEGIN, |
| 92 | CPCC_013 = 14 + CPCC_BEGIN, |
| 93 | CPCC_012 = 15 + CPCC_BEGIN, |
| 94 | |
| 95 | REG_BEGIN = 48, |
| 96 | REG_Z = 1 + REG_BEGIN, // Is zero |
| 97 | REG_LEZ = 2 + REG_BEGIN, // Less or equal to zero |
| 98 | REG_LZ = 3 + REG_BEGIN, // Less than zero |
| 99 | REG_NZ = 5 + REG_BEGIN, // Is not zero |
| 100 | REG_GZ = 6 + REG_BEGIN, // Greater than zero |
| 101 | REG_GEZ = 7 + REG_BEGIN // Greater than or equal to zero |
| 102 | }; |
| 103 | } |
| 104 | |
| 105 | inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { |
| 106 | switch (CC) { |
| 107 | case SPCC::ICC_A: return "a" ; |
| 108 | case SPCC::ICC_N: return "n" ; |
| 109 | case SPCC::ICC_NE: return "ne" ; |
| 110 | case SPCC::ICC_E: return "e" ; |
| 111 | case SPCC::ICC_G: return "g" ; |
| 112 | case SPCC::ICC_LE: return "le" ; |
| 113 | case SPCC::ICC_GE: return "ge" ; |
| 114 | case SPCC::ICC_L: return "l" ; |
| 115 | case SPCC::ICC_GU: return "gu" ; |
| 116 | case SPCC::ICC_LEU: return "leu" ; |
| 117 | case SPCC::ICC_CC: return "cc" ; |
| 118 | case SPCC::ICC_CS: return "cs" ; |
| 119 | case SPCC::ICC_POS: return "pos" ; |
| 120 | case SPCC::ICC_NEG: return "neg" ; |
| 121 | case SPCC::ICC_VC: return "vc" ; |
| 122 | case SPCC::ICC_VS: return "vs" ; |
| 123 | case SPCC::FCC_A: return "a" ; |
| 124 | case SPCC::FCC_N: return "n" ; |
| 125 | case SPCC::FCC_U: return "u" ; |
| 126 | case SPCC::FCC_G: return "g" ; |
| 127 | case SPCC::FCC_UG: return "ug" ; |
| 128 | case SPCC::FCC_L: return "l" ; |
| 129 | case SPCC::FCC_UL: return "ul" ; |
| 130 | case SPCC::FCC_LG: return "lg" ; |
| 131 | case SPCC::FCC_NE: return "ne" ; |
| 132 | case SPCC::FCC_E: return "e" ; |
| 133 | case SPCC::FCC_UE: return "ue" ; |
| 134 | case SPCC::FCC_GE: return "ge" ; |
| 135 | case SPCC::FCC_UGE: return "uge" ; |
| 136 | case SPCC::FCC_LE: return "le" ; |
| 137 | case SPCC::FCC_ULE: return "ule" ; |
| 138 | case SPCC::FCC_O: return "o" ; |
| 139 | case SPCC::CPCC_A: return "a" ; |
| 140 | case SPCC::CPCC_N: return "n" ; |
| 141 | case SPCC::CPCC_3: return "3" ; |
| 142 | case SPCC::CPCC_2: return "2" ; |
| 143 | case SPCC::CPCC_23: return "23" ; |
| 144 | case SPCC::CPCC_1: return "1" ; |
| 145 | case SPCC::CPCC_13: return "13" ; |
| 146 | case SPCC::CPCC_12: return "12" ; |
| 147 | case SPCC::CPCC_123: return "123" ; |
| 148 | case SPCC::CPCC_0: return "0" ; |
| 149 | case SPCC::CPCC_03: return "03" ; |
| 150 | case SPCC::CPCC_02: return "02" ; |
| 151 | case SPCC::CPCC_023: return "023" ; |
| 152 | case SPCC::CPCC_01: return "01" ; |
| 153 | case SPCC::CPCC_013: return "013" ; |
| 154 | case SPCC::CPCC_012: return "012" ; |
| 155 | case SPCC::REG_BEGIN: |
| 156 | llvm_unreachable("Use of reserved cond code" ); |
| 157 | case SPCC::REG_Z: |
| 158 | return "z" ; |
| 159 | case SPCC::REG_LEZ: |
| 160 | return "lez" ; |
| 161 | case SPCC::REG_LZ: |
| 162 | return "lz" ; |
| 163 | case SPCC::REG_NZ: |
| 164 | return "nz" ; |
| 165 | case SPCC::REG_GZ: |
| 166 | return "gz" ; |
| 167 | case SPCC::REG_GEZ: |
| 168 | return "gez" ; |
| 169 | } |
| 170 | llvm_unreachable("Invalid cond code" ); |
| 171 | } |
| 172 | |
| 173 | inline static unsigned HI22(int64_t imm) { |
| 174 | return (unsigned)((imm >> 10) & ((1 << 22)-1)); |
| 175 | } |
| 176 | |
| 177 | inline static unsigned LO10(int64_t imm) { |
| 178 | return (unsigned)(imm & 0x3FF); |
| 179 | } |
| 180 | |
| 181 | inline static unsigned HIX22(int64_t imm) { |
| 182 | return HI22(imm: ~imm); |
| 183 | } |
| 184 | |
| 185 | inline static unsigned LOX10(int64_t imm) { |
| 186 | return ~LO10(imm: ~imm); |
| 187 | } |
| 188 | |
| 189 | } // end namespace llvm |
| 190 | #endif |
| 191 | |