1//===-- XCoreTargetMachine.cpp - Define TargetMachine for XCore -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "XCoreTargetMachine.h"
13#include "TargetInfo/XCoreTargetInfo.h"
14#include "XCore.h"
15#include "XCoreMachineFunctionInfo.h"
16#include "XCoreTargetObjectFile.h"
17#include "XCoreTargetTransformInfo.h"
18#include "llvm/Analysis/TargetTransformInfo.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/TargetPassConfig.h"
21#include "llvm/MC/TargetRegistry.h"
22#include "llvm/Support/CodeGen.h"
23#include "llvm/Support/Compiler.h"
24#include <optional>
25
26using namespace llvm;
27
28static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
29 return RM.value_or(u: Reloc::Static);
30}
31
32static CodeModel::Model
33getEffectiveXCoreCodeModel(std::optional<CodeModel::Model> CM) {
34 if (CM) {
35 if (*CM != CodeModel::Small && *CM != CodeModel::Large)
36 report_fatal_error(reason: "Target only supports CodeModel Small or Large");
37 return *CM;
38 }
39 return CodeModel::Small;
40}
41
42/// Create an ILP32 architecture model
43///
44XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
45 StringRef CPU, StringRef FS,
46 const TargetOptions &Options,
47 std::optional<Reloc::Model> RM,
48 std::optional<CodeModel::Model> CM,
49 CodeGenOptLevel OL, bool JIT)
50 : CodeGenTargetMachineImpl(
51 T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
52 TT, CPU, FS, Options, getEffectiveRelocModel(RM),
53 getEffectiveXCoreCodeModel(CM), OL),
54 TLOF(std::make_unique<XCoreTargetObjectFile>()),
55 Subtarget(TT, std::string(CPU), std::string(FS), *this) {
56 initAsmInfo();
57}
58
59XCoreTargetMachine::~XCoreTargetMachine() = default;
60
61namespace {
62
63/// XCore Code Generator Pass Configuration Options.
64class XCorePassConfig : public TargetPassConfig {
65public:
66 XCorePassConfig(XCoreTargetMachine &TM, PassManagerBase &PM)
67 : TargetPassConfig(TM, PM) {}
68
69 XCoreTargetMachine &getXCoreTargetMachine() const {
70 return getTM<XCoreTargetMachine>();
71 }
72
73 void addIRPasses() override;
74 bool addPreISel() override;
75 bool addInstSelector() override;
76 void addPreEmitPass() override;
77};
78
79} // end anonymous namespace
80
81TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
82 return new XCorePassConfig(*this, PM);
83}
84
85void XCorePassConfig::addIRPasses() {
86 addPass(P: createAtomicExpandLegacyPass());
87
88 TargetPassConfig::addIRPasses();
89}
90
91bool XCorePassConfig::addPreISel() {
92 addPass(P: createXCoreLowerThreadLocalPass());
93 return false;
94}
95
96bool XCorePassConfig::addInstSelector() {
97 addPass(P: createXCoreISelDag(TM&: getXCoreTargetMachine(), OptLevel: getOptLevel()));
98 return false;
99}
100
101void XCorePassConfig::addPreEmitPass() {
102 addPass(P: createXCoreFrameToArgsOffsetEliminationPass());
103}
104
105// Force static initialization.
106extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreTarget() {
107 RegisterTargetMachine<XCoreTargetMachine> X(getTheXCoreTarget());
108 PassRegistry &PR = *PassRegistry::getPassRegistry();
109 initializeXCoreAsmPrinterPass(PR);
110 initializeXCoreDAGToDAGISelLegacyPass(PR);
111 initializeXCoreLowerThreadLocalPass(p&: PR);
112}
113
114TargetTransformInfo
115XCoreTargetMachine::getTargetTransformInfo(const Function &F) const {
116 return TargetTransformInfo(std::make_unique<XCoreTTIImpl>(args: this, args: F));
117}
118
119MachineFunctionInfo *XCoreTargetMachine::createMachineFunctionInfo(
120 BumpPtrAllocator &Allocator, const Function &F,
121 const TargetSubtargetInfo *STI) const {
122 return XCoreFunctionInfo::create<XCoreFunctionInfo>(Allocator, F, STI);
123}
124