1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifndef GET_CC_REGISTER_LISTS
10
11bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
12 MVT LocVT, CCValAssign::LocInfo LocInfo,
13 ISD::ArgFlagsTy ArgFlags, CCState &State);
14bool llvm::CC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
15 MVT LocVT, CCValAssign::LocInfo LocInfo,
16 ISD::ArgFlagsTy ArgFlags, CCState &State);
17bool llvm::CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
18 MVT LocVT, CCValAssign::LocInfo LocInfo,
19 ISD::ArgFlagsTy ArgFlags, CCState &State);
20bool llvm::CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, CCState &State);
23bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT,
24 MVT LocVT, CCValAssign::LocInfo LocInfo,
25 ISD::ArgFlagsTy ArgFlags, CCState &State);
26bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
27 MVT LocVT, CCValAssign::LocInfo LocInfo,
28 ISD::ArgFlagsTy ArgFlags, CCState &State);
29bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT,
30 MVT LocVT, CCValAssign::LocInfo LocInfo,
31 ISD::ArgFlagsTy ArgFlags, CCState &State);
32bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
33 MVT LocVT, CCValAssign::LocInfo LocInfo,
34 ISD::ArgFlagsTy ArgFlags, CCState &State);
35bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
36 MVT LocVT, CCValAssign::LocInfo LocInfo,
37 ISD::ArgFlagsTy ArgFlags, CCState &State);
38bool llvm::CC_AArch64_Preserve_None(unsigned ValNo, MVT ValVT,
39 MVT LocVT, CCValAssign::LocInfo LocInfo,
40 ISD::ArgFlagsTy ArgFlags, CCState &State);
41bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT,
42 MVT LocVT, CCValAssign::LocInfo LocInfo,
43 ISD::ArgFlagsTy ArgFlags, CCState &State);
44bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT,
45 MVT LocVT, CCValAssign::LocInfo LocInfo,
46 ISD::ArgFlagsTy ArgFlags, CCState &State);
47bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
48 MVT LocVT, CCValAssign::LocInfo LocInfo,
49 ISD::ArgFlagsTy ArgFlags, CCState &State);
50bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
51 MVT LocVT, CCValAssign::LocInfo LocInfo,
52 ISD::ArgFlagsTy ArgFlags, CCState &State);
53bool llvm::RetCC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
54 MVT LocVT, CCValAssign::LocInfo LocInfo,
55 ISD::ArgFlagsTy ArgFlags, CCState &State);
56bool llvm::RetCC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
57 MVT LocVT, CCValAssign::LocInfo LocInfo,
58 ISD::ArgFlagsTy ArgFlags, CCState &State);
59
60
61bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
62 MVT LocVT, CCValAssign::LocInfo LocInfo,
63 ISD::ArgFlagsTy ArgFlags, CCState &State) {
64
65 if (ArgFlags.isNest()) {
66 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X18)) {
67 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
68 return false;
69 }
70 }
71
72 if (LocVT == MVT::iPTR) {
73 LocVT = MVT::i64;
74 LocInfo = CCValAssign::BCvt;
75 }
76
77 if (LocVT == MVT::v2f32) {
78 LocVT = MVT::v2i32;
79 LocInfo = CCValAssign::BCvt;
80 }
81
82 if (LocVT == MVT::v2f64 ||
83 LocVT == MVT::v4f32) {
84 LocVT = MVT::v2i64;
85 LocInfo = CCValAssign::BCvt;
86 }
87
88 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
89 if (LocVT == MVT::v2i32 ||
90 LocVT == MVT::v2f32 ||
91 LocVT == MVT::v4i16 ||
92 LocVT == MVT::v4f16 ||
93 LocVT == MVT::v4bf16 ||
94 LocVT == MVT::v8i8) {
95 LocVT = MVT::f64;
96 LocInfo = CCValAssign::BCvt;
97 }
98 }
99
100 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
101 if (LocVT == MVT::v2i64 ||
102 LocVT == MVT::v2f64 ||
103 LocVT == MVT::v4i32 ||
104 LocVT == MVT::v4f32 ||
105 LocVT == MVT::v8i16 ||
106 LocVT == MVT::v8f16 ||
107 LocVT == MVT::v8bf16 ||
108 LocVT == MVT::v16i8) {
109 LocVT = MVT::f128;
110 LocInfo = CCValAssign::BCvt;
111 }
112 }
113
114 if (ArgFlags.isInReg()) {
115 if (LocVT == MVT::i64) {
116 if (ArgFlags.isSRet()) {
117 if (LocVT == MVT::i64) {
118 static const MCPhysReg RegList1[] = {
119 AArch64::X0, AArch64::X1
120 };
121 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
122 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
123 return false;
124 }
125 }
126 }
127 }
128 }
129
130 if (ArgFlags.isSRet()) {
131 if (LocVT == MVT::i64) {
132 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X8)) {
133 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
134 return false;
135 }
136 }
137 }
138
139 if (ArgFlags.isByVal()) {
140 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
141 return false;
142 }
143
144 if (ArgFlags.isSwiftSelf()) {
145 if (LocVT == MVT::i64) {
146 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X20)) {
147 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
148 return false;
149 }
150 }
151 }
152
153 if (ArgFlags.isSwiftError()) {
154 if (LocVT == MVT::i64) {
155 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X21)) {
156 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
157 return false;
158 }
159 }
160 }
161
162 if (ArgFlags.isSwiftAsync()) {
163 if (LocVT == MVT::i64) {
164 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X22)) {
165 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
166 return false;
167 }
168 }
169 }
170
171 if (ArgFlags.isInConsecutiveRegs()) {
172 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
173 return false;
174 }
175
176 if (LocVT == MVT::nxv16i8 ||
177 LocVT == MVT::nxv8i16 ||
178 LocVT == MVT::nxv4i32 ||
179 LocVT == MVT::nxv2i64 ||
180 LocVT == MVT::nxv2f16 ||
181 LocVT == MVT::nxv4f16 ||
182 LocVT == MVT::nxv8f16 ||
183 LocVT == MVT::nxv2bf16 ||
184 LocVT == MVT::nxv4bf16 ||
185 LocVT == MVT::nxv8bf16 ||
186 LocVT == MVT::nxv2f32 ||
187 LocVT == MVT::nxv4f32 ||
188 LocVT == MVT::nxv2f64) {
189 static const MCPhysReg RegList2[] = {
190 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
191 };
192 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
193 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
194 return false;
195 }
196 }
197
198 if (LocVT == MVT::nxv16i8 ||
199 LocVT == MVT::nxv8i16 ||
200 LocVT == MVT::nxv4i32 ||
201 LocVT == MVT::nxv2i64 ||
202 LocVT == MVT::nxv2f16 ||
203 LocVT == MVT::nxv4f16 ||
204 LocVT == MVT::nxv8f16 ||
205 LocVT == MVT::nxv2bf16 ||
206 LocVT == MVT::nxv4bf16 ||
207 LocVT == MVT::nxv8bf16 ||
208 LocVT == MVT::nxv2f32 ||
209 LocVT == MVT::nxv4f32 ||
210 LocVT == MVT::nxv2f64) {
211 LocVT = MVT::i64;
212 LocInfo = CCValAssign::Indirect;
213 }
214
215 if (LocVT == MVT::nxv1i1 ||
216 LocVT == MVT::nxv2i1 ||
217 LocVT == MVT::nxv4i1 ||
218 LocVT == MVT::nxv8i1 ||
219 LocVT == MVT::nxv16i1 ||
220 LocVT == MVT::aarch64svcount) {
221 static const MCPhysReg RegList3[] = {
222 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
223 };
224 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
225 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
226 return false;
227 }
228 }
229
230 if (LocVT == MVT::nxv1i1 ||
231 LocVT == MVT::nxv2i1 ||
232 LocVT == MVT::nxv4i1 ||
233 LocVT == MVT::nxv8i1 ||
234 LocVT == MVT::nxv16i1 ||
235 LocVT == MVT::aarch64svcount) {
236 LocVT = MVT::i64;
237 LocInfo = CCValAssign::Indirect;
238 }
239
240 if (LocVT == MVT::i1 ||
241 LocVT == MVT::i8 ||
242 LocVT == MVT::i16) {
243 LocVT = MVT::i32;
244 if (ArgFlags.isSExt())
245 LocInfo = CCValAssign::SExt;
246 else if (ArgFlags.isZExt())
247 LocInfo = CCValAssign::ZExt;
248 else
249 LocInfo = CCValAssign::AExt;
250 }
251
252 if (LocVT == MVT::i32) {
253 static const MCPhysReg RegList4[] = {
254 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
255 };
256 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
257 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
258 return false;
259 }
260 }
261
262 if (LocVT == MVT::i64) {
263 if (ArgFlags.isSplit()) {
264 static const MCPhysReg RegList5[] = {
265 AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
266 };
267 static const MCPhysReg RegList6[] = {
268 AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
269 };
270 if (unsigned Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
271 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
272 return false;
273 }
274 }
275 }
276
277 if (LocVT == MVT::i64) {
278 if (ArgFlags.isSplit()) {
279 static const MCPhysReg ShadowRegList7[] = {
280 AArch64::X7
281 };
282 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList7);
283 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
284 return false;
285 }
286 }
287
288 if (LocVT == MVT::i64) {
289 static const MCPhysReg RegList9[] = {
290 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
291 };
292 if (unsigned Reg = State.AllocateReg(Regs: RegList9)) {
293 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
294 return false;
295 }
296 }
297
298 if (LocVT == MVT::f16) {
299 static const MCPhysReg RegList10[] = {
300 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
301 };
302 if (unsigned Reg = State.AllocateReg(Regs: RegList10)) {
303 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
304 return false;
305 }
306 }
307
308 if (LocVT == MVT::bf16) {
309 static const MCPhysReg RegList11[] = {
310 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
311 };
312 if (unsigned Reg = State.AllocateReg(Regs: RegList11)) {
313 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
314 return false;
315 }
316 }
317
318 if (LocVT == MVT::f32) {
319 static const MCPhysReg RegList12[] = {
320 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
321 };
322 if (unsigned Reg = State.AllocateReg(Regs: RegList12)) {
323 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
324 return false;
325 }
326 }
327
328 if (LocVT == MVT::f64) {
329 static const MCPhysReg RegList13[] = {
330 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
331 };
332 if (unsigned Reg = State.AllocateReg(Regs: RegList13)) {
333 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
334 return false;
335 }
336 }
337
338 if (LocVT == MVT::v1i64 ||
339 LocVT == MVT::v2i32 ||
340 LocVT == MVT::v4i16 ||
341 LocVT == MVT::v8i8 ||
342 LocVT == MVT::v1f64 ||
343 LocVT == MVT::v2f32 ||
344 LocVT == MVT::v4f16 ||
345 LocVT == MVT::v4bf16) {
346 static const MCPhysReg RegList14[] = {
347 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
348 };
349 if (unsigned Reg = State.AllocateReg(Regs: RegList14)) {
350 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
351 return false;
352 }
353 }
354
355 if (LocVT == MVT::f128 ||
356 LocVT == MVT::v2i64 ||
357 LocVT == MVT::v4i32 ||
358 LocVT == MVT::v8i16 ||
359 LocVT == MVT::v16i8 ||
360 LocVT == MVT::v4f32 ||
361 LocVT == MVT::v2f64 ||
362 LocVT == MVT::v8f16 ||
363 LocVT == MVT::v8bf16) {
364 static const MCPhysReg RegList15[] = {
365 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
366 };
367 if (unsigned Reg = State.AllocateReg(Regs: RegList15)) {
368 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
369 return false;
370 }
371 }
372
373 if (LocVT == MVT::i1 ||
374 LocVT == MVT::i8 ||
375 LocVT == MVT::i16 ||
376 LocVT == MVT::f16 ||
377 LocVT == MVT::bf16) {
378 int64_t Offset16 = State.AllocateStack(Size: 8, Alignment: Align(8));
379 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
380 return false;
381 }
382
383 if (LocVT == MVT::i32 ||
384 LocVT == MVT::f32) {
385 int64_t Offset17 = State.AllocateStack(Size: 8, Alignment: Align(8));
386 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
387 return false;
388 }
389
390 if (LocVT == MVT::i64 ||
391 LocVT == MVT::f64 ||
392 LocVT == MVT::v1f64 ||
393 LocVT == MVT::v2f32 ||
394 LocVT == MVT::v1i64 ||
395 LocVT == MVT::v2i32 ||
396 LocVT == MVT::v4i16 ||
397 LocVT == MVT::v8i8 ||
398 LocVT == MVT::v4f16 ||
399 LocVT == MVT::v4bf16) {
400 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
401 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
402 return false;
403 }
404
405 if (LocVT == MVT::f128 ||
406 LocVT == MVT::v2i64 ||
407 LocVT == MVT::v4i32 ||
408 LocVT == MVT::v8i16 ||
409 LocVT == MVT::v16i8 ||
410 LocVT == MVT::v4f32 ||
411 LocVT == MVT::v2f64 ||
412 LocVT == MVT::v8f16 ||
413 LocVT == MVT::v8bf16) {
414 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
415 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
416 return false;
417 }
418
419 return true; // CC didn't match.
420}
421
422
423bool llvm::CC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
424 MVT LocVT, CCValAssign::LocInfo LocInfo,
425 ISD::ArgFlagsTy ArgFlags, CCState &State) {
426
427 if (LocVT == MVT::i64) {
428 static const MCPhysReg RegList1[] = {
429 AArch64::X11, AArch64::X10, AArch64::X9
430 };
431 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
432 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
433 return false;
434 }
435 }
436
437 return true; // CC didn't match.
438}
439
440
441bool llvm::CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
442 MVT LocVT, CCValAssign::LocInfo LocInfo,
443 ISD::ArgFlagsTy ArgFlags, CCState &State) {
444
445 if (ArgFlags.isInReg()) {
446 if (LocVT == MVT::i64) {
447 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X4)) {
448 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
449 return false;
450 }
451 }
452 }
453
454 if (ArgFlags.isByVal()) {
455 LocVT = MVT::i64;
456 LocInfo = CCValAssign::Indirect;
457 }
458
459 if (LocVT == MVT::i1 ||
460 LocVT == MVT::i8 ||
461 LocVT == MVT::i16) {
462 LocVT = MVT::i32;
463 if (ArgFlags.isSExt())
464 LocInfo = CCValAssign::SExt;
465 else if (ArgFlags.isZExt())
466 LocInfo = CCValAssign::ZExt;
467 else
468 LocInfo = CCValAssign::AExt;
469 }
470
471 if (ArgFlags.isNest()) {
472 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X4)) {
473 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
474 return false;
475 }
476 }
477
478 if (ArgFlags.isSwiftError()) {
479 if (LocVT == MVT::i64) {
480 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X19)) {
481 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
482 return false;
483 }
484 }
485 }
486
487 if (ArgFlags.isSwiftSelf()) {
488 if (LocVT == MVT::i64) {
489 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X20)) {
490 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
491 return false;
492 }
493 }
494 }
495
496 if (ArgFlags.isSwiftAsync()) {
497 if (LocVT == MVT::i64) {
498 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X21)) {
499 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
500 return false;
501 }
502 }
503 }
504
505 if (ArgFlags.isCFGuardTarget()) {
506 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X8)) {
507 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
508 return false;
509 }
510 }
511
512 if (LocVT == MVT::v16i8 ||
513 LocVT == MVT::v8i16 ||
514 LocVT == MVT::v4i32 ||
515 LocVT == MVT::v2i64 ||
516 LocVT == MVT::v8f16 ||
517 LocVT == MVT::v4f32 ||
518 LocVT == MVT::v2f64) {
519 LocVT = MVT::i64;
520 LocInfo = CCValAssign::Indirect;
521 }
522
523 if (LocVT == MVT::v32i8 ||
524 LocVT == MVT::v16i16 ||
525 LocVT == MVT::v8i32 ||
526 LocVT == MVT::v4i64 ||
527 LocVT == MVT::v16f16 ||
528 LocVT == MVT::v8f32 ||
529 LocVT == MVT::v4f64) {
530 LocVT = MVT::i64;
531 LocInfo = CCValAssign::Indirect;
532 }
533
534 if (LocVT == MVT::v64i8 ||
535 LocVT == MVT::v32i16 ||
536 LocVT == MVT::v16i32 ||
537 LocVT == MVT::v32f16 ||
538 LocVT == MVT::v16f32 ||
539 LocVT == MVT::v8f64 ||
540 LocVT == MVT::v8i64) {
541 LocVT = MVT::i64;
542 LocInfo = CCValAssign::Indirect;
543 }
544
545 if (LocVT == MVT::f80) {
546 LocVT = MVT::i64;
547 LocInfo = CCValAssign::Indirect;
548 }
549
550 if (LocVT == MVT::x86mmx) {
551 LocVT = MVT::i64;
552 LocInfo = CCValAssign::BCvt;
553 }
554
555 if (LocVT == MVT::f16) {
556 static const MCPhysReg RegList1[] = {
557 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3
558 };
559 static const MCPhysReg RegList2[] = {
560 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
561 };
562 if (unsigned Reg = State.AllocateReg(Regs: RegList1, ShadowRegs: RegList2)) {
563 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
564 return false;
565 }
566 }
567
568 if (LocVT == MVT::f32) {
569 static const MCPhysReg RegList3[] = {
570 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3
571 };
572 static const MCPhysReg RegList4[] = {
573 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
574 };
575 if (unsigned Reg = State.AllocateReg(Regs: RegList3, ShadowRegs: RegList4)) {
576 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
577 return false;
578 }
579 }
580
581 if (LocVT == MVT::f64) {
582 static const MCPhysReg RegList5[] = {
583 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3
584 };
585 static const MCPhysReg RegList6[] = {
586 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
587 };
588 if (unsigned Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
589 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
590 return false;
591 }
592 }
593
594 if (LocVT == MVT::i32) {
595 static const MCPhysReg RegList7[] = {
596 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3
597 };
598 static const MCPhysReg RegList8[] = {
599 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
600 };
601 if (unsigned Reg = State.AllocateReg(Regs: RegList7, ShadowRegs: RegList8)) {
602 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
603 return false;
604 }
605 }
606
607 if (LocVT == MVT::i64) {
608 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X9)) {
609 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
610 return false;
611 }
612 }
613
614 if (LocVT == MVT::i64) {
615 static const MCPhysReg RegList9[] = {
616 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
617 };
618 static const MCPhysReg RegList10[] = {
619 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
620 };
621 if (unsigned Reg = State.AllocateReg(Regs: RegList9, ShadowRegs: RegList10)) {
622 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
623 return false;
624 }
625 }
626
627 if (LocVT == MVT::i8 ||
628 LocVT == MVT::i16 ||
629 LocVT == MVT::i32 ||
630 LocVT == MVT::i64 ||
631 LocVT == MVT::f16 ||
632 LocVT == MVT::f32 ||
633 LocVT == MVT::f64) {
634 int64_t Offset11 = State.AllocateStack(Size: 8, Alignment: Align(8));
635 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset11, LocVT, HTP: LocInfo));
636 return false;
637 }
638
639 return true; // CC didn't match.
640}
641
642
643bool llvm::CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT,
644 MVT LocVT, CCValAssign::LocInfo LocInfo,
645 ISD::ArgFlagsTy ArgFlags, CCState &State) {
646
647 if (LocVT == MVT::i64) {
648 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X9)) {
649 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
650 return false;
651 }
652 }
653
654 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
655 return false;
656
657 return true; // CC didn't match.
658}
659
660
661bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT,
662 MVT LocVT, CCValAssign::LocInfo LocInfo,
663 ISD::ArgFlagsTy ArgFlags, CCState &State) {
664
665 if (LocVT == MVT::f16 ||
666 LocVT == MVT::bf16) {
667 LocVT = MVT::i16;
668 LocInfo = CCValAssign::BCvt;
669 }
670
671 if (LocVT == MVT::f32) {
672 LocVT = MVT::i32;
673 LocInfo = CCValAssign::BCvt;
674 }
675
676 if (LocVT == MVT::f64 ||
677 LocVT == MVT::v1f64 ||
678 LocVT == MVT::v1i64 ||
679 LocVT == MVT::v2f32 ||
680 LocVT == MVT::v2i32 ||
681 LocVT == MVT::v4i16 ||
682 LocVT == MVT::v4f16 ||
683 LocVT == MVT::v4bf16 ||
684 LocVT == MVT::v8i8 ||
685 LocVT == MVT::iPTR) {
686 LocVT = MVT::i64;
687 LocInfo = CCValAssign::BCvt;
688 }
689
690 if (LocVT == MVT::f128 ||
691 LocVT == MVT::v2f64 ||
692 LocVT == MVT::v2i64 ||
693 LocVT == MVT::v4i32 ||
694 LocVT == MVT::v4f32 ||
695 LocVT == MVT::v8i16 ||
696 LocVT == MVT::v8f16 ||
697 LocVT == MVT::v8bf16 ||
698 LocVT == MVT::v16i8) {
699 LocVT = MVT::i64;
700 LocInfo = CCValAssign::Indirect;
701 }
702
703 if (LocVT == MVT::nxv16i8 ||
704 LocVT == MVT::nxv8i16 ||
705 LocVT == MVT::nxv4i32 ||
706 LocVT == MVT::nxv2i64 ||
707 LocVT == MVT::nxv2f16 ||
708 LocVT == MVT::nxv4f16 ||
709 LocVT == MVT::nxv8f16 ||
710 LocVT == MVT::nxv2bf16 ||
711 LocVT == MVT::nxv4bf16 ||
712 LocVT == MVT::nxv8bf16 ||
713 LocVT == MVT::nxv2f32 ||
714 LocVT == MVT::nxv4f32 ||
715 LocVT == MVT::nxv2f64) {
716 LocVT = MVT::i64;
717 LocInfo = CCValAssign::Indirect;
718 }
719
720 if (LocVT == MVT::nxv2i1 ||
721 LocVT == MVT::nxv4i1 ||
722 LocVT == MVT::nxv8i1 ||
723 LocVT == MVT::nxv16i1) {
724 LocVT = MVT::i64;
725 LocInfo = CCValAssign::Indirect;
726 }
727
728 if (ArgFlags.isInReg()) {
729 if (LocVT == MVT::i64) {
730 if (ArgFlags.isSRet()) {
731 if (LocVT == MVT::i64) {
732 static const MCPhysReg RegList1[] = {
733 AArch64::X0, AArch64::X1
734 };
735 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
736 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
737 return false;
738 }
739 }
740 }
741 }
742 }
743
744 if (ArgFlags.isSRet()) {
745 if (LocVT == MVT::i64) {
746 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X8)) {
747 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
748 return false;
749 }
750 }
751 }
752
753 if (ArgFlags.isByVal()) {
754 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
755 return false;
756 }
757
758 if (LocVT == MVT::i1 ||
759 LocVT == MVT::i8 ||
760 LocVT == MVT::i16) {
761 LocVT = MVT::i32;
762 if (ArgFlags.isSExt())
763 LocInfo = CCValAssign::SExt;
764 else if (ArgFlags.isZExt())
765 LocInfo = CCValAssign::ZExt;
766 else
767 LocInfo = CCValAssign::AExt;
768 }
769
770 if (LocVT == MVT::i32) {
771 static const MCPhysReg RegList2[] = {
772 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3
773 };
774 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
775 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
776 return false;
777 }
778 }
779
780 if (LocVT == MVT::i64) {
781 static const MCPhysReg RegList3[] = {
782 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3
783 };
784 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
785 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
786 return false;
787 }
788 }
789
790 if (LocVT == MVT::i32 ||
791 LocVT == MVT::i64) {
792 int64_t Offset4 = State.AllocateStack(Size: 8, Alignment: Align(8));
793 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
794 return false;
795 }
796
797 return true; // CC didn't match.
798}
799
800
801bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
802 MVT LocVT, CCValAssign::LocInfo LocInfo,
803 ISD::ArgFlagsTy ArgFlags, CCState &State) {
804
805 if (LocVT == MVT::iPTR) {
806 LocVT = MVT::i64;
807 LocInfo = CCValAssign::BCvt;
808 }
809
810 if (LocVT == MVT::v2f32) {
811 LocVT = MVT::v2i32;
812 LocInfo = CCValAssign::BCvt;
813 }
814
815 if (LocVT == MVT::v2f64 ||
816 LocVT == MVT::v4f32 ||
817 LocVT == MVT::f128) {
818 LocVT = MVT::v2i64;
819 LocInfo = CCValAssign::BCvt;
820 }
821
822 if (ArgFlags.isSRet()) {
823 if (LocVT == MVT::i64) {
824 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X8)) {
825 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
826 return false;
827 }
828 }
829 }
830
831 if (ArgFlags.isByVal()) {
832 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
833 return false;
834 }
835
836 if (ArgFlags.isSwiftSelf()) {
837 if (LocVT == MVT::i64) {
838 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X20)) {
839 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
840 return false;
841 }
842 }
843 }
844
845 if (ArgFlags.isSwiftError()) {
846 if (LocVT == MVT::i64) {
847 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X21)) {
848 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
849 return false;
850 }
851 }
852 }
853
854 if (ArgFlags.isSwiftAsync()) {
855 if (LocVT == MVT::i64) {
856 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X22)) {
857 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
858 return false;
859 }
860 }
861 }
862
863 if (ArgFlags.isInConsecutiveRegs()) {
864 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
865 return false;
866 }
867
868 if (LocVT == MVT::i1 ||
869 LocVT == MVT::i8 ||
870 LocVT == MVT::i16) {
871 LocVT = MVT::i32;
872 if (ArgFlags.isSExt())
873 LocInfo = CCValAssign::SExt;
874 else if (ArgFlags.isZExt())
875 LocInfo = CCValAssign::ZExt;
876 else
877 LocInfo = CCValAssign::AExt;
878 }
879
880 if (LocVT == MVT::i32) {
881 static const MCPhysReg RegList1[] = {
882 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
883 };
884 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
885 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
886 return false;
887 }
888 }
889
890 if (LocVT == MVT::i64) {
891 if (ArgFlags.isSplit()) {
892 static const MCPhysReg RegList2[] = {
893 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6
894 };
895 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
896 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
897 return false;
898 }
899 }
900 }
901
902 if (LocVT == MVT::i64) {
903 if (ArgFlags.isSplit()) {
904 static const MCPhysReg ShadowRegList3[] = {
905 AArch64::X7
906 };
907 int64_t Offset4 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList3);
908 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
909 return false;
910 }
911 }
912
913 if (LocVT == MVT::i64) {
914 static const MCPhysReg RegList5[] = {
915 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
916 };
917 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
918 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
919 return false;
920 }
921 }
922
923 if (LocVT == MVT::f16) {
924 static const MCPhysReg RegList6[] = {
925 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
926 };
927 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
928 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
929 return false;
930 }
931 }
932
933 if (LocVT == MVT::bf16) {
934 static const MCPhysReg RegList7[] = {
935 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
936 };
937 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
938 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
939 return false;
940 }
941 }
942
943 if (LocVT == MVT::f32) {
944 static const MCPhysReg RegList8[] = {
945 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
946 };
947 if (unsigned Reg = State.AllocateReg(Regs: RegList8)) {
948 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
949 return false;
950 }
951 }
952
953 if (LocVT == MVT::f64) {
954 static const MCPhysReg RegList9[] = {
955 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
956 };
957 if (unsigned Reg = State.AllocateReg(Regs: RegList9)) {
958 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
959 return false;
960 }
961 }
962
963 if (LocVT == MVT::v1i64 ||
964 LocVT == MVT::v2i32 ||
965 LocVT == MVT::v4i16 ||
966 LocVT == MVT::v8i8 ||
967 LocVT == MVT::v1f64 ||
968 LocVT == MVT::v2f32 ||
969 LocVT == MVT::v4f16 ||
970 LocVT == MVT::v4bf16) {
971 static const MCPhysReg RegList10[] = {
972 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
973 };
974 if (unsigned Reg = State.AllocateReg(Regs: RegList10)) {
975 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
976 return false;
977 }
978 }
979
980 if (LocVT == MVT::v2i64 ||
981 LocVT == MVT::v4i32 ||
982 LocVT == MVT::v8i16 ||
983 LocVT == MVT::v16i8 ||
984 LocVT == MVT::v4f32 ||
985 LocVT == MVT::v2f64 ||
986 LocVT == MVT::v8f16 ||
987 LocVT == MVT::v8bf16) {
988 static const MCPhysReg RegList11[] = {
989 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
990 };
991 if (unsigned Reg = State.AllocateReg(Regs: RegList11)) {
992 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
993 return false;
994 }
995 }
996
997 if (ValVT == MVT::i1 || ValVT == MVT::i8) {
998 int64_t Offset12 = State.AllocateStack(Size: 1, Alignment: Align(1));
999 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset12, LocVT, HTP: LocInfo));
1000 return false;
1001 }
1002
1003 if (ValVT == MVT::i16 || ValVT == MVT::f16 || ValVT == MVT::bf16) {
1004 int64_t Offset13 = State.AllocateStack(Size: 2, Alignment: Align(2));
1005 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset13, LocVT, HTP: LocInfo));
1006 return false;
1007 }
1008
1009 if (LocVT == MVT::i32 ||
1010 LocVT == MVT::f32) {
1011 int64_t Offset14 = State.AllocateStack(Size: 4, Alignment: Align(4));
1012 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset14, LocVT, HTP: LocInfo));
1013 return false;
1014 }
1015
1016 if (ArgFlags.isPointer()) {
1017 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1018 LocVT = MVT::i32;
1019 LocInfo = CCValAssign::Trunc;
1020 }
1021 }
1022
1023 if (ArgFlags.isPointer()) {
1024 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1025 int64_t Offset15 = State.AllocateStack(Size: 4, Alignment: Align(4));
1026 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset15, LocVT, HTP: LocInfo));
1027 return false;
1028 }
1029 }
1030
1031 if (LocVT == MVT::i64 ||
1032 LocVT == MVT::f64 ||
1033 LocVT == MVT::v1f64 ||
1034 LocVT == MVT::v2f32 ||
1035 LocVT == MVT::v1i64 ||
1036 LocVT == MVT::v2i32 ||
1037 LocVT == MVT::v4i16 ||
1038 LocVT == MVT::v8i8 ||
1039 LocVT == MVT::v4f16 ||
1040 LocVT == MVT::v4bf16) {
1041 int64_t Offset16 = State.AllocateStack(Size: 8, Alignment: Align(8));
1042 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
1043 return false;
1044 }
1045
1046 if (LocVT == MVT::v2i64 ||
1047 LocVT == MVT::v4i32 ||
1048 LocVT == MVT::v8i16 ||
1049 LocVT == MVT::v16i8 ||
1050 LocVT == MVT::v4f32 ||
1051 LocVT == MVT::v2f64 ||
1052 LocVT == MVT::v8f16 ||
1053 LocVT == MVT::v8bf16) {
1054 int64_t Offset17 = State.AllocateStack(Size: 16, Alignment: Align(16));
1055 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
1056 return false;
1057 }
1058
1059 return true; // CC didn't match.
1060}
1061
1062
1063bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT,
1064 MVT LocVT, CCValAssign::LocInfo LocInfo,
1065 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1066
1067 if (LocVT == MVT::v2f32) {
1068 LocVT = MVT::v2i32;
1069 LocInfo = CCValAssign::BCvt;
1070 }
1071
1072 if (LocVT == MVT::v2f64 ||
1073 LocVT == MVT::v4f32 ||
1074 LocVT == MVT::f128) {
1075 LocVT = MVT::v2i64;
1076 LocInfo = CCValAssign::BCvt;
1077 }
1078
1079 if (LocVT == MVT::i8 ||
1080 LocVT == MVT::i16) {
1081 LocVT = MVT::i32;
1082 if (ArgFlags.isSExt())
1083 LocInfo = CCValAssign::SExt;
1084 else if (ArgFlags.isZExt())
1085 LocInfo = CCValAssign::ZExt;
1086 else
1087 LocInfo = CCValAssign::AExt;
1088 }
1089
1090 if (LocVT == MVT::f16 ||
1091 LocVT == MVT::bf16) {
1092 LocVT = MVT::f32;
1093 LocInfo = CCValAssign::FPExt;
1094 }
1095
1096 if (ArgFlags.isPointer()) {
1097 if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) {
1098 LocVT = MVT::i32;
1099 LocInfo = CCValAssign::Trunc;
1100 }
1101 }
1102
1103 if (LocVT == MVT::i32 ||
1104 LocVT == MVT::f32) {
1105 int64_t Offset1 = State.AllocateStack(Size: 4, Alignment: Align(4));
1106 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1107 return false;
1108 }
1109
1110 if (LocVT == MVT::i64) {
1111 if (ArgFlags.isSplit()) {
1112 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(16));
1113 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1114 return false;
1115 }
1116 }
1117
1118 if (LocVT == MVT::i64 ||
1119 LocVT == MVT::f64 ||
1120 LocVT == MVT::v1i64 ||
1121 LocVT == MVT::v2i32 ||
1122 LocVT == MVT::v4i16 ||
1123 LocVT == MVT::v8i8 ||
1124 LocVT == MVT::v1f64 ||
1125 LocVT == MVT::v2f32 ||
1126 LocVT == MVT::v4f16 ||
1127 LocVT == MVT::v4bf16) {
1128 int64_t Offset3 = State.AllocateStack(Size: 8, Alignment: Align(8));
1129 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1130 return false;
1131 }
1132
1133 if (LocVT == MVT::v2i64 ||
1134 LocVT == MVT::v4i32 ||
1135 LocVT == MVT::v8i16 ||
1136 LocVT == MVT::v16i8 ||
1137 LocVT == MVT::v4f32 ||
1138 LocVT == MVT::v2f64 ||
1139 LocVT == MVT::v8f16 ||
1140 LocVT == MVT::v8bf16) {
1141 int64_t Offset4 = State.AllocateStack(Size: 16, Alignment: Align(16));
1142 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset4, LocVT, HTP: LocInfo));
1143 return false;
1144 }
1145
1146 return true; // CC didn't match.
1147}
1148
1149
1150bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
1151 MVT LocVT, CCValAssign::LocInfo LocInfo,
1152 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1153
1154 if (LocVT == MVT::iPTR) {
1155 LocVT = MVT::i64;
1156 LocInfo = CCValAssign::BCvt;
1157 }
1158
1159 if (LocVT == MVT::v2f32) {
1160 LocVT = MVT::v2i32;
1161 LocInfo = CCValAssign::BCvt;
1162 }
1163
1164 if (LocVT == MVT::v2f64 ||
1165 LocVT == MVT::v4f32 ||
1166 LocVT == MVT::f128) {
1167 LocVT = MVT::v2i64;
1168 LocInfo = CCValAssign::BCvt;
1169 }
1170
1171 if (ArgFlags.isInConsecutiveRegs()) {
1172 if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1173 return false;
1174 }
1175
1176 if (LocVT == MVT::i8 ||
1177 LocVT == MVT::i16 ||
1178 LocVT == MVT::i32) {
1179 LocVT = MVT::i64;
1180 if (ArgFlags.isSExt())
1181 LocInfo = CCValAssign::SExt;
1182 else if (ArgFlags.isZExt())
1183 LocInfo = CCValAssign::ZExt;
1184 else
1185 LocInfo = CCValAssign::AExt;
1186 }
1187
1188 if (LocVT == MVT::f16 ||
1189 LocVT == MVT::bf16 ||
1190 LocVT == MVT::f32) {
1191 LocVT = MVT::f64;
1192 LocInfo = CCValAssign::FPExt;
1193 }
1194
1195 if (LocVT == MVT::i64) {
1196 if (ArgFlags.isSplit()) {
1197 int64_t Offset1 = State.AllocateStack(Size: 8, Alignment: Align(16));
1198 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset1, LocVT, HTP: LocInfo));
1199 return false;
1200 }
1201 }
1202
1203 if (LocVT == MVT::i64 ||
1204 LocVT == MVT::f64 ||
1205 LocVT == MVT::v1i64 ||
1206 LocVT == MVT::v2i32 ||
1207 LocVT == MVT::v4i16 ||
1208 LocVT == MVT::v8i8 ||
1209 LocVT == MVT::v1f64 ||
1210 LocVT == MVT::v2f32 ||
1211 LocVT == MVT::v4f16 ||
1212 LocVT == MVT::v4bf16) {
1213 int64_t Offset2 = State.AllocateStack(Size: 8, Alignment: Align(8));
1214 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
1215 return false;
1216 }
1217
1218 if (LocVT == MVT::v2i64 ||
1219 LocVT == MVT::v4i32 ||
1220 LocVT == MVT::v8i16 ||
1221 LocVT == MVT::v16i8 ||
1222 LocVT == MVT::v4f32 ||
1223 LocVT == MVT::v2f64 ||
1224 LocVT == MVT::v8f16 ||
1225 LocVT == MVT::v8bf16) {
1226 int64_t Offset3 = State.AllocateStack(Size: 16, Alignment: Align(16));
1227 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset3, LocVT, HTP: LocInfo));
1228 return false;
1229 }
1230
1231 return true; // CC didn't match.
1232}
1233
1234
1235bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
1236 MVT LocVT, CCValAssign::LocInfo LocInfo,
1237 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1238
1239 if (LocVT == MVT::iPTR) {
1240 LocVT = MVT::i64;
1241 LocInfo = CCValAssign::BCvt;
1242 }
1243
1244 if (LocVT == MVT::v1i64 ||
1245 LocVT == MVT::v2i32 ||
1246 LocVT == MVT::v4i16 ||
1247 LocVT == MVT::v8i8 ||
1248 LocVT == MVT::v2f32) {
1249 LocVT = MVT::f64;
1250 LocInfo = CCValAssign::BCvt;
1251 }
1252
1253 if (LocVT == MVT::v2i64 ||
1254 LocVT == MVT::v4i32 ||
1255 LocVT == MVT::v8i16 ||
1256 LocVT == MVT::v16i8 ||
1257 LocVT == MVT::v4f32 ||
1258 LocVT == MVT::f128) {
1259 LocVT = MVT::v2f64;
1260 LocInfo = CCValAssign::BCvt;
1261 }
1262
1263 if (LocVT == MVT::v2f64) {
1264 static const MCPhysReg RegList1[] = {
1265 AArch64::Q4, AArch64::Q5
1266 };
1267 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
1268 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1269 return false;
1270 }
1271 }
1272
1273 if (LocVT == MVT::f32) {
1274 static const MCPhysReg RegList2[] = {
1275 AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11
1276 };
1277 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
1278 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1279 return false;
1280 }
1281 }
1282
1283 if (LocVT == MVT::f64) {
1284 static const MCPhysReg RegList3[] = {
1285 AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15
1286 };
1287 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
1288 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1289 return false;
1290 }
1291 }
1292
1293 if (LocVT == MVT::i8 ||
1294 LocVT == MVT::i16 ||
1295 LocVT == MVT::i32) {
1296 LocVT = MVT::i64;
1297 if (ArgFlags.isSExt())
1298 LocInfo = CCValAssign::SExt;
1299 else if (ArgFlags.isZExt())
1300 LocInfo = CCValAssign::ZExt;
1301 else
1302 LocInfo = CCValAssign::AExt;
1303 }
1304
1305 if (LocVT == MVT::i64) {
1306 static const MCPhysReg RegList4[] = {
1307 AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28
1308 };
1309 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
1310 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1311 return false;
1312 }
1313 }
1314
1315 return true; // CC didn't match.
1316}
1317
1318
1319bool llvm::CC_AArch64_Preserve_None(unsigned ValNo, MVT ValVT,
1320 MVT LocVT, CCValAssign::LocInfo LocInfo,
1321 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1322
1323 if (State.isVarArg()) {
1324 if (State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetDarwin()) {
1325 if (!CC_AArch64_DarwinPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1326 return false;
1327 }
1328 }
1329
1330 if (State.isVarArg()) {
1331 if (State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1332 if (!CC_AArch64_Win64PCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1333 return false;
1334 }
1335 }
1336
1337 if (State.isVarArg()) {
1338 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1339 return false;
1340 }
1341
1342 if (LocVT == MVT::i32) {
1343 static const MCPhysReg RegList1[] = {
1344 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W9
1345 };
1346 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
1347 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1348 return false;
1349 }
1350 }
1351
1352 if (LocVT == MVT::i64) {
1353 static const MCPhysReg RegList2[] = {
1354 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X9
1355 };
1356 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
1357 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1358 return false;
1359 }
1360 }
1361
1362 if (!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1363 if (LocVT == MVT::i32) {
1364 if (unsigned Reg = State.AllocateReg(Reg: AArch64::W15)) {
1365 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1366 return false;
1367 }
1368 }
1369 }
1370
1371 if (!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()) {
1372 if (LocVT == MVT::i64) {
1373 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X15)) {
1374 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1375 return false;
1376 }
1377 }
1378 }
1379
1380 if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1381 return false;
1382
1383 return true; // CC didn't match.
1384}
1385
1386
1387bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT,
1388 MVT LocVT, CCValAssign::LocInfo LocInfo,
1389 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1390
1391 if (LocVT == MVT::iPTR) {
1392 LocVT = MVT::i64;
1393 LocInfo = CCValAssign::BCvt;
1394 }
1395
1396 if (LocVT == MVT::v2f32) {
1397 LocVT = MVT::v2i32;
1398 LocInfo = CCValAssign::BCvt;
1399 }
1400
1401 if (LocVT == MVT::v2f64 ||
1402 LocVT == MVT::v4f32) {
1403 LocVT = MVT::v2i64;
1404 LocInfo = CCValAssign::BCvt;
1405 }
1406
1407 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1408 if (LocVT == MVT::v2i32 ||
1409 LocVT == MVT::v2f32 ||
1410 LocVT == MVT::v4i16 ||
1411 LocVT == MVT::v4f16 ||
1412 LocVT == MVT::v4bf16 ||
1413 LocVT == MVT::v8i8) {
1414 LocVT = MVT::f64;
1415 LocInfo = CCValAssign::BCvt;
1416 }
1417 }
1418
1419 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1420 if (LocVT == MVT::v2i64 ||
1421 LocVT == MVT::v2f64 ||
1422 LocVT == MVT::v4i32 ||
1423 LocVT == MVT::v4f32 ||
1424 LocVT == MVT::v8i16 ||
1425 LocVT == MVT::v8f16 ||
1426 LocVT == MVT::v8bf16 ||
1427 LocVT == MVT::v16i8) {
1428 LocVT = MVT::f128;
1429 LocInfo = CCValAssign::BCvt;
1430 }
1431 }
1432
1433 if (ArgFlags.isInReg()) {
1434 if (LocVT == MVT::i64) {
1435 if (ArgFlags.isSRet()) {
1436 if (LocVT == MVT::i64) {
1437 static const MCPhysReg RegList1[] = {
1438 AArch64::X0, AArch64::X1
1439 };
1440 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
1441 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1442 return false;
1443 }
1444 }
1445 }
1446 }
1447 }
1448
1449 if (ArgFlags.isSRet()) {
1450 if (LocVT == MVT::i64) {
1451 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X8)) {
1452 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1453 return false;
1454 }
1455 }
1456 }
1457
1458 if (ArgFlags.isByVal()) {
1459 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, MinSize: 8, MinAlign: Align(8), ArgFlags);
1460 return false;
1461 }
1462
1463 if (ArgFlags.isSwiftSelf()) {
1464 if (LocVT == MVT::i64) {
1465 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X20)) {
1466 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1467 return false;
1468 }
1469 }
1470 }
1471
1472 if (ArgFlags.isSwiftError()) {
1473 if (LocVT == MVT::i64) {
1474 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X21)) {
1475 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1476 return false;
1477 }
1478 }
1479 }
1480
1481 if (ArgFlags.isSwiftAsync()) {
1482 if (LocVT == MVT::i64) {
1483 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X22)) {
1484 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1485 return false;
1486 }
1487 }
1488 }
1489
1490 if (ArgFlags.isInConsecutiveRegs()) {
1491 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1492 return false;
1493 }
1494
1495 if (LocVT == MVT::nxv16i8 ||
1496 LocVT == MVT::nxv8i16 ||
1497 LocVT == MVT::nxv4i32 ||
1498 LocVT == MVT::nxv2i64 ||
1499 LocVT == MVT::nxv2f16 ||
1500 LocVT == MVT::nxv4f16 ||
1501 LocVT == MVT::nxv8f16 ||
1502 LocVT == MVT::nxv2bf16 ||
1503 LocVT == MVT::nxv4bf16 ||
1504 LocVT == MVT::nxv8bf16 ||
1505 LocVT == MVT::nxv2f32 ||
1506 LocVT == MVT::nxv4f32 ||
1507 LocVT == MVT::nxv2f64) {
1508 static const MCPhysReg RegList2[] = {
1509 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
1510 };
1511 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
1512 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1513 return false;
1514 }
1515 }
1516
1517 if (LocVT == MVT::nxv16i8 ||
1518 LocVT == MVT::nxv8i16 ||
1519 LocVT == MVT::nxv4i32 ||
1520 LocVT == MVT::nxv2i64 ||
1521 LocVT == MVT::nxv2f16 ||
1522 LocVT == MVT::nxv4f16 ||
1523 LocVT == MVT::nxv8f16 ||
1524 LocVT == MVT::nxv2bf16 ||
1525 LocVT == MVT::nxv4bf16 ||
1526 LocVT == MVT::nxv8bf16 ||
1527 LocVT == MVT::nxv2f32 ||
1528 LocVT == MVT::nxv4f32 ||
1529 LocVT == MVT::nxv2f64) {
1530 LocVT = MVT::i64;
1531 LocInfo = CCValAssign::Indirect;
1532 }
1533
1534 if (LocVT == MVT::nxv1i1 ||
1535 LocVT == MVT::nxv2i1 ||
1536 LocVT == MVT::nxv4i1 ||
1537 LocVT == MVT::nxv8i1 ||
1538 LocVT == MVT::nxv16i1 ||
1539 LocVT == MVT::aarch64svcount) {
1540 static const MCPhysReg RegList3[] = {
1541 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
1542 };
1543 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
1544 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1545 return false;
1546 }
1547 }
1548
1549 if (LocVT == MVT::nxv1i1 ||
1550 LocVT == MVT::nxv2i1 ||
1551 LocVT == MVT::nxv4i1 ||
1552 LocVT == MVT::nxv8i1 ||
1553 LocVT == MVT::nxv16i1 ||
1554 LocVT == MVT::aarch64svcount) {
1555 LocVT = MVT::i64;
1556 LocInfo = CCValAssign::Indirect;
1557 }
1558
1559 if (LocVT == MVT::i1 ||
1560 LocVT == MVT::i8 ||
1561 LocVT == MVT::i16) {
1562 LocVT = MVT::i32;
1563 if (ArgFlags.isSExt())
1564 LocInfo = CCValAssign::SExt;
1565 else if (ArgFlags.isZExt())
1566 LocInfo = CCValAssign::ZExt;
1567 else
1568 LocInfo = CCValAssign::AExt;
1569 }
1570
1571 if (LocVT == MVT::i32) {
1572 static const MCPhysReg RegList4[] = {
1573 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
1574 };
1575 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
1576 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1577 return false;
1578 }
1579 }
1580
1581 if (LocVT == MVT::i64) {
1582 if (ArgFlags.isSplit()) {
1583 static const MCPhysReg RegList5[] = {
1584 AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
1585 };
1586 static const MCPhysReg RegList6[] = {
1587 AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
1588 };
1589 if (unsigned Reg = State.AllocateReg(Regs: RegList5, ShadowRegs: RegList6)) {
1590 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1591 return false;
1592 }
1593 }
1594 }
1595
1596 if (LocVT == MVT::i64) {
1597 if (ArgFlags.isSplit()) {
1598 static const MCPhysReg ShadowRegList7[] = {
1599 AArch64::X7
1600 };
1601 int64_t Offset8 = State.AllocateStack(Size: 8, Alignment: Align(16), ShadowRegs: ShadowRegList7);
1602 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset8, LocVT, HTP: LocInfo));
1603 return false;
1604 }
1605 }
1606
1607 if (LocVT == MVT::i64) {
1608 static const MCPhysReg RegList9[] = {
1609 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1610 };
1611 if (unsigned Reg = State.AllocateReg(Regs: RegList9)) {
1612 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1613 return false;
1614 }
1615 }
1616
1617 if (LocVT == MVT::f16) {
1618 static const MCPhysReg RegList10[] = {
1619 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1620 };
1621 if (unsigned Reg = State.AllocateReg(Regs: RegList10)) {
1622 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1623 return false;
1624 }
1625 }
1626
1627 if (LocVT == MVT::bf16) {
1628 static const MCPhysReg RegList11[] = {
1629 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1630 };
1631 if (unsigned Reg = State.AllocateReg(Regs: RegList11)) {
1632 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1633 return false;
1634 }
1635 }
1636
1637 if (LocVT == MVT::f32) {
1638 static const MCPhysReg RegList12[] = {
1639 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
1640 };
1641 if (unsigned Reg = State.AllocateReg(Regs: RegList12)) {
1642 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1643 return false;
1644 }
1645 }
1646
1647 if (LocVT == MVT::f64) {
1648 static const MCPhysReg RegList13[] = {
1649 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1650 };
1651 if (unsigned Reg = State.AllocateReg(Regs: RegList13)) {
1652 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1653 return false;
1654 }
1655 }
1656
1657 if (LocVT == MVT::v1i64 ||
1658 LocVT == MVT::v2i32 ||
1659 LocVT == MVT::v4i16 ||
1660 LocVT == MVT::v8i8 ||
1661 LocVT == MVT::v1f64 ||
1662 LocVT == MVT::v2f32 ||
1663 LocVT == MVT::v4f16 ||
1664 LocVT == MVT::v4bf16) {
1665 static const MCPhysReg RegList14[] = {
1666 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1667 };
1668 if (unsigned Reg = State.AllocateReg(Regs: RegList14)) {
1669 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1670 return false;
1671 }
1672 }
1673
1674 if (LocVT == MVT::f128 ||
1675 LocVT == MVT::v2i64 ||
1676 LocVT == MVT::v4i32 ||
1677 LocVT == MVT::v8i16 ||
1678 LocVT == MVT::v16i8 ||
1679 LocVT == MVT::v4f32 ||
1680 LocVT == MVT::v2f64 ||
1681 LocVT == MVT::v8f16 ||
1682 LocVT == MVT::v8bf16) {
1683 static const MCPhysReg RegList15[] = {
1684 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1685 };
1686 if (unsigned Reg = State.AllocateReg(Regs: RegList15)) {
1687 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1688 return false;
1689 }
1690 }
1691
1692 if (LocVT == MVT::i1 ||
1693 LocVT == MVT::i8 ||
1694 LocVT == MVT::i16 ||
1695 LocVT == MVT::f16 ||
1696 LocVT == MVT::bf16) {
1697 int64_t Offset16 = State.AllocateStack(Size: 8, Alignment: Align(8));
1698 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset16, LocVT, HTP: LocInfo));
1699 return false;
1700 }
1701
1702 if (LocVT == MVT::i32 ||
1703 LocVT == MVT::f32) {
1704 int64_t Offset17 = State.AllocateStack(Size: 8, Alignment: Align(8));
1705 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset17, LocVT, HTP: LocInfo));
1706 return false;
1707 }
1708
1709 if (LocVT == MVT::i64 ||
1710 LocVT == MVT::f64 ||
1711 LocVT == MVT::v1f64 ||
1712 LocVT == MVT::v2f32 ||
1713 LocVT == MVT::v1i64 ||
1714 LocVT == MVT::v2i32 ||
1715 LocVT == MVT::v4i16 ||
1716 LocVT == MVT::v8i8 ||
1717 LocVT == MVT::v4f16 ||
1718 LocVT == MVT::v4bf16) {
1719 int64_t Offset18 = State.AllocateStack(Size: 8, Alignment: Align(8));
1720 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset18, LocVT, HTP: LocInfo));
1721 return false;
1722 }
1723
1724 if (LocVT == MVT::f128 ||
1725 LocVT == MVT::v2i64 ||
1726 LocVT == MVT::v4i32 ||
1727 LocVT == MVT::v8i16 ||
1728 LocVT == MVT::v16i8 ||
1729 LocVT == MVT::v4f32 ||
1730 LocVT == MVT::v2f64 ||
1731 LocVT == MVT::v8f16 ||
1732 LocVT == MVT::v8bf16) {
1733 int64_t Offset19 = State.AllocateStack(Size: 16, Alignment: Align(16));
1734 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset19, LocVT, HTP: LocInfo));
1735 return false;
1736 }
1737
1738 return true; // CC didn't match.
1739}
1740
1741
1742bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT,
1743 MVT LocVT, CCValAssign::LocInfo LocInfo,
1744 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1745
1746 if (LocVT == MVT::i64) {
1747 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X15)) {
1748 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1749 return false;
1750 }
1751 }
1752
1753 return true; // CC didn't match.
1754}
1755
1756
1757bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
1758 MVT LocVT, CCValAssign::LocInfo LocInfo,
1759 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1760
1761 if (LocVT == MVT::f16 ||
1762 LocVT == MVT::bf16) {
1763 LocVT = MVT::i16;
1764 LocInfo = CCValAssign::BCvt;
1765 }
1766
1767 if (LocVT == MVT::f32) {
1768 LocVT = MVT::i32;
1769 LocInfo = CCValAssign::BCvt;
1770 }
1771
1772 if (LocVT == MVT::f64) {
1773 LocVT = MVT::i64;
1774 LocInfo = CCValAssign::BCvt;
1775 }
1776
1777 if (!CC_AArch64_Win64PCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1778 return false;
1779
1780 return true; // CC didn't match.
1781}
1782
1783
1784bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
1785 MVT LocVT, CCValAssign::LocInfo LocInfo,
1786 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1787
1788 if (LocVT == MVT::iPTR) {
1789 LocVT = MVT::i64;
1790 LocInfo = CCValAssign::BCvt;
1791 }
1792
1793 if (LocVT == MVT::v2f32) {
1794 LocVT = MVT::v2i32;
1795 LocInfo = CCValAssign::BCvt;
1796 }
1797
1798 if (LocVT == MVT::v2f64 ||
1799 LocVT == MVT::v4f32) {
1800 LocVT = MVT::v2i64;
1801 LocInfo = CCValAssign::BCvt;
1802 }
1803
1804 if (ArgFlags.isInConsecutiveRegs()) {
1805 if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1806 return false;
1807 }
1808
1809 if (ArgFlags.isSwiftError()) {
1810 if (LocVT == MVT::i64) {
1811 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X21)) {
1812 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1813 return false;
1814 }
1815 }
1816 }
1817
1818 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1819 if (LocVT == MVT::v2i32 ||
1820 LocVT == MVT::v2f32 ||
1821 LocVT == MVT::v4i16 ||
1822 LocVT == MVT::v4f16 ||
1823 LocVT == MVT::v4bf16 ||
1824 LocVT == MVT::v8i8) {
1825 LocVT = MVT::f64;
1826 LocInfo = CCValAssign::BCvt;
1827 }
1828 }
1829
1830 if (State.getMachineFunction().getDataLayout().isBigEndian()) {
1831 if (LocVT == MVT::v2i64 ||
1832 LocVT == MVT::v2f64 ||
1833 LocVT == MVT::v4i32 ||
1834 LocVT == MVT::v4f32 ||
1835 LocVT == MVT::v8i16 ||
1836 LocVT == MVT::v8f16 ||
1837 LocVT == MVT::v8bf16 ||
1838 LocVT == MVT::v16i8) {
1839 LocVT = MVT::f128;
1840 LocInfo = CCValAssign::BCvt;
1841 }
1842 }
1843
1844 if (LocVT == MVT::i1 ||
1845 LocVT == MVT::i8 ||
1846 LocVT == MVT::i16) {
1847 LocVT = MVT::i32;
1848 if (ArgFlags.isSExt())
1849 LocInfo = CCValAssign::SExt;
1850 else if (ArgFlags.isZExt())
1851 LocInfo = CCValAssign::ZExt;
1852 else
1853 LocInfo = CCValAssign::AExt;
1854 }
1855
1856 if (LocVT == MVT::i32) {
1857 static const MCPhysReg RegList1[] = {
1858 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
1859 };
1860 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
1861 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1862 return false;
1863 }
1864 }
1865
1866 if (LocVT == MVT::i64) {
1867 static const MCPhysReg RegList2[] = {
1868 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1869 };
1870 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
1871 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1872 return false;
1873 }
1874 }
1875
1876 if (LocVT == MVT::f16) {
1877 static const MCPhysReg RegList3[] = {
1878 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1879 };
1880 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
1881 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1882 return false;
1883 }
1884 }
1885
1886 if (LocVT == MVT::bf16) {
1887 static const MCPhysReg RegList4[] = {
1888 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
1889 };
1890 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
1891 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1892 return false;
1893 }
1894 }
1895
1896 if (LocVT == MVT::f32) {
1897 static const MCPhysReg RegList5[] = {
1898 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
1899 };
1900 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
1901 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1902 return false;
1903 }
1904 }
1905
1906 if (LocVT == MVT::f64) {
1907 static const MCPhysReg RegList6[] = {
1908 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1909 };
1910 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
1911 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1912 return false;
1913 }
1914 }
1915
1916 if (LocVT == MVT::v1i64 ||
1917 LocVT == MVT::v2i32 ||
1918 LocVT == MVT::v4i16 ||
1919 LocVT == MVT::v8i8 ||
1920 LocVT == MVT::v1f64 ||
1921 LocVT == MVT::v2f32 ||
1922 LocVT == MVT::v4f16 ||
1923 LocVT == MVT::v4bf16) {
1924 static const MCPhysReg RegList7[] = {
1925 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1926 };
1927 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
1928 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1929 return false;
1930 }
1931 }
1932
1933 if (LocVT == MVT::f128 ||
1934 LocVT == MVT::v2i64 ||
1935 LocVT == MVT::v4i32 ||
1936 LocVT == MVT::v8i16 ||
1937 LocVT == MVT::v16i8 ||
1938 LocVT == MVT::v4f32 ||
1939 LocVT == MVT::v2f64 ||
1940 LocVT == MVT::v8f16 ||
1941 LocVT == MVT::v8bf16) {
1942 static const MCPhysReg RegList8[] = {
1943 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1944 };
1945 if (unsigned Reg = State.AllocateReg(Regs: RegList8)) {
1946 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1947 return false;
1948 }
1949 }
1950
1951 if (LocVT == MVT::nxv16i8 ||
1952 LocVT == MVT::nxv8i16 ||
1953 LocVT == MVT::nxv4i32 ||
1954 LocVT == MVT::nxv2i64 ||
1955 LocVT == MVT::nxv2f16 ||
1956 LocVT == MVT::nxv4f16 ||
1957 LocVT == MVT::nxv8f16 ||
1958 LocVT == MVT::nxv2bf16 ||
1959 LocVT == MVT::nxv4bf16 ||
1960 LocVT == MVT::nxv8bf16 ||
1961 LocVT == MVT::nxv2f32 ||
1962 LocVT == MVT::nxv4f32 ||
1963 LocVT == MVT::nxv2f64) {
1964 static const MCPhysReg RegList9[] = {
1965 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
1966 };
1967 if (unsigned Reg = State.AllocateReg(Regs: RegList9)) {
1968 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1969 return false;
1970 }
1971 }
1972
1973 if (LocVT == MVT::nxv1i1 ||
1974 LocVT == MVT::nxv2i1 ||
1975 LocVT == MVT::nxv4i1 ||
1976 LocVT == MVT::nxv8i1 ||
1977 LocVT == MVT::nxv16i1 ||
1978 LocVT == MVT::aarch64svcount) {
1979 static const MCPhysReg RegList10[] = {
1980 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3
1981 };
1982 if (unsigned Reg = State.AllocateReg(Regs: RegList10)) {
1983 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1984 return false;
1985 }
1986 }
1987
1988 return true; // CC didn't match.
1989}
1990
1991
1992bool llvm::RetCC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT,
1993 MVT LocVT, CCValAssign::LocInfo LocInfo,
1994 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1995
1996 if (LocVT == MVT::i64) {
1997 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X11)) {
1998 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
1999 return false;
2000 }
2001 }
2002
2003 return true; // CC didn't match.
2004}
2005
2006
2007bool llvm::RetCC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT,
2008 MVT LocVT, CCValAssign::LocInfo LocInfo,
2009 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2010
2011 if (LocVT == MVT::x86mmx) {
2012 LocVT = MVT::i64;
2013 LocInfo = CCValAssign::BCvt;
2014 }
2015
2016 if (LocVT == MVT::f16) {
2017 static const MCPhysReg RegList1[] = {
2018 AArch64::H0, AArch64::H1
2019 };
2020 if (unsigned Reg = State.AllocateReg(Regs: RegList1)) {
2021 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2022 return false;
2023 }
2024 }
2025
2026 if (LocVT == MVT::f32) {
2027 static const MCPhysReg RegList2[] = {
2028 AArch64::S0, AArch64::S1
2029 };
2030 if (unsigned Reg = State.AllocateReg(Regs: RegList2)) {
2031 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2032 return false;
2033 }
2034 }
2035
2036 if (LocVT == MVT::f64) {
2037 static const MCPhysReg RegList3[] = {
2038 AArch64::D0, AArch64::D1
2039 };
2040 if (unsigned Reg = State.AllocateReg(Regs: RegList3)) {
2041 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2042 return false;
2043 }
2044 }
2045
2046 if (LocVT == MVT::f128) {
2047 static const MCPhysReg RegList4[] = {
2048 AArch64::Q0, AArch64::Q1
2049 };
2050 if (unsigned Reg = State.AllocateReg(Regs: RegList4)) {
2051 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2052 return false;
2053 }
2054 }
2055
2056 if (ArgFlags.isSwiftError()) {
2057 if (LocVT == MVT::i64) {
2058 if (unsigned Reg = State.AllocateReg(Reg: AArch64::X19)) {
2059 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2060 return false;
2061 }
2062 }
2063 }
2064
2065 if (LocVT == MVT::i1 ||
2066 LocVT == MVT::i8 ||
2067 LocVT == MVT::i16) {
2068 LocVT = MVT::i32;
2069 if (ArgFlags.isSExt())
2070 LocInfo = CCValAssign::SExt;
2071 else if (ArgFlags.isZExt())
2072 LocInfo = CCValAssign::ZExt;
2073 else
2074 LocInfo = CCValAssign::AExt;
2075 }
2076
2077 if (LocVT == MVT::i32) {
2078 static const MCPhysReg RegList5[] = {
2079 AArch64::W8, AArch64::W1, AArch64::W0
2080 };
2081 if (unsigned Reg = State.AllocateReg(Regs: RegList5)) {
2082 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2083 return false;
2084 }
2085 }
2086
2087 if (LocVT == MVT::i64) {
2088 static const MCPhysReg RegList6[] = {
2089 AArch64::X8, AArch64::X1, AArch64::X0
2090 };
2091 if (unsigned Reg = State.AllocateReg(Regs: RegList6)) {
2092 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2093 return false;
2094 }
2095 }
2096
2097 if (LocVT == MVT::v16i8 ||
2098 LocVT == MVT::v8i16 ||
2099 LocVT == MVT::v4i32 ||
2100 LocVT == MVT::v2i64 ||
2101 LocVT == MVT::v8f16 ||
2102 LocVT == MVT::v4f32 ||
2103 LocVT == MVT::v2f64) {
2104 static const MCPhysReg RegList7[] = {
2105 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3
2106 };
2107 if (unsigned Reg = State.AllocateReg(Regs: RegList7)) {
2108 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, RegNo: Reg, LocVT, HTP: LocInfo));
2109 return false;
2110 }
2111 }
2112
2113 return true; // CC didn't match.
2114}
2115
2116#else
2117
2118const MCRegister CC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X18, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2119const MCRegister CC_AArch64_Arm64EC_CFGuard_Check_ArgRegs[] = { AArch64::X10, AArch64::X11, AArch64::X9 };
2120const MCRegister CC_AArch64_Arm64EC_Thunk_ArgRegs[] = { AArch64::X4, AArch64::X8, AArch64::X9 };
2121const MCRegister CC_AArch64_Arm64EC_Thunk_Native_ArgRegs[] = { AArch64::X9 };
2122const MCRegister CC_AArch64_Arm64EC_VarArg_ArgRegs[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X8 };
2123const MCRegister CC_AArch64_DarwinPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8 };
2124const MCRegister CC_AArch64_DarwinPCS_ILP32_VarArg_ArgRegs[] = { 0 };
2125const MCRegister CC_AArch64_DarwinPCS_VarArg_ArgRegs[] = { 0 };
2126const MCRegister CC_AArch64_GHC_ArgRegs[] = { AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::Q4, AArch64::Q5, AArch64::S10, AArch64::S11, AArch64::S8, AArch64::S9, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28 };
2127const MCRegister CC_AArch64_Preserve_None_ArgRegs[] = { AArch64::W0, AArch64::W1, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W2, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W9, AArch64::X0, AArch64::X1, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X2, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X9 };
2128const MCRegister CC_AArch64_Win64PCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2129const MCRegister CC_AArch64_Win64_CFGuard_Check_ArgRegs[] = { AArch64::X15 };
2130const MCRegister CC_AArch64_Win64_VarArg_ArgRegs[] = { 0 };
2131const MCRegister RetCC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 };
2132const MCRegister RetCC_AArch64_Arm64EC_CFGuard_Check_ArgRegs[] = { AArch64::X11 };
2133const MCRegister RetCC_AArch64_Arm64EC_Thunk_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::H0, AArch64::H1, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::S0, AArch64::S1, AArch64::W0, AArch64::W1, AArch64::W8, AArch64::X0, AArch64::X1, AArch64::X8 };
2134
2135// Registers used by Swift.
2136const MCRegister CC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2137const MCRegister CC_AArch64_Arm64EC_Thunk_Swift_ArgRegs[] = { AArch64::X19, AArch64::X20, AArch64::X21 };
2138const MCRegister CC_AArch64_DarwinPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2139const MCRegister CC_AArch64_Win64PCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 };
2140const MCRegister RetCC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X21 };
2141const MCRegister RetCC_AArch64_Arm64EC_Thunk_Swift_ArgRegs[] = { AArch64::X19 };
2142
2143#endif // CC_REGISTER_LIST
2144